INTC changes to consume for RISCV

-----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmXYX5ATHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoapHD/9wNuONAuqnPA9s087kixWBCnQzR8b/
 5LvXhgoNufi2U34Pj1PYXjf3NNv0ALyiF6VOFnPeEFVDTB3CUIUqA6zw1aHYXHRd
 aet4sQ3+j5Mm2Tive23MYWIuvwNu/sZkyVuIVC0GTeUE7VUurKeM3ruqtD73NSMe
 KUOwPheEx9b8oiBTQInNtPh7jalBlIFJL0o0t2rIjAonwviTl5f34wiUecT3dkx3
 Bp6pgsweEThy6ZFq11n+2xRNw4vVEfIarFNV7BYGgM/srmGsay648i4G7nTISXtb
 YVJO2JS+TmR26y90STM5R7xfDkS3XwaZKRsSdLckEIc+8HWKzoGkf+1ZLk3CMXX3
 V6YDGbiUOeI2pVu2U3Qifux8s1ALrUtD/6E84RnyAXq804MNkTGzcGYOIkH1hYZR
 Xx+wPPzzL4gHybveve6la5Yx0seTRU1smFLpFKGVr5qr8IniuYNQ5XZhSiGhqTzO
 LgcTBuFWrKakV4quYVCOtIWduj0ObJMGh6ZJfd6oIEFUVe9TxzhTd0FEoDLxbgRv
 pLUH3vjw9RxeVjxg8mfxThnHainW4JcWJZag0SYXSx9Sq+WfLSntQ8X+JExY5sPe
 ZiF3V5y4Pe6+iAq9D7UpIRBFEzxpRtgc3JwQn3qh70kszWLumncL9P3tf1ATZOzC
 nPpbfAvtbTG/wg==
 =EzZe
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmXwYkYTHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRAuExnzX7sYiYeRD/91IW3J1E8sgr+IgtQFsNAjq/7YdKBN
 E4hlBfqZe1rs37G6QshUqsU2YVTSfjYWYl4fx/v1++3mnLrgAw5cXQYGzCaryy4q
 4nSXwjYCKPJMDb8o+f4ikMOOpimou7kEKRwN6fXuYMGpWwD7qVqJFh0V6WfeYMEg
 HPcLLJl1sKGPG+heIn9tS2SffCC0NsKTdshkM+6LvJJqzpVcHvog5nIxaPmft9Th
 H4ReZ/QsPQXSuK5eUz4jIbsPLJw4k4lGaBpKYOdPhXjlimdJ7m3/d//fbVOuoFNz
 8Wcqge1tEyNeh0nZ0t69okeAQAVVZ82xVlre9ScGbmLrPBP8gu+znF21mcbzMojY
 e7tlg/3ALl/mLCm2l8SHuQaYUs1VJcd+19si2+itD9zYptK/3KLDRdnxzW3lVrjE
 0JikzWQGZNGzdv3aOcTgl+7AprvmLAF3G01N27yQopbU/weRNHwCvJQiIa+qhzrX
 a1+Q/yHRKqeJmP4XIbfdV3kzsmfWYEuFjzkXQGlHDHqqyklbe+Rrs+Hvvg4pf20c
 0/cKxONd2nflsB4orGsJ7V06Y/42vfW5Un1RXbg3+K2pIjSox6aaAWMshKOifchc
 9TG/PB5ydfW5xN+tHZkK7sIaNHQFDwSiDZuDrws1SAXvN1OhywZnUjKdlj5rCQnW
 5SJh26IThF4MHQ==
 =+Ke1
 -----END PGP SIGNATURE-----

Merge tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip into for-next

INTC changes to consume for RISCV

* tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  irqchip/riscv-intc: Allow large non-standard interrupt number
This commit is contained in:
Palmer Dabbelt 2024-03-12 07:10:08 -07:00
commit b8e00bdf25
2 changed files with 87 additions and 13 deletions

View File

@ -17,17 +17,19 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/smp.h>
#include <linux/soc/andes/irq.h>
static struct irq_domain *intc_domain;
static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG;
static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
if (unlikely(cause >= BITS_PER_LONG))
panic("unexpected interrupt cause");
generic_handle_domain_irq(intc_domain, cause);
if (generic_handle_domain_irq(intc_domain, cause))
pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause);
}
/*
@ -47,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}
static void andes_intc_irq_mask(struct irq_data *d)
{
/*
* Andes specific S-mode local interrupt causes (hwirq)
* are defined as (256 + n) and controlled by n-th bit
* of SLIE.
*/
unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
if (d->hwirq < ANDES_SLI_CAUSE_BASE)
csr_clear(CSR_IE, mask);
else
csr_clear(ANDES_CSR_SLIE, mask);
}
static void andes_intc_irq_unmask(struct irq_data *d)
{
unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
if (d->hwirq < ANDES_SLI_CAUSE_BASE)
csr_set(CSR_IE, mask);
else
csr_set(ANDES_CSR_SLIE, mask);
}
static void riscv_intc_irq_eoi(struct irq_data *d)
{
/*
@ -70,12 +97,21 @@ static struct irq_chip riscv_intc_chip = {
.irq_eoi = riscv_intc_irq_eoi,
};
static struct irq_chip andes_intc_chip = {
.name = "RISC-V INTC",
.irq_mask = andes_intc_irq_mask,
.irq_unmask = andes_intc_irq_unmask,
.irq_eoi = riscv_intc_irq_eoi,
};
static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct irq_chip *chip = d->host_data;
irq_set_percpu_devid(irq);
irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
handle_percpu_devid_irq, NULL, NULL);
irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
NULL, NULL);
return 0;
}
@ -93,6 +129,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
if (ret)
return ret;
/*
* Only allow hwirq for which we have corresponding standard or
* custom interrupt enable register.
*/
if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
(hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
return -EINVAL;
for (i = 0; i < nr_irqs; i++) {
ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
if (ret)
@ -113,12 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
return intc_domain->fwnode;
}
static int __init riscv_intc_init_common(struct fwnode_handle *fn)
static int __init riscv_intc_init_common(struct fwnode_handle *fn,
struct irq_chip *chip)
{
int rc;
intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
&riscv_intc_domain_ops, NULL);
intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@ -132,7 +176,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
if (riscv_intc_custom_nr_irqs) {
pr_info("%d custom local interrupts mapped\n",
riscv_intc_custom_nr_irqs);
}
return 0;
}
@ -140,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
static int __init riscv_intc_init(struct device_node *node,
struct device_node *parent)
{
int rc;
struct irq_chip *chip = &riscv_intc_chip;
unsigned long hartid;
int rc;
rc = riscv_of_parent_hartid(node, &hartid);
if (rc < 0) {
@ -166,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node,
return 0;
}
return riscv_intc_init_common(of_node_to_fwnode(node));
if (of_device_is_compatible(node, "andestech,cpu-intc")) {
riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
chip = &andes_intc_chip;
}
return riscv_intc_init_common(of_node_to_fwnode(node), chip);
}
IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
#ifdef CONFIG_ACPI
@ -196,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
return -ENOMEM;
}
return riscv_intc_init_common(fn);
return riscv_intc_init_common(fn, &riscv_intc_chip);
}
IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,

View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2023 Andes Technology Corporation
*/
#ifndef __ANDES_IRQ_H
#define __ANDES_IRQ_H
/* Andes PMU irq number */
#define ANDES_RV_IRQ_PMOVI 18
#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
#define ANDES_SLI_CAUSE_BASE 256
/* Andes PMU related registers */
#define ANDES_CSR_SLIE 0x9c4
#define ANDES_CSR_SLIP 0x9c5
#define ANDES_CSR_SCOUNTEROF 0x9d4
#endif /* __ANDES_IRQ_H */