drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation
Split out the PLL parameter->frequency conversion logic for each type of PLL for symmetry with their corresponding inverse conversion functions. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-12-imre.deak@intel.com
This commit is contained in:
Imre Deak
parent
350ab42f97
commit
b953eb2153
drivers/gpu/drm/i915/display
@ -1350,13 +1350,15 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
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static void gen11_dsi_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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intel_dsc_get_config(encoder, pipe_config);
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/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
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pipe_config->port_clock = intel_dpll_get_freq(encoder, pipe_config);
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pipe_config->port_clock = intel_dpll_get_freq(i915,
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pipe_config->shared_dpll);
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pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
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if (intel_dsi->dual_link)
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@ -1383,8 +1383,8 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
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pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
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encoder->port);
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else
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pipe_config->port_clock = intel_dpll_get_freq(encoder,
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pipe_config);
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pipe_config->port_clock =
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intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
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ddi_dotclock_get(pipe_config);
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}
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@ -1052,23 +1052,6 @@ static bool hsw_get_dpll(struct intel_atomic_state *state,
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return true;
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}
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static int hsw_ddi_clock_get(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_shared_dpll *pll = pipe_config->shared_dpll;
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switch (pll->info->id) {
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case DPLL_ID_WRPLL1:
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case DPLL_ID_WRPLL2:
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return hsw_ddi_wrpll_get_freq(dev_priv, pll);
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case DPLL_ID_SPLL:
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return hsw_ddi_spll_get_freq(dev_priv, pll);
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default:
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return hsw_ddi_lcpll_get_freq(dev_priv, pll);
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}
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}
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static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
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const struct intel_dpll_hw_state *hw_state)
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{
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@ -1080,12 +1063,14 @@ static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
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.enable = hsw_ddi_wrpll_enable,
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.disable = hsw_ddi_wrpll_disable,
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.get_hw_state = hsw_ddi_wrpll_get_hw_state,
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.get_freq = hsw_ddi_wrpll_get_freq,
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};
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static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
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.enable = hsw_ddi_spll_enable,
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.disable = hsw_ddi_spll_disable,
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.get_hw_state = hsw_ddi_spll_get_hw_state,
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.get_freq = hsw_ddi_spll_get_freq,
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};
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static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
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@ -1109,6 +1094,7 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
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.enable = hsw_ddi_lcpll_enable,
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.disable = hsw_ddi_lcpll_disable,
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.get_hw_state = hsw_ddi_lcpll_get_hw_state,
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.get_freq = hsw_ddi_lcpll_get_freq,
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};
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static const struct dpll_info hsw_plls[] = {
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@ -1574,8 +1560,10 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
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return true;
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}
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static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
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static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
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int ref_clock = 24000;
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u32 p0, p1, p2, dco_freq;
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@ -1670,6 +1658,40 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
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return true;
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}
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static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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int link_clock = 0;
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switch ((pll->state.hw_state.ctrl1 &
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DPLL_CTRL1_LINK_RATE_MASK(0)) >>
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DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
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case DPLL_CTRL1_LINK_RATE_810:
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link_clock = 81000;
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break;
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case DPLL_CTRL1_LINK_RATE_1080:
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link_clock = 108000;
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break;
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case DPLL_CTRL1_LINK_RATE_1350:
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link_clock = 135000;
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break;
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case DPLL_CTRL1_LINK_RATE_1620:
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link_clock = 162000;
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break;
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case DPLL_CTRL1_LINK_RATE_2160:
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link_clock = 216000;
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break;
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case DPLL_CTRL1_LINK_RATE_2700:
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link_clock = 270000;
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break;
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default:
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drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
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break;
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}
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return link_clock * 2;
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}
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static bool skl_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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@ -1719,50 +1741,17 @@ static bool skl_get_dpll(struct intel_atomic_state *state,
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return true;
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}
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static int skl_ddi_clock_get(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state)
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static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
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int link_clock;
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/*
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* ctrl1 register is already shifted for each pll, just use 0 to get
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* the internal shift for each field
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*/
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if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
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link_clock = skl_calc_wrpll_link(pll_state);
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} else {
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link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
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link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
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switch (link_clock) {
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case DPLL_CTRL1_LINK_RATE_810:
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link_clock = 81000;
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break;
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case DPLL_CTRL1_LINK_RATE_1080:
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link_clock = 108000;
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break;
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case DPLL_CTRL1_LINK_RATE_1350:
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link_clock = 135000;
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break;
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case DPLL_CTRL1_LINK_RATE_1620:
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link_clock = 162000;
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break;
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case DPLL_CTRL1_LINK_RATE_2160:
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link_clock = 216000;
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break;
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case DPLL_CTRL1_LINK_RATE_2700:
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link_clock = 270000;
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break;
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default:
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drm_WARN(encoder->base.dev, 1,
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"Unsupported link rate\n");
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break;
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}
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link_clock *= 2;
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}
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return link_clock;
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if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
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return skl_ddi_wrpll_get_freq(i915, pll);
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else
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return skl_ddi_lcpll_get_freq(i915, pll);
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}
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static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -1779,12 +1768,14 @@ static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
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.enable = skl_ddi_pll_enable,
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.disable = skl_ddi_pll_disable,
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.get_hw_state = skl_ddi_pll_get_hw_state,
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.get_freq = skl_ddi_pll_get_freq,
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};
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static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
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.enable = skl_ddi_dpll0_enable,
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.disable = skl_ddi_dpll0_disable,
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.get_hw_state = skl_ddi_dpll0_get_hw_state,
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.get_freq = skl_ddi_pll_get_freq,
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};
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static const struct dpll_info skl_plls[] = {
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@ -2190,11 +2181,10 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
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return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
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}
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static int bxt_ddi_clock_get(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state)
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static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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struct intel_dpll_hw_state *pll_state =
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&crtc_state->shared_dpll->state.hw_state;
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const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
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struct dpll clock;
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clock.m1 = 2;
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@ -2264,6 +2254,7 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
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.enable = bxt_ddi_pll_enable,
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.disable = bxt_ddi_pll_disable,
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.get_hw_state = bxt_ddi_pll_get_hw_state,
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.get_freq = bxt_ddi_pll_get_freq,
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};
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static const struct dpll_info bxt_plls[] = {
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@ -2608,9 +2599,10 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
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return true;
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}
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static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
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struct intel_dpll_hw_state *pll_state)
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static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
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const struct intel_shared_dpll *pll)
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{
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const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
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u32 p0, p1, p2, dco_freq, ref_clock;
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p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
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@ -2709,6 +2701,44 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
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return true;
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}
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static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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int link_clock = 0;
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switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) {
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case DPLL_CFGCR0_LINK_RATE_810:
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link_clock = 81000;
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break;
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case DPLL_CFGCR0_LINK_RATE_1080:
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link_clock = 108000;
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break;
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case DPLL_CFGCR0_LINK_RATE_1350:
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link_clock = 135000;
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break;
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case DPLL_CFGCR0_LINK_RATE_1620:
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link_clock = 162000;
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break;
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case DPLL_CFGCR0_LINK_RATE_2160:
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link_clock = 216000;
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break;
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case DPLL_CFGCR0_LINK_RATE_2700:
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link_clock = 270000;
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break;
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case DPLL_CFGCR0_LINK_RATE_3240:
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link_clock = 324000;
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break;
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case DPLL_CFGCR0_LINK_RATE_4050:
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link_clock = 405000;
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break;
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default:
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drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
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break;
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}
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return link_clock * 2;
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}
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static bool cnl_get_dpll(struct intel_atomic_state *state,
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struct intel_crtc *crtc,
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struct intel_encoder *encoder)
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@ -2758,51 +2788,13 @@ static bool cnl_get_dpll(struct intel_atomic_state *state,
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return true;
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}
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static int cnl_ddi_clock_get(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
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int link_clock;
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if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
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link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
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} else {
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link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
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switch (link_clock) {
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case DPLL_CFGCR0_LINK_RATE_810:
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link_clock = 81000;
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break;
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case DPLL_CFGCR0_LINK_RATE_1080:
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link_clock = 108000;
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break;
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case DPLL_CFGCR0_LINK_RATE_1350:
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link_clock = 135000;
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break;
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case DPLL_CFGCR0_LINK_RATE_1620:
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link_clock = 162000;
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break;
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case DPLL_CFGCR0_LINK_RATE_2160:
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link_clock = 216000;
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break;
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case DPLL_CFGCR0_LINK_RATE_2700:
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link_clock = 270000;
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break;
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case DPLL_CFGCR0_LINK_RATE_3240:
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link_clock = 324000;
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break;
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case DPLL_CFGCR0_LINK_RATE_4050:
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link_clock = 405000;
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break;
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default:
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drm_WARN(&dev_priv->drm, 1, "Unsupported link rate\n");
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break;
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}
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link_clock *= 2;
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}
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return link_clock;
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if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE)
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return cnl_ddi_wrpll_get_freq(i915, pll);
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else
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return cnl_ddi_lcpll_get_freq(i915, pll);
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}
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static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
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@ -2818,6 +2810,7 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
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.enable = cnl_ddi_pll_enable,
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.disable = cnl_ddi_pll_disable,
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.get_hw_state = cnl_ddi_pll_get_hw_state,
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.get_freq = cnl_ddi_pll_get_freq,
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};
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static const struct dpll_info cnl_plls[] = {
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@ -2979,6 +2972,18 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
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return true;
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}
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static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
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{
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/*
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* The PLL outputs multiple frequencies at the same time, selection is
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* made at DDI clock mux level.
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*/
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drm_WARN_ON(&i915->drm, 1);
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return 0;
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}
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static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder,
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struct intel_dpll_hw_state *pll_state)
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@ -3317,9 +3322,10 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
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return true;
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}
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static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
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const struct intel_dpll_hw_state *pll_state)
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static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
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const struct intel_shared_dpll *pll)
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{
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const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
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u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
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u64 tmp;
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@ -3388,19 +3394,6 @@ static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
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return tmp;
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}
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static int icl_ddi_clock_get(struct intel_encoder *encoder,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
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enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
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if (intel_phy_is_combo(dev_priv, phy))
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return cnl_calc_wrpll_link(dev_priv, pll_state);
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else
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return icl_calc_mg_pll_link(dev_priv, pll_state);
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}
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/**
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* icl_set_active_port_dpll - select the active port DPLL for a given CRTC
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* @crtc_state: state for the CRTC to select the DPLL for
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@ -3485,6 +3478,12 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
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return true;
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}
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static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
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const struct intel_shared_dpll *pll)
|
||||
{
|
||||
return cnl_ddi_wrpll_get_freq(i915, pll);
|
||||
}
|
||||
|
||||
static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder)
|
||||
@ -4141,18 +4140,21 @@ static const struct intel_shared_dpll_funcs combo_pll_funcs = {
|
||||
.enable = combo_pll_enable,
|
||||
.disable = combo_pll_disable,
|
||||
.get_hw_state = combo_pll_get_hw_state,
|
||||
.get_freq = icl_ddi_combo_pll_get_freq,
|
||||
};
|
||||
|
||||
static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
|
||||
.enable = tbt_pll_enable,
|
||||
.disable = tbt_pll_disable,
|
||||
.get_hw_state = tbt_pll_get_hw_state,
|
||||
.get_freq = icl_ddi_tbt_pll_get_freq,
|
||||
};
|
||||
|
||||
static const struct intel_shared_dpll_funcs mg_pll_funcs = {
|
||||
.enable = mg_pll_enable,
|
||||
.disable = mg_pll_disable,
|
||||
.get_hw_state = mg_pll_get_hw_state,
|
||||
.get_freq = icl_ddi_mg_pll_get_freq,
|
||||
};
|
||||
|
||||
static const struct dpll_info icl_plls[] = {
|
||||
@ -4192,6 +4194,7 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
|
||||
.enable = mg_pll_enable,
|
||||
.disable = mg_pll_disable,
|
||||
.get_hw_state = dkl_pll_get_hw_state,
|
||||
.get_freq = icl_ddi_mg_pll_get_freq,
|
||||
};
|
||||
|
||||
static const struct dpll_info tgl_plls[] = {
|
||||
@ -4348,27 +4351,15 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
|
||||
dpll_mgr->update_active_dpll(state, crtc, encoder);
|
||||
}
|
||||
|
||||
int intel_dpll_get_freq(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
int intel_dpll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
|
||||
if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
|
||||
return 0;
|
||||
|
||||
if (INTEL_GEN(i915) >= 11)
|
||||
return icl_ddi_clock_get(encoder, crtc_state);
|
||||
else if (IS_CANNONLAKE(i915))
|
||||
return cnl_ddi_clock_get(encoder, crtc_state);
|
||||
else if (IS_GEN9_LP(i915))
|
||||
return bxt_ddi_clock_get(encoder, crtc_state);
|
||||
else if (IS_GEN9_BC(i915))
|
||||
return skl_ddi_clock_get(encoder, crtc_state);
|
||||
else if (INTEL_GEN(i915) <= 8)
|
||||
hsw_ddi_clock_get(encoder, crtc_state);
|
||||
|
||||
drm_WARN_ON(&i915->drm, 1);
|
||||
return 0;
|
||||
return pll->info->funcs->get_freq(i915, pll);
|
||||
}
|
||||
|
||||
|
||||
static void readout_dpll_hw_state(struct drm_i915_private *i915,
|
||||
struct intel_shared_dpll *pll)
|
||||
{
|
||||
|
||||
@ -278,6 +278,9 @@ struct intel_shared_dpll_funcs {
|
||||
bool (*get_hw_state)(struct drm_i915_private *dev_priv,
|
||||
struct intel_shared_dpll *pll,
|
||||
struct intel_dpll_hw_state *hw_state);
|
||||
|
||||
int (*get_freq)(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll);
|
||||
};
|
||||
|
||||
/**
|
||||
@ -372,8 +375,8 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
|
||||
void intel_update_active_dpll(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
struct intel_encoder *encoder);
|
||||
int intel_dpll_get_freq(struct intel_encoder *encoder,
|
||||
struct intel_crtc_state *crtc_state);
|
||||
int intel_dpll_get_freq(struct drm_i915_private *i915,
|
||||
const struct intel_shared_dpll *pll);
|
||||
void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
|
||||
@ -384,7 +387,6 @@ void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
|
||||
|
||||
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
|
||||
const struct intel_dpll_hw_state *hw_state);
|
||||
int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
|
||||
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
|
||||
bool intel_dpll_is_combophy(enum intel_dpll_id id);
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user