davinci: am18x/da850/omap-l138: keep async clock constant with cpufreq
Keep PLL0 SYSCLK3 at a constant rate of 100MHz. This enables the AEMIF timing to remain valid even as the PLL0 output is changed by cpufreq driver to save power. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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@ -787,7 +787,7 @@ static __init void da850_evm_init(void)
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if (ret)
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pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
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ret = da850_register_cpufreq();
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ret = da850_register_cpufreq("pll0_sysclk3");
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if (ret)
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pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
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ret);
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@ -86,6 +86,8 @@ static struct clk pll0_sysclk3 = {
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.parent = &pll0_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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.set_rate = davinci_set_sysclk_rate,
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.maxrate = 100000000,
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};
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static struct clk pll0_sysclk4 = {
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@ -929,10 +931,16 @@ static struct platform_device da850_cpufreq_device = {
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.dev = {
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.platform_data = &cpufreq_info,
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},
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.id = -1,
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};
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int __init da850_register_cpufreq(void)
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int __init da850_register_cpufreq(char *async_clk)
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{
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/* cpufreq driver can help keep an "async" clock constant */
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if (async_clk)
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clk_add_alias("async", da850_cpufreq_device.name,
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async_clk, NULL);
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return platform_device_register(&da850_cpufreq_device);
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}
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@ -78,7 +78,7 @@ int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
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int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
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void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
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int da8xx_register_rtc(void);
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int da850_register_cpufreq(void);
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int da850_register_cpufreq(char *async_clk);
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int da8xx_register_cpuidle(void);
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void __iomem * __init da8xx_get_mem_ctlr(void);
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int da850_register_pm(struct platform_device *pdev);
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