ARM: KVM: Remove the old world switch
As we now have a full reimplementation of the world switch, it is time to kiss the old stuff goodbye. I'm not sure we'll miss it. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Marc Zyngier
parent
b57cd6f640
commit
b98e2e728e
@ -17,198 +17,8 @@
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*/
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#include <linux/linkage.h>
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#include <linux/const.h>
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#include <asm/unified.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_arm.h>
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#include <asm/vfpmacros.h>
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#include "interrupts_head.S"
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.text
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.pushsection .hyp.text, "ax"
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/********************************************************************
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* Flush per-VMID TLBs
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*
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* void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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*
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* We rely on the hardware to broadcast the TLB invalidation to all CPUs
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* inside the inner-shareable domain (which is the case for all v7
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* implementations). If we come across a non-IS SMP implementation, we'll
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* have to use an IPI based mechanism. Until then, we stick to the simple
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* hardware assisted version.
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*
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* As v7 does not support flushing per IPA, just nuke the whole TLB
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* instead, ignoring the ipa value.
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*/
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ENTRY(__kvm_tlb_flush_vmid_ipa)
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push {r2, r3}
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dsb ishst
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add r0, r0, #KVM_VTTBR
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ldrd r2, r3, [r0]
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mcrr p15, 6, rr_lo_hi(r2, r3), c2 @ Write VTTBR
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isb
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mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored)
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dsb ish
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isb
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mov r2, #0
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mov r3, #0
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mcrr p15, 6, r2, r3, c2 @ Back to VMID #0
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isb @ Not necessary if followed by eret
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pop {r2, r3}
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bx lr
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ENDPROC(__kvm_tlb_flush_vmid_ipa)
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/**
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* void __kvm_tlb_flush_vmid(struct kvm *kvm) - Flush per-VMID TLBs
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*
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* Reuses __kvm_tlb_flush_vmid_ipa() for ARMv7, without passing address
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* parameter
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*/
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ENTRY(__kvm_tlb_flush_vmid)
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b __kvm_tlb_flush_vmid_ipa
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ENDPROC(__kvm_tlb_flush_vmid)
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/********************************************************************
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* Flush TLBs and instruction caches of all CPUs inside the inner-shareable
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* domain, for all VMIDs
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*
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* void __kvm_flush_vm_context(void);
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*/
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ENTRY(__kvm_flush_vm_context)
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mov r0, #0 @ rn parameter for c15 flushes is SBZ
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/* Invalidate NS Non-Hyp TLB Inner Shareable (TLBIALLNSNHIS) */
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mcr p15, 4, r0, c8, c3, 4
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/* Invalidate instruction caches Inner Shareable (ICIALLUIS) */
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mcr p15, 0, r0, c7, c1, 0
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dsb ish
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isb @ Not necessary if followed by eret
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bx lr
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ENDPROC(__kvm_flush_vm_context)
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/********************************************************************
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* Hypervisor world-switch code
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*
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*
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* int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
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*/
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ENTRY(__kvm_vcpu_run)
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@ Save the vcpu pointer
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mcr p15, 4, vcpu, c13, c0, 2 @ HTPIDR
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save_host_regs
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restore_vgic_state
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restore_timer_state
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@ Store hardware CP15 state and load guest state
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read_cp15_state store_to_vcpu = 0
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write_cp15_state read_from_vcpu = 1
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@ If the host kernel has not been configured with VFPv3 support,
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@ then it is safer if we deny guests from using it as well.
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#ifdef CONFIG_VFPv3
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@ Set FPEXC_EN so the guest doesn't trap floating point instructions
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VFPFMRX r2, FPEXC @ VMRS
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push {r2}
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orr r2, r2, #FPEXC_EN
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VFPFMXR FPEXC, r2 @ VMSR
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#endif
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@ Configure Hyp-role
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configure_hyp_role vmentry
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@ Trap coprocessor CRx accesses
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set_hstr vmentry
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set_hcptr vmentry, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
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set_hdcr vmentry
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@ Write configured ID register into MIDR alias
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ldr r1, [vcpu, #VCPU_MIDR]
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mcr p15, 4, r1, c0, c0, 0
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@ Write guest view of MPIDR into VMPIDR
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ldr r1, [vcpu, #CP15_OFFSET(c0_MPIDR)]
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mcr p15, 4, r1, c0, c0, 5
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@ Set up guest memory translation
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ldr r1, [vcpu, #VCPU_KVM]
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add r1, r1, #KVM_VTTBR
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ldrd r2, r3, [r1]
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mcrr p15, 6, rr_lo_hi(r2, r3), c2 @ Write VTTBR
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@ We're all done, just restore the GPRs and go to the guest
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restore_guest_regs
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clrex @ Clear exclusive monitor
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eret
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__kvm_vcpu_return:
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/*
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* return convention:
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* guest r0, r1, r2 saved on the stack
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* r0: vcpu pointer
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* r1: exception code
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*/
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save_guest_regs
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@ Set VMID == 0
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mov r2, #0
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mov r3, #0
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mcrr p15, 6, r2, r3, c2 @ Write VTTBR
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@ Don't trap coprocessor accesses for host kernel
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set_hstr vmexit
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set_hdcr vmexit
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set_hcptr vmexit, (HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11)), after_vfp_restore
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#ifdef CONFIG_VFPv3
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@ Switch VFP/NEON hardware state to the host's
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add r7, vcpu, #(VCPU_GUEST_CTXT + CPU_CTXT_VFP)
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store_vfp_state r7
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add r7, vcpu, #VCPU_HOST_CTXT
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ldr r7, [r7]
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add r7, r7, #CPU_CTXT_VFP
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restore_vfp_state r7
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after_vfp_restore:
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@ Restore FPEXC_EN which we clobbered on entry
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pop {r2}
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VFPFMXR FPEXC, r2
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#else
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after_vfp_restore:
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#endif
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@ Reset Hyp-role
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configure_hyp_role vmexit
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@ Let host read hardware MIDR
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mrc p15, 0, r2, c0, c0, 0
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mcr p15, 4, r2, c0, c0, 0
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@ Back to hardware MPIDR
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mrc p15, 0, r2, c0, c0, 5
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mcr p15, 4, r2, c0, c0, 5
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@ Store guest CP15 state and restore host state
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read_cp15_state store_to_vcpu = 1
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write_cp15_state read_from_vcpu = 0
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save_timer_state
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save_vgic_state
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restore_host_regs
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clrex @ Clear exclusive monitor
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mov r0, r1 @ Return the return code
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bx lr @ return to IOCTL
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/********************************************************************
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* Call function in Hyp mode
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@ -239,281 +49,4 @@ after_vfp_restore:
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ENTRY(kvm_call_hyp)
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hvc #0
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bx lr
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/********************************************************************
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* Hypervisor exception vector and handlers
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*
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*
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* The KVM/ARM Hypervisor ABI is defined as follows:
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*
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* Entry to Hyp mode from the host kernel will happen _only_ when an HVC
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* instruction is issued since all traps are disabled when running the host
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* kernel as per the Hyp-mode initialization at boot time.
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*
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* HVC instructions cause a trap to the vector page + offset 0x14 (see hyp_hvc
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* below) when the HVC instruction is called from SVC mode (i.e. a guest or the
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* host kernel) and they cause a trap to the vector page + offset 0x8 when HVC
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* instructions are called from within Hyp-mode.
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*
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* Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
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* Switching to Hyp mode is done through a simple HVC #0 instruction. The
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* exception vector code will check that the HVC comes from VMID==0 and if
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* so will push the necessary state (SPSR, lr_usr) on the Hyp stack.
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* - r0 contains a pointer to a HYP function
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* - r1, r2, and r3 contain arguments to the above function.
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* - The HYP function will be called with its arguments in r0, r1 and r2.
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* On HYP function return, we return directly to SVC.
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*
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* Note that the above is used to execute code in Hyp-mode from a host-kernel
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* point of view, and is a different concept from performing a world-switch and
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* executing guest code SVC mode (with a VMID != 0).
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*/
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/* Handle undef, svc, pabt, or dabt by crashing with a user notice */
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.macro bad_exception exception_code, panic_str
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push {r0-r2}
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mrrc p15, 6, r0, r1, c2 @ Read VTTBR
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lsr r1, r1, #16
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ands r1, r1, #0xff
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beq 99f
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load_vcpu @ Load VCPU pointer
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.if \exception_code == ARM_EXCEPTION_DATA_ABORT
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mrc p15, 4, r2, c5, c2, 0 @ HSR
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mrc p15, 4, r1, c6, c0, 0 @ HDFAR
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str r2, [vcpu, #VCPU_HSR]
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str r1, [vcpu, #VCPU_HxFAR]
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.endif
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.if \exception_code == ARM_EXCEPTION_PREF_ABORT
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mrc p15, 4, r2, c5, c2, 0 @ HSR
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mrc p15, 4, r1, c6, c0, 2 @ HIFAR
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str r2, [vcpu, #VCPU_HSR]
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str r1, [vcpu, #VCPU_HxFAR]
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.endif
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mov r1, #\exception_code
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b __kvm_vcpu_return
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@ We were in the host already. Let's craft a panic-ing return to SVC.
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99: mrs r2, cpsr
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bic r2, r2, #MODE_MASK
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orr r2, r2, #SVC_MODE
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THUMB( orr r2, r2, #PSR_T_BIT )
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msr spsr_cxsf, r2
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mrs r1, ELR_hyp
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ldr r2, =panic
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msr ELR_hyp, r2
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ldr r0, =\panic_str
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clrex @ Clear exclusive monitor
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eret
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.endm
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.align 5
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__kvm_hyp_vector:
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.globl __kvm_hyp_vector
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@ Hyp-mode exception vector
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W(b) hyp_reset
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W(b) hyp_undef
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W(b) hyp_svc
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W(b) hyp_pabt
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W(b) hyp_dabt
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W(b) hyp_hvc
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W(b) hyp_irq
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W(b) hyp_fiq
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.align
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hyp_reset:
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b hyp_reset
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.align
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hyp_undef:
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bad_exception ARM_EXCEPTION_UNDEFINED, und_die_str
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.align
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hyp_svc:
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bad_exception ARM_EXCEPTION_HVC, svc_die_str
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.align
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hyp_pabt:
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bad_exception ARM_EXCEPTION_PREF_ABORT, pabt_die_str
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.align
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hyp_dabt:
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bad_exception ARM_EXCEPTION_DATA_ABORT, dabt_die_str
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.align
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hyp_hvc:
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/*
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* Getting here is either becuase of a trap from a guest or from calling
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* HVC from the host kernel, which means "switch to Hyp mode".
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*/
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push {r0, r1, r2}
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@ Check syndrome register
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mrc p15, 4, r1, c5, c2, 0 @ HSR
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lsr r0, r1, #HSR_EC_SHIFT
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cmp r0, #HSR_EC_HVC
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bne guest_trap @ Not HVC instr.
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/*
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* Let's check if the HVC came from VMID 0 and allow simple
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* switch to Hyp mode
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*/
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mrrc p15, 6, r0, r2, c2
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lsr r2, r2, #16
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and r2, r2, #0xff
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cmp r2, #0
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bne guest_trap @ Guest called HVC
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/*
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* Getting here means host called HVC, we shift parameters and branch
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* to Hyp function.
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*/
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pop {r0, r1, r2}
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/* Check for __hyp_get_vectors */
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cmp r0, #-1
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mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR
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beq 1f
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push {lr}
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mrs lr, SPSR
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push {lr}
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mov lr, r0
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mov r0, r1
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mov r1, r2
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mov r2, r3
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THUMB( orr lr, #1)
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blx lr @ Call the HYP function
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pop {lr}
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msr SPSR_csxf, lr
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pop {lr}
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1: eret
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guest_trap:
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load_vcpu @ Load VCPU pointer to r0
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str r1, [vcpu, #VCPU_HSR]
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@ Check if we need the fault information
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lsr r1, r1, #HSR_EC_SHIFT
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#ifdef CONFIG_VFPv3
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cmp r1, #HSR_EC_CP_0_13
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beq switch_to_guest_vfp
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#endif
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cmp r1, #HSR_EC_IABT
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mrceq p15, 4, r2, c6, c0, 2 @ HIFAR
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beq 2f
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cmp r1, #HSR_EC_DABT
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bne 1f
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mrc p15, 4, r2, c6, c0, 0 @ HDFAR
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2: str r2, [vcpu, #VCPU_HxFAR]
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/*
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* B3.13.5 Reporting exceptions taken to the Non-secure PL2 mode:
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*
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* Abort on the stage 2 translation for a memory access from a
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* Non-secure PL1 or PL0 mode:
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*
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* For any Access flag fault or Translation fault, and also for any
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* Permission fault on the stage 2 translation of a memory access
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* made as part of a translation table walk for a stage 1 translation,
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* the HPFAR holds the IPA that caused the fault. Otherwise, the HPFAR
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* is UNKNOWN.
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*/
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/* Check for permission fault, and S1PTW */
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mrc p15, 4, r1, c5, c2, 0 @ HSR
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and r0, r1, #HSR_FSC_TYPE
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cmp r0, #FSC_PERM
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tsteq r1, #(1 << 7) @ S1PTW
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mrcne p15, 4, r2, c6, c0, 4 @ HPFAR
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bne 3f
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/* Preserve PAR */
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mrrc p15, 0, r0, r1, c7 @ PAR
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push {r0, r1}
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/* Resolve IPA using the xFAR */
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mcr p15, 0, r2, c7, c8, 0 @ ATS1CPR
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isb
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mrrc p15, 0, r0, r1, c7 @ PAR
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tst r0, #1
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bne 4f @ Failed translation
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ubfx r2, r0, #12, #20
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lsl r2, r2, #4
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orr r2, r2, r1, lsl #24
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/* Restore PAR */
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pop {r0, r1}
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mcrr p15, 0, r0, r1, c7 @ PAR
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3: load_vcpu @ Load VCPU pointer to r0
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str r2, [r0, #VCPU_HPFAR]
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1: mov r1, #ARM_EXCEPTION_HVC
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b __kvm_vcpu_return
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4: pop {r0, r1} @ Failed translation, return to guest
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mcrr p15, 0, r0, r1, c7 @ PAR
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clrex
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pop {r0, r1, r2}
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eret
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/*
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* If VFPv3 support is not available, then we will not switch the VFP
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* registers; however cp10 and cp11 accesses will still trap and fallback
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* to the regular coprocessor emulation code, which currently will
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* inject an undefined exception to the guest.
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*/
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#ifdef CONFIG_VFPv3
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switch_to_guest_vfp:
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push {r3-r7}
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@ NEON/VFP used. Turn on VFP access.
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set_hcptr vmtrap, (HCPTR_TCP(10) | HCPTR_TCP(11))
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@ Switch VFP/NEON hardware state to the guest's
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add r7, r0, #VCPU_HOST_CTXT
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ldr r7, [r7]
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add r7, r7, #CPU_CTXT_VFP
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store_vfp_state r7
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add r7, r0, #(VCPU_GUEST_CTXT + CPU_CTXT_VFP)
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restore_vfp_state r7
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pop {r3-r7}
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pop {r0-r2}
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clrex
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eret
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#endif
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.align
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hyp_irq:
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push {r0, r1, r2}
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mov r1, #ARM_EXCEPTION_IRQ
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load_vcpu @ Load VCPU pointer to r0
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b __kvm_vcpu_return
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||||
.align
|
||||
hyp_fiq:
|
||||
b hyp_fiq
|
||||
|
||||
.ltorg
|
||||
|
||||
.popsection
|
||||
|
||||
.pushsection ".rodata"
|
||||
|
||||
und_die_str:
|
||||
.ascii "unexpected undefined exception in Hyp mode at: %#08x\n"
|
||||
pabt_die_str:
|
||||
.ascii "unexpected prefetch abort in Hyp mode at: %#08x\n"
|
||||
dabt_die_str:
|
||||
.ascii "unexpected data abort in Hyp mode at: %#08x\n"
|
||||
svc_die_str:
|
||||
.ascii "unexpected HVC/SVC trap in Hyp mode at: %#08x\n"
|
||||
|
||||
.popsection
|
||||
ENDPROC(kvm_call_hyp)
|
||||
|
||||
@ -1,660 +0,0 @@
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
/* Compat macro, until we get rid of this file entierely */
|
||||
#define VCPU_GP_REGS (VCPU_GUEST_CTXT + CPU_CTXT_GP_REGS)
|
||||
#define VCPU_USR_REGS (VCPU_GP_REGS + GP_REGS_USR)
|
||||
#define VCPU_SVC_REGS (VCPU_GP_REGS + GP_REGS_SVC)
|
||||
#define VCPU_ABT_REGS (VCPU_GP_REGS + GP_REGS_ABT)
|
||||
#define VCPU_UND_REGS (VCPU_GP_REGS + GP_REGS_UND)
|
||||
#define VCPU_IRQ_REGS (VCPU_GP_REGS + GP_REGS_IRQ)
|
||||
#define VCPU_FIQ_REGS (VCPU_GP_REGS + GP_REGS_FIQ)
|
||||
#define VCPU_PC (VCPU_GP_REGS + GP_REGS_PC)
|
||||
#define VCPU_CPSR (VCPU_GP_REGS + GP_REGS_CPSR)
|
||||
|
||||
#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
|
||||
#define VCPU_USR_SP (VCPU_USR_REG(13))
|
||||
#define VCPU_USR_LR (VCPU_USR_REG(14))
|
||||
#define VCPU_CP15_BASE (VCPU_GUEST_CTXT + CPU_CTXT_CP15)
|
||||
#define CP15_OFFSET(_cp15_reg_idx) (VCPU_CP15_BASE + (_cp15_reg_idx * 4))
|
||||
|
||||
/*
|
||||
* Many of these macros need to access the VCPU structure, which is always
|
||||
* held in r0. These macros should never clobber r1, as it is used to hold the
|
||||
* exception code on the return path (except of course the macro that switches
|
||||
* all the registers before the final jump to the VM).
|
||||
*/
|
||||
vcpu .req r0 @ vcpu pointer always in r0
|
||||
|
||||
/* Clobbers {r2-r6} */
|
||||
.macro store_vfp_state vfp_base
|
||||
@ The VFPFMRX and VFPFMXR macros are the VMRS and VMSR instructions
|
||||
VFPFMRX r2, FPEXC
|
||||
@ Make sure VFP is enabled so we can touch the registers.
|
||||
orr r6, r2, #FPEXC_EN
|
||||
VFPFMXR FPEXC, r6
|
||||
|
||||
VFPFMRX r3, FPSCR
|
||||
tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
|
||||
beq 1f
|
||||
@ If FPEXC_EX is 0, then FPINST/FPINST2 reads are upredictable, so
|
||||
@ we only need to save them if FPEXC_EX is set.
|
||||
VFPFMRX r4, FPINST
|
||||
tst r2, #FPEXC_FP2V
|
||||
VFPFMRX r5, FPINST2, ne @ vmrsne
|
||||
bic r6, r2, #FPEXC_EX @ FPEXC_EX disable
|
||||
VFPFMXR FPEXC, r6
|
||||
1:
|
||||
VFPFSTMIA \vfp_base, r6 @ Save VFP registers
|
||||
stm \vfp_base, {r2-r5} @ Save FPEXC, FPSCR, FPINST, FPINST2
|
||||
.endm
|
||||
|
||||
/* Assume FPEXC_EN is on and FPEXC_EX is off, clobbers {r2-r6} */
|
||||
.macro restore_vfp_state vfp_base
|
||||
VFPFLDMIA \vfp_base, r6 @ Load VFP registers
|
||||
ldm \vfp_base, {r2-r5} @ Load FPEXC, FPSCR, FPINST, FPINST2
|
||||
|
||||
VFPFMXR FPSCR, r3
|
||||
tst r2, #FPEXC_EX @ Check for VFP Subarchitecture
|
||||
beq 1f
|
||||
VFPFMXR FPINST, r4
|
||||
tst r2, #FPEXC_FP2V
|
||||
VFPFMXR FPINST2, r5, ne
|
||||
1:
|
||||
VFPFMXR FPEXC, r2 @ FPEXC (last, in case !EN)
|
||||
.endm
|
||||
|
||||
/* These are simply for the macros to work - value don't have meaning */
|
||||
.equ usr, 0
|
||||
.equ svc, 1
|
||||
.equ abt, 2
|
||||
.equ und, 3
|
||||
.equ irq, 4
|
||||
.equ fiq, 5
|
||||
|
||||
.macro push_host_regs_mode mode
|
||||
mrs r2, SP_\mode
|
||||
mrs r3, LR_\mode
|
||||
mrs r4, SPSR_\mode
|
||||
push {r2, r3, r4}
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Store all host persistent registers on the stack.
|
||||
* Clobbers all registers, in all modes, except r0 and r1.
|
||||
*/
|
||||
.macro save_host_regs
|
||||
/* Hyp regs. Only ELR_hyp (SPSR_hyp already saved) */
|
||||
mrs r2, ELR_hyp
|
||||
push {r2}
|
||||
|
||||
/* usr regs */
|
||||
push {r4-r12} @ r0-r3 are always clobbered
|
||||
mrs r2, SP_usr
|
||||
mov r3, lr
|
||||
push {r2, r3}
|
||||
|
||||
push_host_regs_mode svc
|
||||
push_host_regs_mode abt
|
||||
push_host_regs_mode und
|
||||
push_host_regs_mode irq
|
||||
|
||||
/* fiq regs */
|
||||
mrs r2, r8_fiq
|
||||
mrs r3, r9_fiq
|
||||
mrs r4, r10_fiq
|
||||
mrs r5, r11_fiq
|
||||
mrs r6, r12_fiq
|
||||
mrs r7, SP_fiq
|
||||
mrs r8, LR_fiq
|
||||
mrs r9, SPSR_fiq
|
||||
push {r2-r9}
|
||||
.endm
|
||||
|
||||
.macro pop_host_regs_mode mode
|
||||
pop {r2, r3, r4}
|
||||
msr SP_\mode, r2
|
||||
msr LR_\mode, r3
|
||||
msr SPSR_\mode, r4
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Restore all host registers from the stack.
|
||||
* Clobbers all registers, in all modes, except r0 and r1.
|
||||
*/
|
||||
.macro restore_host_regs
|
||||
pop {r2-r9}
|
||||
msr r8_fiq, r2
|
||||
msr r9_fiq, r3
|
||||
msr r10_fiq, r4
|
||||
msr r11_fiq, r5
|
||||
msr r12_fiq, r6
|
||||
msr SP_fiq, r7
|
||||
msr LR_fiq, r8
|
||||
msr SPSR_fiq, r9
|
||||
|
||||
pop_host_regs_mode irq
|
||||
pop_host_regs_mode und
|
||||
pop_host_regs_mode abt
|
||||
pop_host_regs_mode svc
|
||||
|
||||
pop {r2, r3}
|
||||
msr SP_usr, r2
|
||||
mov lr, r3
|
||||
pop {r4-r12}
|
||||
|
||||
pop {r2}
|
||||
msr ELR_hyp, r2
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Restore SP, LR and SPSR for a given mode. offset is the offset of
|
||||
* this mode's registers from the VCPU base.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*
|
||||
* Clobbers r1, r2, r3, r4.
|
||||
*/
|
||||
.macro restore_guest_regs_mode mode, offset
|
||||
add r1, vcpu, \offset
|
||||
ldm r1, {r2, r3, r4}
|
||||
msr SP_\mode, r2
|
||||
msr LR_\mode, r3
|
||||
msr SPSR_\mode, r4
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Restore all guest registers from the vcpu struct.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*
|
||||
* Clobbers *all* registers.
|
||||
*/
|
||||
.macro restore_guest_regs
|
||||
restore_guest_regs_mode svc, #VCPU_SVC_REGS
|
||||
restore_guest_regs_mode abt, #VCPU_ABT_REGS
|
||||
restore_guest_regs_mode und, #VCPU_UND_REGS
|
||||
restore_guest_regs_mode irq, #VCPU_IRQ_REGS
|
||||
|
||||
add r1, vcpu, #VCPU_FIQ_REGS
|
||||
ldm r1, {r2-r9}
|
||||
msr r8_fiq, r2
|
||||
msr r9_fiq, r3
|
||||
msr r10_fiq, r4
|
||||
msr r11_fiq, r5
|
||||
msr r12_fiq, r6
|
||||
msr SP_fiq, r7
|
||||
msr LR_fiq, r8
|
||||
msr SPSR_fiq, r9
|
||||
|
||||
@ Load return state
|
||||
ldr r2, [vcpu, #VCPU_PC]
|
||||
ldr r3, [vcpu, #VCPU_CPSR]
|
||||
msr ELR_hyp, r2
|
||||
msr SPSR_cxsf, r3
|
||||
|
||||
@ Load user registers
|
||||
ldr r2, [vcpu, #VCPU_USR_SP]
|
||||
ldr r3, [vcpu, #VCPU_USR_LR]
|
||||
msr SP_usr, r2
|
||||
mov lr, r3
|
||||
add vcpu, vcpu, #(VCPU_USR_REGS)
|
||||
ldm vcpu, {r0-r12}
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Save SP, LR and SPSR for a given mode. offset is the offset of
|
||||
* this mode's registers from the VCPU base.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*
|
||||
* Clobbers r2, r3, r4, r5.
|
||||
*/
|
||||
.macro save_guest_regs_mode mode, offset
|
||||
add r2, vcpu, \offset
|
||||
mrs r3, SP_\mode
|
||||
mrs r4, LR_\mode
|
||||
mrs r5, SPSR_\mode
|
||||
stm r2, {r3, r4, r5}
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Save all guest registers to the vcpu struct
|
||||
* Expects guest's r0, r1, r2 on the stack.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*
|
||||
* Clobbers r2, r3, r4, r5.
|
||||
*/
|
||||
.macro save_guest_regs
|
||||
@ Store usr registers
|
||||
add r2, vcpu, #VCPU_USR_REG(3)
|
||||
stm r2, {r3-r12}
|
||||
add r2, vcpu, #VCPU_USR_REG(0)
|
||||
pop {r3, r4, r5} @ r0, r1, r2
|
||||
stm r2, {r3, r4, r5}
|
||||
mrs r2, SP_usr
|
||||
mov r3, lr
|
||||
str r2, [vcpu, #VCPU_USR_SP]
|
||||
str r3, [vcpu, #VCPU_USR_LR]
|
||||
|
||||
@ Store return state
|
||||
mrs r2, ELR_hyp
|
||||
mrs r3, spsr
|
||||
str r2, [vcpu, #VCPU_PC]
|
||||
str r3, [vcpu, #VCPU_CPSR]
|
||||
|
||||
@ Store other guest registers
|
||||
save_guest_regs_mode svc, #VCPU_SVC_REGS
|
||||
save_guest_regs_mode abt, #VCPU_ABT_REGS
|
||||
save_guest_regs_mode und, #VCPU_UND_REGS
|
||||
save_guest_regs_mode irq, #VCPU_IRQ_REGS
|
||||
.endm
|
||||
|
||||
/* Reads cp15 registers from hardware and stores them in memory
|
||||
* @store_to_vcpu: If 0, registers are written in-order to the stack,
|
||||
* otherwise to the VCPU struct pointed to by vcpup
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*
|
||||
* Clobbers r2 - r12
|
||||
*/
|
||||
.macro read_cp15_state store_to_vcpu
|
||||
mrc p15, 0, r2, c1, c0, 0 @ SCTLR
|
||||
mrc p15, 0, r3, c1, c0, 2 @ CPACR
|
||||
mrc p15, 0, r4, c2, c0, 2 @ TTBCR
|
||||
mrc p15, 0, r5, c3, c0, 0 @ DACR
|
||||
mrrc p15, 0, r6, r7, c2 @ TTBR 0
|
||||
mrrc p15, 1, r8, r9, c2 @ TTBR 1
|
||||
mrc p15, 0, r10, c10, c2, 0 @ PRRR
|
||||
mrc p15, 0, r11, c10, c2, 1 @ NMRR
|
||||
mrc p15, 2, r12, c0, c0, 0 @ CSSELR
|
||||
|
||||
.if \store_to_vcpu == 0
|
||||
push {r2-r12} @ Push CP15 registers
|
||||
.else
|
||||
str r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
|
||||
str r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
|
||||
str r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
|
||||
str r5, [vcpu, #CP15_OFFSET(c3_DACR)]
|
||||
add r2, vcpu, #CP15_OFFSET(c2_TTBR0)
|
||||
strd r6, r7, [r2]
|
||||
add r2, vcpu, #CP15_OFFSET(c2_TTBR1)
|
||||
strd r8, r9, [r2]
|
||||
str r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
|
||||
str r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
|
||||
str r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
|
||||
.endif
|
||||
|
||||
mrc p15, 0, r2, c13, c0, 1 @ CID
|
||||
mrc p15, 0, r3, c13, c0, 2 @ TID_URW
|
||||
mrc p15, 0, r4, c13, c0, 3 @ TID_URO
|
||||
mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV
|
||||
mrc p15, 0, r6, c5, c0, 0 @ DFSR
|
||||
mrc p15, 0, r7, c5, c0, 1 @ IFSR
|
||||
mrc p15, 0, r8, c5, c1, 0 @ ADFSR
|
||||
mrc p15, 0, r9, c5, c1, 1 @ AIFSR
|
||||
mrc p15, 0, r10, c6, c0, 0 @ DFAR
|
||||
mrc p15, 0, r11, c6, c0, 2 @ IFAR
|
||||
mrc p15, 0, r12, c12, c0, 0 @ VBAR
|
||||
|
||||
.if \store_to_vcpu == 0
|
||||
push {r2-r12} @ Push CP15 registers
|
||||
.else
|
||||
str r2, [vcpu, #CP15_OFFSET(c13_CID)]
|
||||
str r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
|
||||
str r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
|
||||
str r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
|
||||
str r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
|
||||
str r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
|
||||
str r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
|
||||
str r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
|
||||
str r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
|
||||
str r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
|
||||
str r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
|
||||
.endif
|
||||
|
||||
mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
|
||||
mrrc p15, 0, r4, r5, c7 @ PAR
|
||||
mrc p15, 0, r6, c10, c3, 0 @ AMAIR0
|
||||
mrc p15, 0, r7, c10, c3, 1 @ AMAIR1
|
||||
|
||||
.if \store_to_vcpu == 0
|
||||
push {r2,r4-r7}
|
||||
.else
|
||||
str r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
|
||||
add r12, vcpu, #CP15_OFFSET(c7_PAR)
|
||||
strd r4, r5, [r12]
|
||||
str r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
|
||||
str r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Reads cp15 registers from memory and writes them to hardware
|
||||
* @read_from_vcpu: If 0, registers are read in-order from the stack,
|
||||
* otherwise from the VCPU struct pointed to by vcpup
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*/
|
||||
.macro write_cp15_state read_from_vcpu
|
||||
.if \read_from_vcpu == 0
|
||||
pop {r2,r4-r7}
|
||||
.else
|
||||
ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
|
||||
add r12, vcpu, #CP15_OFFSET(c7_PAR)
|
||||
ldrd r4, r5, [r12]
|
||||
ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
|
||||
ldr r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
|
||||
.endif
|
||||
|
||||
mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL
|
||||
mcrr p15, 0, r4, r5, c7 @ PAR
|
||||
mcr p15, 0, r6, c10, c3, 0 @ AMAIR0
|
||||
mcr p15, 0, r7, c10, c3, 1 @ AMAIR1
|
||||
|
||||
.if \read_from_vcpu == 0
|
||||
pop {r2-r12}
|
||||
.else
|
||||
ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
|
||||
ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
|
||||
ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
|
||||
ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
|
||||
ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
|
||||
ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
|
||||
ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
|
||||
ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
|
||||
ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
|
||||
ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
|
||||
ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
|
||||
.endif
|
||||
|
||||
mcr p15, 0, r2, c13, c0, 1 @ CID
|
||||
mcr p15, 0, r3, c13, c0, 2 @ TID_URW
|
||||
mcr p15, 0, r4, c13, c0, 3 @ TID_URO
|
||||
mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV
|
||||
mcr p15, 0, r6, c5, c0, 0 @ DFSR
|
||||
mcr p15, 0, r7, c5, c0, 1 @ IFSR
|
||||
mcr p15, 0, r8, c5, c1, 0 @ ADFSR
|
||||
mcr p15, 0, r9, c5, c1, 1 @ AIFSR
|
||||
mcr p15, 0, r10, c6, c0, 0 @ DFAR
|
||||
mcr p15, 0, r11, c6, c0, 2 @ IFAR
|
||||
mcr p15, 0, r12, c12, c0, 0 @ VBAR
|
||||
|
||||
.if \read_from_vcpu == 0
|
||||
pop {r2-r12}
|
||||
.else
|
||||
ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
|
||||
ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
|
||||
ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
|
||||
ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
|
||||
add r12, vcpu, #CP15_OFFSET(c2_TTBR0)
|
||||
ldrd r6, r7, [r12]
|
||||
add r12, vcpu, #CP15_OFFSET(c2_TTBR1)
|
||||
ldrd r8, r9, [r12]
|
||||
ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
|
||||
ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
|
||||
ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
|
||||
.endif
|
||||
|
||||
mcr p15, 0, r2, c1, c0, 0 @ SCTLR
|
||||
mcr p15, 0, r3, c1, c0, 2 @ CPACR
|
||||
mcr p15, 0, r4, c2, c0, 2 @ TTBCR
|
||||
mcr p15, 0, r5, c3, c0, 0 @ DACR
|
||||
mcrr p15, 0, r6, r7, c2 @ TTBR 0
|
||||
mcrr p15, 1, r8, r9, c2 @ TTBR 1
|
||||
mcr p15, 0, r10, c10, c2, 0 @ PRRR
|
||||
mcr p15, 0, r11, c10, c2, 1 @ NMRR
|
||||
mcr p15, 2, r12, c0, c0, 0 @ CSSELR
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Save the VGIC CPU state into memory
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*/
|
||||
.macro save_vgic_state
|
||||
/* Get VGIC VCTRL base into r2 */
|
||||
ldr r2, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r2, #KVM_VGIC_VCTRL]
|
||||
cmp r2, #0
|
||||
beq 2f
|
||||
|
||||
/* Compute the address of struct vgic_cpu */
|
||||
add r11, vcpu, #VCPU_VGIC_CPU
|
||||
|
||||
/* Save all interesting registers */
|
||||
ldr r4, [r2, #GICH_VMCR]
|
||||
ldr r5, [r2, #GICH_MISR]
|
||||
ldr r6, [r2, #GICH_EISR0]
|
||||
ldr r7, [r2, #GICH_EISR1]
|
||||
ldr r8, [r2, #GICH_ELRSR0]
|
||||
ldr r9, [r2, #GICH_ELRSR1]
|
||||
ldr r10, [r2, #GICH_APR]
|
||||
ARM_BE8(rev r4, r4 )
|
||||
ARM_BE8(rev r5, r5 )
|
||||
ARM_BE8(rev r6, r6 )
|
||||
ARM_BE8(rev r7, r7 )
|
||||
ARM_BE8(rev r8, r8 )
|
||||
ARM_BE8(rev r9, r9 )
|
||||
ARM_BE8(rev r10, r10 )
|
||||
|
||||
str r4, [r11, #VGIC_V2_CPU_VMCR]
|
||||
str r5, [r11, #VGIC_V2_CPU_MISR]
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
str r6, [r11, #(VGIC_V2_CPU_EISR + 4)]
|
||||
str r7, [r11, #VGIC_V2_CPU_EISR]
|
||||
str r8, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
|
||||
str r9, [r11, #VGIC_V2_CPU_ELRSR]
|
||||
#else
|
||||
str r6, [r11, #VGIC_V2_CPU_EISR]
|
||||
str r7, [r11, #(VGIC_V2_CPU_EISR + 4)]
|
||||
str r8, [r11, #VGIC_V2_CPU_ELRSR]
|
||||
str r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
|
||||
#endif
|
||||
str r10, [r11, #VGIC_V2_CPU_APR]
|
||||
|
||||
/* Clear GICH_HCR */
|
||||
mov r5, #0
|
||||
str r5, [r2, #GICH_HCR]
|
||||
|
||||
/* Save list registers */
|
||||
add r2, r2, #GICH_LR0
|
||||
add r3, r11, #VGIC_V2_CPU_LR
|
||||
ldr r4, [r11, #VGIC_CPU_NR_LR]
|
||||
1: ldr r6, [r2], #4
|
||||
ARM_BE8(rev r6, r6 )
|
||||
str r6, [r3], #4
|
||||
subs r4, r4, #1
|
||||
bne 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Restore the VGIC CPU state from memory
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
*/
|
||||
.macro restore_vgic_state
|
||||
/* Get VGIC VCTRL base into r2 */
|
||||
ldr r2, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r2, #KVM_VGIC_VCTRL]
|
||||
cmp r2, #0
|
||||
beq 2f
|
||||
|
||||
/* Compute the address of struct vgic_cpu */
|
||||
add r11, vcpu, #VCPU_VGIC_CPU
|
||||
|
||||
/* We only restore a minimal set of registers */
|
||||
ldr r3, [r11, #VGIC_V2_CPU_HCR]
|
||||
ldr r4, [r11, #VGIC_V2_CPU_VMCR]
|
||||
ldr r8, [r11, #VGIC_V2_CPU_APR]
|
||||
ARM_BE8(rev r3, r3 )
|
||||
ARM_BE8(rev r4, r4 )
|
||||
ARM_BE8(rev r8, r8 )
|
||||
|
||||
str r3, [r2, #GICH_HCR]
|
||||
str r4, [r2, #GICH_VMCR]
|
||||
str r8, [r2, #GICH_APR]
|
||||
|
||||
/* Restore list registers */
|
||||
add r2, r2, #GICH_LR0
|
||||
add r3, r11, #VGIC_V2_CPU_LR
|
||||
ldr r4, [r11, #VGIC_CPU_NR_LR]
|
||||
1: ldr r6, [r3], #4
|
||||
ARM_BE8(rev r6, r6 )
|
||||
str r6, [r2], #4
|
||||
subs r4, r4, #1
|
||||
bne 1b
|
||||
2:
|
||||
.endm
|
||||
|
||||
#define CNTHCTL_PL1PCTEN (1 << 0)
|
||||
#define CNTHCTL_PL1PCEN (1 << 1)
|
||||
|
||||
/*
|
||||
* Save the timer state onto the VCPU and allow physical timer/counter access
|
||||
* for the host.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
* Clobbers r2-r5
|
||||
*/
|
||||
.macro save_timer_state
|
||||
ldr r4, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r4, #KVM_TIMER_ENABLED]
|
||||
cmp r2, #0
|
||||
beq 1f
|
||||
|
||||
mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
str r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
||||
|
||||
isb
|
||||
|
||||
mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
|
||||
ldr r4, =VCPU_TIMER_CNTV_CVAL
|
||||
add r5, vcpu, r4
|
||||
strd r2, r3, [r5]
|
||||
|
||||
@ Ensure host CNTVCT == CNTPCT
|
||||
mov r2, #0
|
||||
mcrr p15, 4, r2, r2, c14 @ CNTVOFF
|
||||
|
||||
1:
|
||||
mov r2, #0 @ Clear ENABLE
|
||||
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
|
||||
@ Allow physical timer/counter access for the host
|
||||
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
orr r2, r2, #(CNTHCTL_PL1PCEN | CNTHCTL_PL1PCTEN)
|
||||
mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Load the timer state from the VCPU and deny physical timer/counter access
|
||||
* for the host.
|
||||
*
|
||||
* Assumes vcpu pointer in vcpu reg
|
||||
* Clobbers r2-r5
|
||||
*/
|
||||
.macro restore_timer_state
|
||||
@ Disallow physical timer access for the guest
|
||||
@ Physical counter access is allowed
|
||||
mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
orr r2, r2, #CNTHCTL_PL1PCTEN
|
||||
bic r2, r2, #CNTHCTL_PL1PCEN
|
||||
mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL
|
||||
|
||||
ldr r4, [vcpu, #VCPU_KVM]
|
||||
ldr r2, [r4, #KVM_TIMER_ENABLED]
|
||||
cmp r2, #0
|
||||
beq 1f
|
||||
|
||||
ldr r2, [r4, #KVM_TIMER_CNTVOFF]
|
||||
ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
|
||||
mcrr p15, 4, rr_lo_hi(r2, r3), c14 @ CNTVOFF
|
||||
|
||||
ldr r4, =VCPU_TIMER_CNTV_CVAL
|
||||
add r5, vcpu, r4
|
||||
ldrd r2, r3, [r5]
|
||||
mcrr p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL
|
||||
isb
|
||||
|
||||
ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
|
||||
and r2, r2, #3
|
||||
mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL
|
||||
1:
|
||||
.endm
|
||||
|
||||
.equ vmentry, 0
|
||||
.equ vmexit, 1
|
||||
|
||||
/* Configures the HSTR (Hyp System Trap Register) on entry/return
|
||||
* (hardware reset value is 0) */
|
||||
.macro set_hstr operation
|
||||
mrc p15, 4, r2, c1, c1, 3
|
||||
ldr r3, =HSTR_T(15)
|
||||
.if \operation == vmentry
|
||||
orr r2, r2, r3 @ Trap CR{15}
|
||||
.else
|
||||
bic r2, r2, r3 @ Don't trap any CRx accesses
|
||||
.endif
|
||||
mcr p15, 4, r2, c1, c1, 3
|
||||
.endm
|
||||
|
||||
/* Configures the HCPTR (Hyp Coprocessor Trap Register) on entry/return
|
||||
* (hardware reset value is 0). Keep previous value in r2.
|
||||
* An ISB is emited on vmexit/vmtrap, but executed on vmexit only if
|
||||
* VFP wasn't already enabled (always executed on vmtrap).
|
||||
* If a label is specified with vmexit, it is branched to if VFP wasn't
|
||||
* enabled.
|
||||
*/
|
||||
.macro set_hcptr operation, mask, label = none
|
||||
mrc p15, 4, r2, c1, c1, 2
|
||||
ldr r3, =\mask
|
||||
.if \operation == vmentry
|
||||
orr r3, r2, r3 @ Trap coproc-accesses defined in mask
|
||||
.else
|
||||
bic r3, r2, r3 @ Don't trap defined coproc-accesses
|
||||
.endif
|
||||
mcr p15, 4, r3, c1, c1, 2
|
||||
.if \operation != vmentry
|
||||
.if \operation == vmexit
|
||||
tst r2, #(HCPTR_TCP(10) | HCPTR_TCP(11))
|
||||
beq 1f
|
||||
.endif
|
||||
isb
|
||||
.if \label != none
|
||||
b \label
|
||||
.endif
|
||||
1:
|
||||
.endif
|
||||
.endm
|
||||
|
||||
/* Configures the HDCR (Hyp Debug Configuration Register) on entry/return
|
||||
* (hardware reset value is 0) */
|
||||
.macro set_hdcr operation
|
||||
mrc p15, 4, r2, c1, c1, 1
|
||||
ldr r3, =(HDCR_TPM|HDCR_TPMCR)
|
||||
.if \operation == vmentry
|
||||
orr r2, r2, r3 @ Trap some perfmon accesses
|
||||
.else
|
||||
bic r2, r2, r3 @ Don't trap any perfmon accesses
|
||||
.endif
|
||||
mcr p15, 4, r2, c1, c1, 1
|
||||
.endm
|
||||
|
||||
/* Enable/Disable: stage-2 trans., trap interrupts, trap wfi, trap smc */
|
||||
.macro configure_hyp_role operation
|
||||
.if \operation == vmentry
|
||||
ldr r2, [vcpu, #VCPU_HCR]
|
||||
ldr r3, [vcpu, #VCPU_IRQ_LINES]
|
||||
orr r2, r2, r3
|
||||
.else
|
||||
mov r2, #0
|
||||
.endif
|
||||
mcr p15, 4, r2, c1, c1, 0 @ HCR
|
||||
.endm
|
||||
|
||||
.macro load_vcpu
|
||||
mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR
|
||||
.endm
|
||||
Loading…
Reference in New Issue
Block a user