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PCI: dwc: Move dw_pcie_setup_rc() to DWC common code

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All RC complex drivers must call dw_pcie_setup_rc(). The ordering of the
call shouldn't be too important other than being after any RC resets.

There's a few calls of dw_pcie_setup_rc() left as drivers implementing
suspend/resume need it.

Link: https://lore.kernel.org/r/20201105211159.1814485-13-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Minghuan Lian <minghuan.Lian@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>
Cc: Yue Wang <yue.wang@Amlogic.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-amlogic@lists.infradead.org
Cc: linux-arm-kernel@axis.com
Cc: linux-arm-msm@vger.kernel.org
This commit is contained in:
Rob Herring 2020-11-05 15:11:55 -06:00 committed by Lorenzo Pieralisi
parent 59fbab1ae4
commit b9ac0f9dc8
15 changed files with 1 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/pci/controller/dwc/pci-dra7xx.c
View File

@ -181,7 +181,6 @@ static int dra7xx_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
dw_pcie_setup_rc(pp);
dra7xx_pcie_enable_interrupts(dra7xx);
return 0;

1
drivers/pci/controller/dwc/pci-exynos.c
View File

@ -372,7 +372,6 @@ static int exynos_pcie_host_init(struct pcie_port *pp)
phy_init(ep->phy);
exynos_pcie_deassert_core_reset(ep);
dw_pcie_setup_rc(pp);
exynos_pcie_assert_reset(ep);
exynos_pcie_enable_interrupts(ep);

1
drivers/pci/controller/dwc/pci-imx6.c
View File

@ -834,7 +834,6 @@ static int imx6_pcie_host_init(struct pcie_port *pp)
imx6_pcie_init_phy(imx6_pcie);
imx6_pcie_deassert_core_reset(imx6_pcie);
imx6_setup_phy_mpll(imx6_pcie);
dw_pcie_setup_rc(pp);
return 0;
}

2
drivers/pci/controller/dwc/pci-keystone.c
View File

@ -807,8 +807,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
if (ret)
return ret;
dw_pcie_setup_rc(pp);
ks_pcie_stop_link(pci);
ks_pcie_setup_rc_app_regs(ks_pcie);
writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),

2
drivers/pci/controller/dwc/pci-layerscape.c
View File

@ -136,8 +136,6 @@ static int ls_pcie_host_init(struct pcie_port *pp)
ls_pcie_drop_msg_tlp(pcie);
dw_pcie_setup_rc(pp);
return 0;
}

2
drivers/pci/controller/dwc/pci-meson.c
View File

@ -380,8 +380,6 @@ static int meson_pcie_host_init(struct pcie_port *pp)
meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
dw_pcie_setup_rc(pp);
return 0;
}

2
drivers/pci/controller/dwc/pcie-armada8k.c
View File

@ -171,8 +171,6 @@ static int armada8k_pcie_host_init(struct pcie_port *pp)
u32 reg;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
dw_pcie_setup_rc(pp);
if (!dw_pcie_link_up(pci)) {
/* Disable LTSSM state machine to enable configuration */
reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);

1
drivers/pci/controller/dwc/pcie-artpec6.c
View File

@ -328,7 +328,6 @@ static int artpec6_pcie_host_init(struct pcie_port *pp)
artpec6_pcie_init_phy(artpec6_pcie);
artpec6_pcie_deassert_core_reset(artpec6_pcie);
artpec6_pcie_wait_for_phy(artpec6_pcie);
dw_pcie_setup_rc(pp);
return 0;
}

1
drivers/pci/controller/dwc/pcie-designware-host.c
View File

@ -422,6 +422,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
goto err_free_msi;
}
dw_pcie_setup_rc(pp);
dw_pcie_msi_init(pp);
if (!dw_pcie_link_up(pci) && pci->ops->start_link) {

8
drivers/pci/controller/dwc/pcie-designware-plat.c
View File

@ -33,15 +33,7 @@ struct dw_plat_pcie_of_data {
static const struct of_device_id dw_plat_pcie_of_match[];
static int dw_plat_pcie_host_init(struct pcie_port *pp)
{
dw_pcie_setup_rc(pp);
return 0;
}
static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
.host_init = dw_plat_pcie_host_init,
};
static int dw_plat_pcie_establish_link(struct dw_pcie *pci)

3
drivers/pci/controller/dwc/pcie-histb.c
View File

@ -196,9 +196,6 @@ static int histb_pcie_host_init(struct pcie_port *pp)
regval |= PCIE_WM_RC;
histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
/* setup root complex */
dw_pcie_setup_rc(pp);
return 0;
}

2
drivers/pci/controller/dwc/pcie-kirin.c
View File

@ -405,8 +405,6 @@ static int kirin_pcie_host_init(struct pcie_port *pp)
{
pp->bridge->ops = &kirin_pci_ops;
dw_pcie_setup_rc(pp);
return 0;
}

1
drivers/pci/controller/dwc/pcie-qcom.c
View File

@ -1280,7 +1280,6 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
goto err_disable_phy;
}
dw_pcie_setup_rc(pp);
qcom_ep_reset_deassert(pcie);
return 0;

2
drivers/pci/controller/dwc/pcie-spear13xx.c
View File

@ -130,8 +130,6 @@ static int spear13xx_pcie_host_init(struct pcie_port *pp)
spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
dw_pcie_setup_rc(pp);
/*
* this controller support only 128 bytes read size, however its
* default value in capability register is 512 bytes. So force

2
drivers/pci/controller/dwc/pcie-uniphier.c
View File

@ -314,8 +314,6 @@ static int uniphier_pcie_host_init(struct pcie_port *pp)
uniphier_pcie_irq_enable(priv);
dw_pcie_setup_rc(pp);
return 0;
}