bnxt_en: Use existing MSIX vectors for all mqprio TX rings
We can now fully support sharing the same MSIX for all mqprio TX rings belonging to the same ethtool channel with the new infrastructure: 1. Allocate the proper entries for cp_ring_arr in struct bnxt_cp_ring_info to support the additional TX rings. 2. Populate the tx_ring array in struct bnxt_napi for all TX rings sharing the same NAPI. 3. bnxt_num_tx_to_cp() returns the proper NQ/completion rings to support the TX rings in the input. 4. Adjust bnxt_get_num_ring_stats() for the reduced number of ring counters with the new scheme. Reviewed-by: Andy Gospodarek <andrew.gospodarek@broadcom.com> Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -3609,7 +3609,10 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp)
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{
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bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
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int i, j, rc, ulp_base_vec, ulp_msix;
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int tcs = netdev_get_num_tc(bp->dev);
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if (!tcs)
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tcs = 1;
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ulp_msix = bnxt_get_ulp_msix_num(bp);
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ulp_base_vec = bnxt_get_ulp_msix_base(bp);
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for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
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@ -3617,6 +3620,7 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp)
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struct bnxt_cp_ring_info *cpr, *cpr2;
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struct bnxt_ring_struct *ring;
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int cp_count = 0, k;
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int rx = 0, tx = 0;
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if (!bnapi)
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continue;
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@ -3637,11 +3641,18 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp)
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if (!(bp->flags & BNXT_FLAG_CHIP_P5))
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continue;
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if (i < bp->rx_nr_rings)
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if (i < bp->rx_nr_rings) {
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cp_count++;
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if ((sh && i < bp->tx_nr_rings) ||
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(!sh && i >= bp->rx_nr_rings))
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rx = 1;
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}
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if (i < bp->tx_nr_rings_xdp) {
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cp_count++;
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tx = 1;
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} else if ((sh && i < bp->tx_nr_rings) ||
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(!sh && i >= bp->rx_nr_rings)) {
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cp_count += tcs;
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tx = 1;
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}
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cpr->cp_ring_arr = kcalloc(cp_count, sizeof(*cpr),
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GFP_KERNEL);
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@ -3656,14 +3667,19 @@ static int bnxt_alloc_cp_rings(struct bnxt *bp)
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return rc;
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cpr2->bnapi = bnapi;
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cpr2->cp_idx = k;
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if (!k && i < bp->rx_nr_rings) {
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if (!k && rx) {
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bp->rx_ring[i].rx_cpr = cpr2;
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cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_RX;
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} else {
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bp->tx_ring[j++].tx_cpr = cpr2;
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int n, tc = k - rx;
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n = BNXT_TC_TO_RING_BASE(bp, tc) + j;
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bp->tx_ring[n].tx_cpr = cpr2;
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cpr2->cp_ring_type = BNXT_NQ_HDL_TYPE_TX;
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}
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}
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if (tx)
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j++;
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}
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return 0;
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}
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@ -4704,24 +4720,33 @@ static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
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else
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j = bp->rx_nr_rings;
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for (i = 0; i < bp->tx_nr_rings; i++, j++) {
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for (i = 0; i < bp->tx_nr_rings; i++) {
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struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
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struct bnxt_napi *bnapi2;
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if (bp->flags & BNXT_FLAG_CHIP_P5)
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txr->tx_ring_struct.ring_mem.flags =
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BNXT_RMEM_RING_PTE_FLAG;
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else
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txr->tx_cpr = &bp->bnapi[i]->cp_ring;
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txr->bnapi = bp->bnapi[j];
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bp->bnapi[j]->tx_ring[0] = txr;
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bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
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if (i >= bp->tx_nr_rings_xdp) {
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int k = j + BNXT_RING_TO_TC_OFF(bp, i);
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bnapi2 = bp->bnapi[k];
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txr->txq_index = i - bp->tx_nr_rings_xdp;
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bp->bnapi[j]->tx_int = bnxt_tx_int;
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txr->tx_napi_idx =
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BNXT_RING_TO_TC(bp, txr->txq_index);
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bnapi2->tx_ring[txr->tx_napi_idx] = txr;
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bnapi2->tx_int = bnxt_tx_int;
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} else {
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bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
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bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
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bnapi2 = bp->bnapi[j];
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bnapi2->flags |= BNXT_NAPI_FLAG_XDP;
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bnapi2->tx_ring[0] = txr;
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bnapi2->tx_int = bnxt_tx_int_xdp;
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j++;
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}
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txr->bnapi = bnapi2;
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if (!(bp->flags & BNXT_FLAG_CHIP_P5))
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txr->tx_cpr = &bnapi2->cp_ring;
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}
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rc = bnxt_alloc_stats(bp);
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@ -9099,7 +9124,7 @@ static int __bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
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static int __bnxt_num_tx_to_cp(struct bnxt *bp, int tx, int tx_sets, int tx_xdp)
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{
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return tx;
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return (tx - tx_xdp) / tx_sets + tx_xdp;
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}
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int bnxt_num_tx_to_cp(struct bnxt *bp, int tx)
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@ -13723,7 +13748,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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}
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max_irqs = bnxt_get_max_irq(pdev);
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dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
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dev = alloc_etherdev_mqs(sizeof(*bp), max_irqs * BNXT_MAX_QUEUE,
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max_irqs);
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if (!dev)
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return -ENOMEM;
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@ -528,7 +528,8 @@ static int bnxt_get_num_ring_stats(struct bnxt *bp)
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bnxt_get_num_tpa_ring_stats(bp);
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tx = NUM_RING_TX_HW_STATS;
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cmn = NUM_RING_CMN_SW_STATS;
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return rx * bp->rx_nr_rings + tx * bp->tx_nr_rings +
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return rx * bp->rx_nr_rings +
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tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) +
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cmn * bp->cp_nr_rings;
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}
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