drm/amdgpu/display/mst: adjust the logic in 2nd phase of updating payload

[why & how]
adjust the coding in dm_helpers_dp_mst_send_payload_allocation()
for reading easily.

Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wayne Lin 2023-01-18 18:01:15 +08:00 committed by Alex Deucher
parent f0127cb112
commit ba512eaa75

View File

@ -277,6 +277,7 @@ bool dm_helpers_dp_mst_send_payload_allocation(
struct drm_dp_mst_atomic_payload *payload;
enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
int ret = 0;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
@ -293,7 +294,10 @@ bool dm_helpers_dp_mst_send_payload_allocation(
clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
}
if (enable && drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload)) {
if (enable)
ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload);
if (ret) {
amdgpu_dm_set_mst_status(&aconnector->mst_status,
set_flag, false);
} else {