From 19bfa9ebebb5ec0695def57eb1d80de7e9cab369 Mon Sep 17 00:00:00 2001 From: Tomas Winkler Date: Tue, 20 Jun 2023 16:19:04 +0300 Subject: [PATCH 001/105] mtd: use refcount to prevent corruption When underlying device is removed mtd core will crash in case user space is holding open handle. Need to use proper refcounting so device is release only when has no users. Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230620131905.648089-2-alexander.usyskin@intel.com --- drivers/mtd/mtdcore.c | 72 ++++++++++++++++++++++------------------- drivers/mtd/mtdcore.h | 1 + drivers/mtd/mtdpart.c | 14 ++++---- include/linux/mtd/mtd.h | 2 +- 4 files changed, 49 insertions(+), 40 deletions(-) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index e00b12aa5ec9..6dbd596a1129 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -93,10 +93,33 @@ static void mtd_release(struct device *dev) struct mtd_info *mtd = dev_get_drvdata(dev); dev_t index = MTD_DEVT(mtd->index); + if (mtd_is_partition(mtd)) + release_mtd_partition(mtd); + /* remove /dev/mtdXro node */ device_destroy(&mtd_class, index + 1); } +static void mtd_device_release(struct kref *kref) +{ + struct mtd_info *mtd = container_of(kref, struct mtd_info, refcnt); + + debugfs_remove_recursive(mtd->dbg.dfs_dir); + + /* Try to remove the NVMEM provider */ + nvmem_unregister(mtd->nvmem); + + device_unregister(&mtd->dev); + + /* Clear dev so mtd can be safely re-registered later if desired */ + memset(&mtd->dev, 0, sizeof(mtd->dev)); + + idr_remove(&mtd_idr, mtd->index); + of_node_put(mtd_get_of_node(mtd)); + + module_put(THIS_MODULE); +} + #define MTD_DEVICE_ATTR_RO(name) \ static DEVICE_ATTR(name, 0444, mtd_##name##_show, NULL) @@ -666,7 +689,7 @@ int add_mtd_device(struct mtd_info *mtd) } mtd->index = i; - mtd->usecount = 0; + kref_init(&mtd->refcnt); /* default value if not set by driver */ if (mtd->bitflip_threshold == 0) @@ -779,7 +802,6 @@ int del_mtd_device(struct mtd_info *mtd) { int ret; struct mtd_notifier *not; - struct device_node *mtd_of_node; mutex_lock(&mtd_table_mutex); @@ -793,28 +815,8 @@ int del_mtd_device(struct mtd_info *mtd) list_for_each_entry(not, &mtd_notifiers, list) not->remove(mtd); - if (mtd->usecount) { - printk(KERN_NOTICE "Removing MTD device #%d (%s) with use count %d\n", - mtd->index, mtd->name, mtd->usecount); - ret = -EBUSY; - } else { - mtd_of_node = mtd_get_of_node(mtd); - debugfs_remove_recursive(mtd->dbg.dfs_dir); - - /* Try to remove the NVMEM provider */ - nvmem_unregister(mtd->nvmem); - - device_unregister(&mtd->dev); - - /* Clear dev so mtd can be safely re-registered later if desired */ - memset(&mtd->dev, 0, sizeof(mtd->dev)); - - idr_remove(&mtd_idr, mtd->index); - of_node_put(mtd_of_node); - - module_put(THIS_MODULE); - ret = 0; - } + kref_put(&mtd->refcnt, mtd_device_release); + ret = 0; out_error: mutex_unlock(&mtd_table_mutex); @@ -1230,19 +1232,21 @@ int __get_mtd_device(struct mtd_info *mtd) if (!try_module_get(master->owner)) return -ENODEV; + kref_get(&mtd->refcnt); + if (master->_get_device) { err = master->_get_device(mtd); if (err) { + kref_put(&mtd->refcnt, mtd_device_release); module_put(master->owner); return err; } } - master->usecount++; - while (mtd->parent) { - mtd->usecount++; + if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd->parent != master) + kref_get(&mtd->parent->refcnt); mtd = mtd->parent; } @@ -1329,18 +1333,20 @@ void __put_mtd_device(struct mtd_info *mtd) { struct mtd_info *master = mtd_get_master(mtd); - while (mtd->parent) { - --mtd->usecount; - BUG_ON(mtd->usecount < 0); - mtd = mtd->parent; - } + while (mtd != master) { + struct mtd_info *parent = mtd->parent; - master->usecount--; + kref_put(&mtd->refcnt, mtd_device_release); + mtd = parent; + } if (master->_put_device) master->_put_device(master); module_put(master->owner); + + if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) + kref_put(&master->refcnt, mtd_device_release); } EXPORT_SYMBOL_GPL(__put_mtd_device); diff --git a/drivers/mtd/mtdcore.h b/drivers/mtd/mtdcore.h index b5eefeabf310..b014861a06a6 100644 --- a/drivers/mtd/mtdcore.h +++ b/drivers/mtd/mtdcore.h @@ -12,6 +12,7 @@ int __must_check add_mtd_device(struct mtd_info *mtd); int del_mtd_device(struct mtd_info *mtd); int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); int del_mtd_partitions(struct mtd_info *); +void release_mtd_partition(struct mtd_info *mtd); struct mtd_partitions; diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index a46affbb037d..23483db8f30c 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -32,6 +32,12 @@ static inline void free_partition(struct mtd_info *mtd) kfree(mtd); } +void release_mtd_partition(struct mtd_info *mtd) +{ + WARN_ON(!list_empty(&mtd->part.node)); + free_partition(mtd); +} + static struct mtd_info *allocate_partition(struct mtd_info *parent, const struct mtd_partition *part, int partno, uint64_t cur_offset) @@ -309,13 +315,11 @@ static int __mtd_del_partition(struct mtd_info *mtd) sysfs_remove_files(&mtd->dev.kobj, mtd_partition_attrs); + list_del_init(&mtd->part.node); err = del_mtd_device(mtd); if (err) return err; - list_del(&mtd->part.node); - free_partition(mtd); - return 0; } @@ -333,6 +337,7 @@ static int __del_mtd_partitions(struct mtd_info *mtd) __del_mtd_partitions(child); pr_info("Deleting %s MTD partition\n", child->name); + list_del_init(&child->part.node); ret = del_mtd_device(child); if (ret < 0) { pr_err("Error when deleting partition \"%s\" (%d)\n", @@ -340,9 +345,6 @@ static int __del_mtd_partitions(struct mtd_info *mtd) err = ret; continue; } - - list_del(&child->part.node); - free_partition(child); } return err; diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 7c58c44662b8..914a9f974baa 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -379,7 +379,7 @@ struct mtd_info { struct module *owner; struct device dev; - int usecount; + struct kref refcnt; struct mtd_debug_info dbg; struct nvmem_device *nvmem; struct nvmem_device *otp_user_nvmem; From 79c4a56250216991f1d965ee26dcd273376e4e91 Mon Sep 17 00:00:00 2001 From: Alexander Usyskin Date: Tue, 20 Jun 2023 16:19:05 +0300 Subject: [PATCH 002/105] mtd: call external _get and _put in right order MTD provider provides mtd_info object to mtd subsystem. With kref patch the mtd_info object can be alive after provider released mtd device. Fix calling order in _get and _put functions to allow mtd provider to safely alloc and release mtd object. Execute: 1) call external _get 2) get_module 3) add internal kref in the get function and opposite order in the put one. The _put_device callback should be the last in put as the master struct memory may be freed in this callback. Signed-off-by: Alexander Usyskin Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230620131905.648089-3-alexander.usyskin@intel.com --- drivers/mtd/mtdcore.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 6dbd596a1129..2466ea466466 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1229,21 +1229,20 @@ int __get_mtd_device(struct mtd_info *mtd) struct mtd_info *master = mtd_get_master(mtd); int err; - if (!try_module_get(master->owner)) - return -ENODEV; - - kref_get(&mtd->refcnt); - if (master->_get_device) { err = master->_get_device(mtd); - - if (err) { - kref_put(&mtd->refcnt, mtd_device_release); - module_put(master->owner); + if (err) return err; - } } + if (!try_module_get(master->owner)) { + if (master->_put_device) + master->_put_device(master); + return -ENODEV; + } + + kref_get(&mtd->refcnt); + while (mtd->parent) { if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd->parent != master) kref_get(&mtd->parent->refcnt); @@ -1340,13 +1339,14 @@ void __put_mtd_device(struct mtd_info *mtd) mtd = parent; } - if (master->_put_device) - master->_put_device(master); + if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) + kref_put(&master->refcnt, mtd_device_release); module_put(master->owner); - if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) - kref_put(&master->refcnt, mtd_device_release); + /* must be the last as master can be freed in the _put_device */ + if (master->_put_device) + master->_put_device(master); } EXPORT_SYMBOL_GPL(__put_mtd_device); From 746b0f2675de6cc2197a9363873de7274c539d84 Mon Sep 17 00:00:00 2001 From: Sridharan S N Date: Fri, 23 Jun 2023 10:27:55 +0530 Subject: [PATCH 003/105] mtd: spinand: gigadevice: add support for GD5F1GQ{4,5}RExxH Add support for: GD5F1GQ5RExxH GD5F1GQ4RExxH Both are 1Gb SLC NAND flash with 4b/512b on-die ECC capability and has 2K + 64B PageSize. Signed-off-by: Sridharan S N Signed-off-by: Md Sadre Alam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230623045757.30055-2-quic_sridsn@quicinc.com --- drivers/mtd/nand/spi/gigadevice.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index cfd7c3b26dc4..987710e09441 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -511,6 +511,26 @@ static const struct spinand_info gigadevice_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ5RExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4RExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), }; static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { From aa08bf187f322b6e38810d93896d052ea7cd6758 Mon Sep 17 00:00:00 2001 From: Sridharan S N Date: Fri, 23 Jun 2023 10:27:56 +0530 Subject: [PATCH 004/105] mtd: spinand: esmt: add support for F50D2G41KA This adds support for ESMT F50D2G41KA. This is 2Gb SLC NAND flash with 8b/512b on-die ECC capability. Signed-off-by: Sridharan S N Signed-off-by: Md Sadre Alam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230623045757.30055-3-quic_sridsn@quicinc.com --- drivers/mtd/nand/spi/esmt.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mtd/nand/spi/esmt.c b/drivers/mtd/nand/spi/esmt.c index 1a3ffb982335..31c439a557b1 100644 --- a/drivers/mtd/nand/spi/esmt.c +++ b/drivers/mtd/nand/spi/esmt.c @@ -121,6 +121,15 @@ static const struct spinand_info esmt_c8_spinand_table[] = { &update_cache_variants), 0, SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), + SPINAND_INFO("F50D2G41KA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)), }; static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = { From dabd64be75ae38be09c35ea66037d410c68bc322 Mon Sep 17 00:00:00 2001 From: Sridharan S N Date: Fri, 23 Jun 2023 10:27:57 +0530 Subject: [PATCH 005/105] mtd: spinand: toshiba: add support for T{C,H}58NYG{0,2}S3HBAI4 and TH58NYG3S0HBAI6 Add support for: TC58NYG0S3HBAI4 - 1Gb SLC NAND flash TH58NYG2S3HBAI4 - 4Gb SLC NAND flash TH58NYG3S0HBAI6 - 8Gb SLC NAND flash All of these has 8b/512b on-die ECC capability Signed-off-by: Sridharan S N Signed-off-by: Md Sadre Alam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230623045757.30055-4-quic_sridsn@quicinc.com --- drivers/mtd/nand/spi/toshiba.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c index 7380b1ebaccd..cd027b41dd58 100644 --- a/drivers/mtd/nand/spi/toshiba.c +++ b/drivers/mtd/nand/spi/toshiba.c @@ -266,6 +266,39 @@ static const struct spinand_info toshiba_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 1Gb (1st generation) */ + SPINAND_INFO("TC58NYG0S3HBAI4", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1), + NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 4Gb (1st generation) */ + SPINAND_INFO("TH58NYG2S3HBAI4", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xAC), + NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 2, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_x4_variants, + &update_cache_x4_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), + /* 1.8V 8Gb (1st generation) */ + SPINAND_INFO("TH58NYG3S0HBAI6", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA3), + NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_x4_variants, + &update_cache_x4_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout, + tx58cxgxsxraix_ecc_get_status)), }; static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = { From ecdaf0ee79156ce0c103cc1a7e38634fa0de6a5a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:30 +0200 Subject: [PATCH 006/105] nand: oxnas_nand: remove obsolete raw nand driver Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 nand. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Miquel Raynal Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230630-topic-oxnas-upstream-remove-v2-5-fb6ab3dea87c@linaro.org --- drivers/mtd/nand/raw/Kconfig | 7 - drivers/mtd/nand/raw/Makefile | 1 - drivers/mtd/nand/raw/oxnas_nand.c | 209 ------------------------------ 3 files changed, 217 deletions(-) delete mode 100644 drivers/mtd/nand/raw/oxnas_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..5b871e2f5c5e 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -204,13 +204,6 @@ config MTD_NAND_BCM47XXNFLASH registered by bcma as platform devices. This enables driver for NAND flash memories. For now only BCM4706 is supported. -config MTD_NAND_OXNAS - tristate "Oxford Semiconductor NAND controller" - depends on ARCH_OXNAS || COMPILE_TEST - depends on HAS_IOMEM - help - This enables the NAND flash controller on Oxford Semiconductor SoCs. - config MTD_NAND_MPC5121_NFC tristate "MPC5121 NAND controller" depends on PPC_MPC512x diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d93e861d8ba7..25120a4afada 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_MTD_NAND_MARVELL) += marvell_nand.o obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -obj-$(CONFIG_MTD_NAND_OXNAS) += oxnas_nand.o obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_MTD_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o diff --git a/drivers/mtd/nand/raw/oxnas_nand.c b/drivers/mtd/nand/raw/oxnas_nand.c deleted file mode 100644 index e3c9807df1cd..000000000000 --- a/drivers/mtd/nand/raw/oxnas_nand.c +++ /dev/null @@ -1,209 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Oxford Semiconductor OXNAS NAND driver - - * Copyright (C) 2016 Neil Armstrong - * Heavily based on plat_nand.c : - * Author: Vitaly Wool - * Copyright (C) 2013 Ma Haijun - * Copyright (C) 2012 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Nand commands */ -#define OXNAS_NAND_CMD_ALE BIT(18) -#define OXNAS_NAND_CMD_CLE BIT(19) - -#define OXNAS_NAND_MAX_CHIPS 1 - -struct oxnas_nand_ctrl { - struct nand_controller base; - void __iomem *io_base; - struct clk *clk; - struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS]; - unsigned int nchips; -}; - -static uint8_t oxnas_nand_read_byte(struct nand_chip *chip) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - return readb(oxnas->io_base); -} - -static void oxnas_nand_read_buf(struct nand_chip *chip, u8 *buf, int len) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - ioread8_rep(oxnas->io_base, buf, len); -} - -static void oxnas_nand_write_buf(struct nand_chip *chip, const u8 *buf, - int len) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - iowrite8_rep(oxnas->io_base, buf, len); -} - -/* Single CS command control */ -static void oxnas_nand_cmd_ctrl(struct nand_chip *chip, int cmd, - unsigned int ctrl) -{ - struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip); - - if (ctrl & NAND_CLE) - writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE); - else if (ctrl & NAND_ALE) - writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE); -} - -/* - * Probe for the NAND device. - */ -static int oxnas_nand_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *nand_np; - struct oxnas_nand_ctrl *oxnas; - struct nand_chip *chip; - struct mtd_info *mtd; - int count = 0; - int err = 0; - int i; - - /* Allocate memory for the device structure (and zero it) */ - oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas), - GFP_KERNEL); - if (!oxnas) - return -ENOMEM; - - nand_controller_init(&oxnas->base); - - oxnas->io_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(oxnas->io_base)) - return PTR_ERR(oxnas->io_base); - - oxnas->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(oxnas->clk)) - oxnas->clk = NULL; - - /* Only a single chip node is supported */ - count = of_get_child_count(np); - if (count > 1) - return -EINVAL; - - err = clk_prepare_enable(oxnas->clk); - if (err) - return err; - - device_reset_optional(&pdev->dev); - - for_each_child_of_node(np, nand_np) { - chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), - GFP_KERNEL); - if (!chip) { - err = -ENOMEM; - goto err_release_child; - } - - chip->controller = &oxnas->base; - - nand_set_flash_node(chip, nand_np); - nand_set_controller_data(chip, oxnas); - - mtd = nand_to_mtd(chip); - mtd->dev.parent = &pdev->dev; - mtd->priv = chip; - - chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl; - chip->legacy.read_buf = oxnas_nand_read_buf; - chip->legacy.read_byte = oxnas_nand_read_byte; - chip->legacy.write_buf = oxnas_nand_write_buf; - chip->legacy.chip_delay = 30; - - /* Scan to find existence of the device */ - err = nand_scan(chip, 1); - if (err) - goto err_release_child; - - err = mtd_device_register(mtd, NULL, 0); - if (err) - goto err_cleanup_nand; - - oxnas->chips[oxnas->nchips++] = chip; - } - - /* Exit if no chips found */ - if (!oxnas->nchips) { - err = -ENODEV; - goto err_clk_unprepare; - } - - platform_set_drvdata(pdev, oxnas); - - return 0; - -err_cleanup_nand: - nand_cleanup(chip); -err_release_child: - of_node_put(nand_np); - - for (i = 0; i < oxnas->nchips; i++) { - chip = oxnas->chips[i]; - WARN_ON(mtd_device_unregister(nand_to_mtd(chip))); - nand_cleanup(chip); - } - -err_clk_unprepare: - clk_disable_unprepare(oxnas->clk); - return err; -} - -static void oxnas_nand_remove(struct platform_device *pdev) -{ - struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev); - struct nand_chip *chip; - int i; - - for (i = 0; i < oxnas->nchips; i++) { - chip = oxnas->chips[i]; - WARN_ON(mtd_device_unregister(nand_to_mtd(chip))); - nand_cleanup(chip); - } - - clk_disable_unprepare(oxnas->clk); -} - -static const struct of_device_id oxnas_nand_match[] = { - { .compatible = "oxsemi,ox820-nand" }, - {}, -}; -MODULE_DEVICE_TABLE(of, oxnas_nand_match); - -static struct platform_driver oxnas_nand_driver = { - .probe = oxnas_nand_probe, - .remove_new = oxnas_nand_remove, - .driver = { - .name = "oxnas_nand", - .of_match_table = oxnas_nand_match, - }, -}; - -module_platform_driver(oxnas_nand_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Neil Armstrong "); -MODULE_DESCRIPTION("Oxnas NAND driver"); -MODULE_ALIAS("platform:oxnas_nand"); From b7c9b576b5f61fe4b8705bf419a1fb09541e4be8 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 30 Jun 2023 18:58:31 +0200 Subject: [PATCH 007/105] dt-bindings: mtd: oxnas-nand: remove obsolete bindings Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove the for OX810 and OX820 nand bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Acked-by: Miquel Raynal Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230630-topic-oxnas-upstream-remove-v2-6-fb6ab3dea87c@linaro.org --- .../devicetree/bindings/mtd/oxnas-nand.txt | 41 ------------------- 1 file changed, 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mtd/oxnas-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt b/Documentation/devicetree/bindings/mtd/oxnas-nand.txt deleted file mode 100644 index 2ba07fc8b79c..000000000000 --- a/Documentation/devicetree/bindings/mtd/oxnas-nand.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Oxford Semiconductor OXNAS NAND Controller - -Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings. - -Required properties: - - compatible: "oxsemi,ox820-nand" - - reg: Base address and length for NAND mapped memory. - -Optional Properties: - - clocks: phandle to the NAND gate clock if needed. - - resets: phandle to the NAND reset control if needed. - -Example: - -nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk CLK_820_NAND>; - resets = <&reset RESET_NAND>; - #address-cells = <1>; - #size-cells = <0>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - read-only; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; From 079c8d9da26ed041a54706de68b754337e6df17e Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Wed, 5 Jul 2023 13:43:57 +0300 Subject: [PATCH 008/105] mtd: rawnand: export 'nand_exit_status_op()' Export this function to work in pair with 'nand_status_op()' which is already exported. Signed-off-by: Arseniy Krasnov Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230705104403.696680-2-AVKrasnov@sberdevices.ru --- drivers/mtd/nand/raw/nand_base.c | 1 + include/linux/mtd/rawnand.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index a6af521832aa..d4b55155aeae 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -1885,6 +1885,7 @@ int nand_exit_status_op(struct nand_chip *chip) return 0; } +EXPORT_SYMBOL_GPL(nand_exit_status_op); /** * nand_erase_op - Do an erase operation diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 5159d692f9ce..90a141ba2a5a 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -1540,6 +1540,7 @@ int nand_reset_op(struct nand_chip *chip); int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, unsigned int len); int nand_status_op(struct nand_chip *chip, u8 *status); +int nand_exit_status_op(struct nand_chip *chip); int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); int nand_read_page_op(struct nand_chip *chip, unsigned int page, unsigned int offset_in_page, void *buf, unsigned int len); From cda24ab77374ea823af413249eb19ff5f49bf9ad Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Wed, 5 Jul 2023 13:43:58 +0300 Subject: [PATCH 009/105] mtd: rawnand: meson: use NAND core API to check status NAND core API already has functions to send NAND_CMD_STATUS and leave status checking mode by sending NAND_CMD_READ0, so use both of them instead of direct access to the controller registers. Signed-off-by: Arseniy Krasnov Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230705104403.696680-3-AVKrasnov@sberdevices.ru --- drivers/mtd/nand/raw/meson_nand.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index d3faf8086631..91eeac49d18f 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -400,9 +400,10 @@ static void meson_nfc_set_data_oob(struct nand_chip *nand, } } -static int meson_nfc_wait_no_rb_pin(struct meson_nfc *nfc, int timeout_ms, +static int meson_nfc_wait_no_rb_pin(struct nand_chip *nand, int timeout_ms, bool need_cmd_read0) { + struct meson_nfc *nfc = nand_get_controller_data(nand); u32 cmd, cfg; meson_nfc_cmd_idle(nfc, nfc->timing.twb); @@ -414,8 +415,7 @@ static int meson_nfc_wait_no_rb_pin(struct meson_nfc *nfc, int timeout_ms, writel(cfg, nfc->reg_base + NFC_REG_CFG); reinit_completion(&nfc->completion); - cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_STATUS; - writel(cmd, nfc->reg_base + NFC_REG_CMD); + nand_status_op(nand, NULL); /* use the max erase time as the maximum clock for waiting R/B */ cmd = NFC_CMD_RB | NFC_CMD_RB_INT_NO_PIN | nfc->timing.tbers_max; @@ -425,12 +425,8 @@ static int meson_nfc_wait_no_rb_pin(struct meson_nfc *nfc, int timeout_ms, msecs_to_jiffies(timeout_ms))) return -ETIMEDOUT; - if (need_cmd_read0) { - cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_READ0; - writel(cmd, nfc->reg_base + NFC_REG_CMD); - meson_nfc_drain_cmd(nfc); - meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT); - } + if (need_cmd_read0) + nand_exit_status_op(nand); return 0; } @@ -463,9 +459,11 @@ static int meson_nfc_wait_rb_pin(struct meson_nfc *nfc, int timeout_ms) return ret; } -static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms, +static int meson_nfc_queue_rb(struct nand_chip *nand, int timeout_ms, bool need_cmd_read0) { + struct meson_nfc *nfc = nand_get_controller_data(nand); + if (nfc->no_rb_pin) { /* This mode is used when there is no wired R/B pin. * It works like 'nand_soft_waitrdy()', but instead of @@ -477,7 +475,7 @@ static int meson_nfc_queue_rb(struct meson_nfc *nfc, int timeout_ms, * needed (for all cases except page programming - this * is reason of 'need_cmd_read0' flag). */ - return meson_nfc_wait_no_rb_pin(nfc, timeout_ms, + return meson_nfc_wait_no_rb_pin(nand, timeout_ms, need_cmd_read0); } else { return meson_nfc_wait_rb_pin(nfc, timeout_ms); @@ -687,7 +685,7 @@ static int meson_nfc_rw_cmd_prepare_and_execute(struct nand_chip *nand, if (in) { nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART; writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD); - meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tR_max), true); + meson_nfc_queue_rb(nand, PSEC_TO_MSEC(sdr->tR_max), true); } else { meson_nfc_cmd_idle(nfc, nfc->timing.tadl); } @@ -733,7 +731,7 @@ static int meson_nfc_write_page_sub(struct nand_chip *nand, cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG; writel(cmd, nfc->reg_base + NFC_REG_CMD); - meson_nfc_queue_rb(nfc, PSEC_TO_MSEC(sdr->tPROG_max), false); + meson_nfc_queue_rb(nand, PSEC_TO_MSEC(sdr->tPROG_max), false); meson_nfc_dma_buffer_release(nand, data_len, info_len, DMA_TO_DEVICE); @@ -1049,7 +1047,7 @@ static int meson_nfc_exec_op(struct nand_chip *nand, break; case NAND_OP_WAITRDY_INSTR: - meson_nfc_queue_rb(nfc, instr->ctx.waitrdy.timeout_ms, + meson_nfc_queue_rb(nand, instr->ctx.waitrdy.timeout_ms, true); if (instr->delay_ns) meson_nfc_cmd_idle(nfc, delay_idle); From 2ec2839a9062db8a592525a3fdabd42dcd9a3a9b Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:05 -0700 Subject: [PATCH 010/105] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller v7.2 controller has different ECC level field size and shift in the acc control register than its predecessor and successor controller. It needs to be set specifically. Fixes: decba6d47869 ("mtd: brcmnand: Add v7.2 controller support") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-2-william.zhang@broadcom.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 74 +++++++++++++----------- 1 file changed, 41 insertions(+), 33 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 2e9c2e2d9c9f..9ea96911d16b 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -272,6 +272,7 @@ struct brcmnand_controller { const unsigned int *page_sizes; unsigned int page_size_shift; unsigned int max_oob; + u32 ecc_level_shift; u32 features; /* for low-power standby/resume only */ @@ -596,6 +597,34 @@ enum { INTFC_CTLR_READY = BIT(31), }; +/*********************************************************************** + * NAND ACC CONTROL bitfield + * + * Some bits have remained constant throughout hardware revision, while + * others have shifted around. + ***********************************************************************/ + +/* Constant for all versions (where supported) */ +enum { + /* See BRCMNAND_HAS_CACHE_MODE */ + ACC_CONTROL_CACHE_MODE = BIT(22), + + /* See BRCMNAND_HAS_PREFETCH */ + ACC_CONTROL_PREFETCH = BIT(23), + + ACC_CONTROL_PAGE_HIT = BIT(24), + ACC_CONTROL_WR_PREEMPT = BIT(25), + ACC_CONTROL_PARTIAL_PAGE = BIT(26), + ACC_CONTROL_RD_ERASED = BIT(27), + ACC_CONTROL_FAST_PGM_RDIN = BIT(28), + ACC_CONTROL_WR_ECC = BIT(30), + ACC_CONTROL_RD_ECC = BIT(31), +}; + +#define ACC_CONTROL_ECC_SHIFT 16 +/* Only for v7.2 */ +#define ACC_CONTROL_ECC_EXT_SHIFT 13 + static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl) { #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA) @@ -737,6 +766,12 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) ctrl->features |= BRCMNAND_HAS_WP; + /* v7.2 has different ecc level shift in the acc register */ + if (ctrl->nand_version == 0x0702) + ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; + else + ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; + return 0; } @@ -931,30 +966,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) return 0; } -/*********************************************************************** - * NAND ACC CONTROL bitfield - * - * Some bits have remained constant throughout hardware revision, while - * others have shifted around. - ***********************************************************************/ - -/* Constant for all versions (where supported) */ -enum { - /* See BRCMNAND_HAS_CACHE_MODE */ - ACC_CONTROL_CACHE_MODE = BIT(22), - - /* See BRCMNAND_HAS_PREFETCH */ - ACC_CONTROL_PREFETCH = BIT(23), - - ACC_CONTROL_PAGE_HIT = BIT(24), - ACC_CONTROL_WR_PREEMPT = BIT(25), - ACC_CONTROL_PARTIAL_PAGE = BIT(26), - ACC_CONTROL_RD_ERASED = BIT(27), - ACC_CONTROL_FAST_PGM_RDIN = BIT(28), - ACC_CONTROL_WR_ECC = BIT(30), - ACC_CONTROL_RD_ECC = BIT(31), -}; - static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) { if (ctrl->nand_version == 0x0702) @@ -967,18 +978,15 @@ static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) return GENMASK(4, 0); } -#define NAND_ACC_CONTROL_ECC_SHIFT 16 -#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 - static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) { u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; - mask <<= NAND_ACC_CONTROL_ECC_SHIFT; + mask <<= ACC_CONTROL_ECC_SHIFT; /* v7.2 includes additional ECC levels */ - if (ctrl->nand_version >= 0x0702) - mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; + if (ctrl->nand_version == 0x0702) + mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; return mask; } @@ -992,8 +1000,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) if (en) { acc_control |= ecc_flags; /* enable RD/WR ECC */ - acc_control |= host->hwcfg.ecc_level - << NAND_ACC_CONTROL_ECC_SHIFT; + acc_control &= ~brcmnand_ecc_level_mask(ctrl); + acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; } else { acc_control &= ~ecc_flags; /* disable RD/WR ECC */ acc_control &= ~brcmnand_ecc_level_mask(ctrl); @@ -2561,7 +2569,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *host, tmp &= ~brcmnand_ecc_level_mask(ctrl); tmp &= ~brcmnand_spare_area_mask(ctrl); if (ctrl->nand_version >= 0x0302) { - tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; + tmp |= cfg->ecc_level << ctrl->ecc_level_shift; tmp |= cfg->spare_area_size; } nand_writereg(ctrl, acc_control_offs, tmp); From 9cc0a598b944816f2968baf2631757f22721b996 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:06 -0700 Subject: [PATCH 011/105] mtd: rawnand: brcmnand: Fix potential false time out warning If system is busy during the command status polling function, the driver may not get the chance to poll the status register till the end of time out and return the premature status. Do a final check after time out happens to ensure reading the correct status. Fixes: 9d2ee0a60b8b ("mtd: nand: brcmnand: Check flash #WP pin status before nand erase/program") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-3-william.zhang@broadcom.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 9ea96911d16b..9a373a10304d 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1080,6 +1080,14 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, cpu_relax(); } while (time_after(limit, jiffies)); + /* + * do a final check after time out in case the CPU was busy and the driver + * did not get enough time to perform the polling to avoid false alarms + */ + val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); + if ((val & mask) == expected_val) + return 0; + dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", expected_val, val & mask); From e66dd317194daae0475fe9e5577c80aa97f16cb9 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:07 -0700 Subject: [PATCH 012/105] mtd: rawnand: brcmnand: Fix crash during the panic_write When executing a NAND command within the panic write path, wait for any pending command instead of calling BUG_ON to avoid crashing while already crashing. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Reviewed-by: Kursad Oney Reviewed-by: Kamal Dasu Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-4-william.zhang@broadcom.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 9a373a10304d..b2c6396060db 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1608,7 +1608,17 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); - BUG_ON(ctrl->cmd_pending != 0); + /* + * If we came here through _panic_write and there is a pending + * command, try to wait for it. If it times out, rather than + * hitting BUG_ON, just return so we don't crash while crashing. + */ + if (oops_in_progress) { + if (ctrl->cmd_pending && + bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) + return; + } else + BUG_ON(ctrl->cmd_pending != 0); ctrl->cmd_pending = cmd; ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); From 5d53244186c9ac58cb88d76a0958ca55b83a15cd Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:08 -0700 Subject: [PATCH 013/105] mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write When the oob buffer length is not in multiple of words, the oob write function does out-of-bounds read on the oob source buffer at the last iteration. Fix that by always checking length limit on the oob buffer read and fill with 0xff when reaching the end of the buffer to the oob registers. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-5-william.zhang@broadcom.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index b2c6396060db..71d0ba652bee 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1477,19 +1477,33 @@ static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, const u8 *oob, int sas, int sector_1k) { int tbytes = sas << sector_1k; - int j; + int j, k = 0; + u32 last = 0xffffffff; + u8 *plast = (u8 *)&last; /* Adjust OOB values for 1K sector size */ if (sector_1k && (i & 0x01)) tbytes = max(0, tbytes - (int)ctrl->max_oob); tbytes = min_t(int, tbytes, ctrl->max_oob); - for (j = 0; j < tbytes; j += 4) + /* + * tbytes may not be multiple of words. Make sure we don't read out of + * the boundary and stop at last word. + */ + for (j = 0; (j + 3) < tbytes; j += 4) oob_reg_write(ctrl, j, (oob[j + 0] << 24) | (oob[j + 1] << 16) | (oob[j + 2] << 8) | (oob[j + 3] << 0)); + + /* handle the remaing bytes */ + while (j < tbytes) + plast[k++] = oob[j++]; + + if (tbytes & 0x3) + oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); + return tbytes; } From 60177390fa061c62d156f4a546e3efd90df3c183 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:09 -0700 Subject: [PATCH 014/105] mtd: rawnand: brcmnand: Fix mtd oobsize brcmnand controller can only access the flash spare area up to certain bytes based on the ECC level. It can be less than the actual flash spare area size. For example, for many NAND chip supporting ECC BCH-8, it has 226 bytes spare area. But controller can only uses 218 bytes. So brcmand driver overrides the mtd oobsize with the controller's accessible spare area size. When the nand base driver utilizes the nand_device object, it resets the oobsize back to the actual flash spare aprea size from nand_memory_organization structure and controller may not able to access all the oob area as mtd advises. This change fixes the issue by overriding the oobsize in the nand_memory_organization structure to the controller's accessible spare area size. Fixes: a7ab085d7c16 ("mtd: rawnand: Initialize the nand_device object") Signed-off-by: William Zhang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-6-william.zhang@broadcom.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 71d0ba652bee..39661e23d7d4 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -2652,6 +2652,8 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) struct nand_chip *chip = &host->chip; const struct nand_ecc_props *requirements = nanddev_get_ecc_requirements(&chip->base); + struct nand_memory_organization *memorg = + nanddev_get_memorg(&chip->base); struct brcmnand_controller *ctrl = host->ctrl; struct brcmnand_cfg *cfg = &host->hwcfg; char msg[128]; @@ -2673,10 +2675,11 @@ static int brcmnand_setup_dev(struct brcmnand_host *host) if (cfg->spare_area_size > ctrl->max_oob) cfg->spare_area_size = ctrl->max_oob; /* - * Set oobsize to be consistent with controller's spare_area_size, as - * the rest is inaccessible. + * Set mtd and memorg oobsize to be consistent with controller's + * spare_area_size, as the rest is inaccessible. */ mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); + memorg->oobsize = mtd->oobsize; cfg->device_size = mtd->size; cfg->block_size = mtd->erasesize; From 81a16e154cc03e3ec76537694ab4afb8df3965eb Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:05 +0800 Subject: [PATCH 015/105] mtd: rawnand: sunxi: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Acked-by: Jernej Skrabec Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-1-frank.li@vivo.com --- drivers/mtd/nand/raw/sunxi_nand.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 9884304634f6..db36bd755b8d 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -2087,8 +2087,7 @@ static int sunxi_nfc_probe(struct platform_device *pdev) nand_controller_init(&nfc->controller); INIT_LIST_HEAD(&nfc->chips); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - nfc->regs = devm_ioremap_resource(dev, r); + nfc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r); if (IS_ERR(nfc->regs)) return PTR_ERR(nfc->regs); From 1c66c7523f2fd2d9c8f81a2b7116252c323847a0 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:06 +0800 Subject: [PATCH 016/105] mtd: rawnand: lpc32xx_slc: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-2-frank.li@vivo.com --- drivers/mtd/nand/raw/lpc32xx_slc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c index 3139b6107660..2201264d3c37 100644 --- a/drivers/mtd/nand/raw/lpc32xx_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_slc.c @@ -836,8 +836,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) if (!host) return -ENOMEM; - rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); - host->io_base = devm_ioremap_resource(&pdev->dev, rc); + host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc); if (IS_ERR(host->io_base)) return PTR_ERR(host->io_base); From c96b3e0905b41cbf8e369faa1e4decded58860b5 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:07 +0800 Subject: [PATCH 017/105] mtd: rawnand: mxc: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-3-frank.li@vivo.com --- drivers/mtd/nand/raw/mxc_nand.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 3d4b2e8294ea..2f8dcda0f435 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1696,7 +1696,6 @@ static int mxcnd_probe(struct platform_device *pdev) struct nand_chip *this; struct mtd_info *mtd; struct mxc_nand_host *host; - struct resource *res; int err = 0; /* Allocate memory for MTD device structure and private data */ @@ -1740,17 +1739,15 @@ static int mxcnd_probe(struct platform_device *pdev) this->options |= NAND_KEEP_TIMINGS; if (host->devtype_data->needs_ip) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - host->regs_ip = devm_ioremap_resource(&pdev->dev, res); + host->regs_ip = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->regs_ip)) return PTR_ERR(host->regs_ip); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + host->base = devm_platform_ioremap_resource(pdev, 1); } else { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + host->base = devm_platform_ioremap_resource(pdev, 0); } - host->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->base)) return PTR_ERR(host->base); From 4eef841d29fac5fc8500668d1498a1ab8f9a91ce Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:08 +0800 Subject: [PATCH 018/105] mtd: rawnand: sh_flctl: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-4-frank.li@vivo.com --- drivers/mtd/nand/raw/sh_flctl.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/drivers/mtd/nand/raw/sh_flctl.c index 63bf20c41719..db243b54c953 100644 --- a/drivers/mtd/nand/raw/sh_flctl.c +++ b/drivers/mtd/nand/raw/sh_flctl.c @@ -1124,8 +1124,7 @@ static int flctl_probe(struct platform_device *pdev) if (!flctl) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - flctl->reg = devm_ioremap_resource(&pdev->dev, res); + flctl->reg = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(flctl->reg)) return PTR_ERR(flctl->reg); flctl->fifo = res->start + 0x24; /* FLDTFIFO */ From 189175e0c3554434416e75d7687011ef6c185159 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:09 +0800 Subject: [PATCH 019/105] mtd: rawnand: omap2: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-5-frank.li@vivo.com --- drivers/mtd/nand/raw/omap2.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c index db22b3af16d8..277d16f1e0bb 100644 --- a/drivers/mtd/nand/raw/omap2.c +++ b/drivers/mtd/nand/raw/omap2.c @@ -2219,8 +2219,7 @@ static int omap_nand_probe(struct platform_device *pdev) } } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - vaddr = devm_ioremap_resource(&pdev->dev, res); + vaddr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(vaddr)) return PTR_ERR(vaddr); From 68e10224a5ee9de5867152da8086acd543263c29 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:10 +0800 Subject: [PATCH 020/105] mtd: rawnand: stm32_fmc2: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-6-frank.li@vivo.com --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 10c11cecac08..2f9e43f64dd7 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -1922,8 +1922,8 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) if (!(nfc->cs_assigned & BIT(chip_cs))) continue; - res = platform_get_resource(pdev, IORESOURCE_MEM, mem_region); - nfc->data_base[chip_cs] = devm_ioremap_resource(dev, res); + nfc->data_base[chip_cs] = devm_platform_get_and_ioremap_resource(pdev, + mem_region, &res); if (IS_ERR(nfc->data_base[chip_cs])) return PTR_ERR(nfc->data_base[chip_cs]); From 9cd9dda8f06c9100997e981f11e8ef9cec042a95 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:11 +0800 Subject: [PATCH 021/105] mtd: rawnand: lpc32xx_mlc: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-7-frank.li@vivo.com --- drivers/mtd/nand/raw/lpc32xx_mlc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c index b3136ae6f4e9..488fd452611a 100644 --- a/drivers/mtd/nand/raw/lpc32xx_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c @@ -695,8 +695,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) host->pdev = pdev; - rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); - host->io_base = devm_ioremap_resource(&pdev->dev, rc); + host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc); if (IS_ERR(host->io_base)) return PTR_ERR(host->io_base); From 892ad2638a6ba33c0b5afb335501b9bb7e8a83b6 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:12 +0800 Subject: [PATCH 022/105] mtd: rawnand: fsl_upm: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-8-frank.li@vivo.com --- drivers/mtd/nand/raw/fsl_upm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c index 086426139173..f1810e2f2c07 100644 --- a/drivers/mtd/nand/raw/fsl_upm.c +++ b/drivers/mtd/nand/raw/fsl_upm.c @@ -172,8 +172,7 @@ static int fun_probe(struct platform_device *ofdev) if (!fun) return -ENOMEM; - io_res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); - fun->io_base = devm_ioremap_resource(&ofdev->dev, io_res); + fun->io_base = devm_platform_get_and_ioremap_resource(ofdev, 0, &io_res); if (IS_ERR(fun->io_base)) return PTR_ERR(fun->io_base); From 09ea085f6414e3c0d8ff034e941fe30216bd6f89 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:14 +0800 Subject: [PATCH 023/105] mtd: rawnand: atmel: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-10-frank.li@vivo.com --- drivers/mtd/nand/raw/atmel/nand-controller.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c index 81e3d682a8cd..3f494f7c7ecb 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1791,8 +1791,7 @@ atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc) nand->numcs = 1; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - nand->cs[0].io.virt = devm_ioremap_resource(dev, res); + nand->cs[0].io.virt = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(nand->cs[0].io.virt)) return PTR_ERR(nand->cs[0].io.virt); From 717a53833d0b0d735df82f041d1d000afa768cf8 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:15 +0800 Subject: [PATCH 024/105] mtd: nand: samsung: Convert to devm_platform_ioremap_resource() and devm_platform_get_and_ioremap_resource() Use devm_platform_ioremap_resource() and devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-11-frank.li@vivo.com --- drivers/mtd/nand/onenand/onenand_samsung.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/onenand/onenand_samsung.c b/drivers/mtd/nand/onenand/onenand_samsung.c index 92151aa52964..fd6890a03d55 100644 --- a/drivers/mtd/nand/onenand/onenand_samsung.c +++ b/drivers/mtd/nand/onenand/onenand_samsung.c @@ -860,8 +860,7 @@ static int s3c_onenand_probe(struct platform_device *pdev) s3c_onenand_setup(mtd); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - onenand->base = devm_ioremap_resource(&pdev->dev, r); + onenand->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); if (IS_ERR(onenand->base)) return PTR_ERR(onenand->base); @@ -874,8 +873,7 @@ static int s3c_onenand_probe(struct platform_device *pdev) this->options |= ONENAND_SKIP_UNLOCK_CHECK; if (onenand->type != TYPE_S5PC110) { - r = platform_get_resource(pdev, IORESOURCE_MEM, 1); - onenand->ahb_addr = devm_ioremap_resource(&pdev->dev, r); + onenand->ahb_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(onenand->ahb_addr)) return PTR_ERR(onenand->ahb_addr); @@ -895,8 +893,7 @@ static int s3c_onenand_probe(struct platform_device *pdev) this->subpagesize = mtd->writesize; } else { /* S5PC110 */ - r = platform_get_resource(pdev, IORESOURCE_MEM, 1); - onenand->dma_addr = devm_ioremap_resource(&pdev->dev, r); + onenand->dma_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(onenand->dma_addr)) return PTR_ERR(onenand->dma_addr); From 0e0d59f2f6ba8f26a16081fb76d301fc369cea36 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:17 +0800 Subject: [PATCH 025/105] mtd: plat-ram: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-13-frank.li@vivo.com --- drivers/mtd/maps/plat-ram.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/maps/plat-ram.c b/drivers/mtd/maps/plat-ram.c index cedd8ef9a6bf..4c921dce7396 100644 --- a/drivers/mtd/maps/plat-ram.c +++ b/drivers/mtd/maps/plat-ram.c @@ -123,8 +123,7 @@ static int platram_probe(struct platform_device *pdev) info->pdata = pdata; /* get the resource for the memory mapping */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - info->map.virt = devm_ioremap_resource(&pdev->dev, res); + info->map.virt = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(info->map.virt)) { err = PTR_ERR(info->map.virt); goto exit_free; From 6145e07e9c77a99cfe98f10b6544beef8026ce28 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:18 +0800 Subject: [PATCH 026/105] mtd: lantiq-flash: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-14-frank.li@vivo.com --- drivers/mtd/maps/lantiq-flash.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c index 67a1dbfdd72c..a1da1c8973c0 100644 --- a/drivers/mtd/maps/lantiq-flash.c +++ b/drivers/mtd/maps/lantiq-flash.c @@ -118,11 +118,9 @@ ltq_mtd_probe(struct platform_device *pdev) platform_set_drvdata(pdev, ltq_mtd); - ltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!ltq_mtd->res) { - dev_err(&pdev->dev, "failed to get memory resource\n"); - return -ENOENT; - } + ltq_mtd->map->virt = devm_platform_get_and_ioremap_resource(pdev, 0, <q_mtd->res); + if (IS_ERR(ltq_mtd->map->virt)) + return PTR_ERR(ltq_mtd->map->virt); ltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info), GFP_KERNEL); @@ -131,9 +129,6 @@ ltq_mtd_probe(struct platform_device *pdev) ltq_mtd->map->phys = ltq_mtd->res->start; ltq_mtd->map->size = resource_size(ltq_mtd->res); - ltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res); - if (IS_ERR(ltq_mtd->map->virt)) - return PTR_ERR(ltq_mtd->map->virt); ltq_mtd->map->name = ltq_map_name; ltq_mtd->map->bankwidth = 2; From a29f696aa96f94ced1655b183c9694920d8bbfe2 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:19 +0800 Subject: [PATCH 027/105] mtd: lpddr2_nvm: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-15-frank.li@vivo.com --- drivers/mtd/lpddr/lpddr2_nvm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/mtd/lpddr/lpddr2_nvm.c b/drivers/mtd/lpddr/lpddr2_nvm.c index e71af4c49096..f4e5174b2449 100644 --- a/drivers/mtd/lpddr/lpddr2_nvm.c +++ b/drivers/mtd/lpddr/lpddr2_nvm.c @@ -412,7 +412,6 @@ static int lpddr2_nvm_probe(struct platform_device *pdev) struct map_info *map; struct mtd_info *mtd; struct resource *add_range; - struct resource *control_regs; struct pcm_int_data *pcm_data; /* Allocate memory control_regs data structures */ @@ -452,8 +451,7 @@ static int lpddr2_nvm_probe(struct platform_device *pdev) simple_map_init(map); /* fill with default methods */ - control_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); - pcm_data->ctl_regs = devm_ioremap_resource(&pdev->dev, control_regs); + pcm_data->ctl_regs = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(pcm_data->ctl_regs)) return PTR_ERR(pcm_data->ctl_regs); From 1726813c2efff24a78836dd6333cd213b28cd5fa Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:20 +0800 Subject: [PATCH 028/105] mtd: st_spi_fsm: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-16-frank.li@vivo.com --- drivers/mtd/devices/st_spi_fsm.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c index 3dbb1aa80bfa..95530cbbb1e0 100644 --- a/drivers/mtd/devices/st_spi_fsm.c +++ b/drivers/mtd/devices/st_spi_fsm.c @@ -2016,7 +2016,6 @@ static int stfsm_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct flash_info *info; - struct resource *res; struct stfsm *fsm; int ret; @@ -2033,18 +2032,9 @@ static int stfsm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, fsm); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "Resource not found\n"); - return -ENODEV; - } - - fsm->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(fsm->base)) { - dev_err(&pdev->dev, - "Failed to reserve memory region %pR\n", res); + fsm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(fsm->base)) return PTR_ERR(fsm->base); - } fsm->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(fsm->clk)) { From badd019b4a2a44815e976a0108dd8e52a1a24a83 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:21 +0800 Subject: [PATCH 029/105] mtd: spear_smi: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-17-frank.li@vivo.com --- drivers/mtd/devices/spear_smi.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/mtd/devices/spear_smi.c b/drivers/mtd/devices/spear_smi.c index cc17133be297..93bca5225116 100644 --- a/drivers/mtd/devices/spear_smi.c +++ b/drivers/mtd/devices/spear_smi.c @@ -937,7 +937,6 @@ static int spear_smi_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct spear_smi_plat_data *pdata = NULL; struct spear_smi *dev; - struct resource *smi_base; int irq, ret = 0; int i; @@ -975,9 +974,7 @@ static int spear_smi_probe(struct platform_device *pdev) goto err; } - smi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - dev->io_base = devm_ioremap_resource(&pdev->dev, smi_base); + dev->io_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dev->io_base)) { ret = PTR_ERR(dev->io_base); goto err; From e1666cfd78222ae145ac260368f29fa443d97b3f Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 7 Jul 2023 12:06:22 +0800 Subject: [PATCH 030/105] mtd: physmap-core: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230707040622.78174-18-frank.li@vivo.com --- drivers/mtd/maps/physmap-core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/maps/physmap-core.c b/drivers/mtd/maps/physmap-core.c index c73854da5136..78710fbc8e7f 100644 --- a/drivers/mtd/maps/physmap-core.c +++ b/drivers/mtd/maps/physmap-core.c @@ -508,8 +508,7 @@ static int physmap_flash_probe(struct platform_device *dev) for (i = 0; i < info->nmaps; i++) { struct resource *res; - res = platform_get_resource(dev, IORESOURCE_MEM, i); - info->maps[i].virt = devm_ioremap_resource(&dev->dev, res); + info->maps[i].virt = devm_platform_get_and_ioremap_resource(dev, i, &res); if (IS_ERR(info->maps[i].virt)) { err = PTR_ERR(info->maps[i].virt); goto err_out; From 259b4d4c1308a1fa0a671be3ecd8f847c7ce2e95 Mon Sep 17 00:00:00 2001 From: Su Hui Date: Mon, 29 May 2023 09:50:11 +0800 Subject: [PATCH 031/105] mtd: devices: docg3: Remove unnecessary (void*) conversions Pointer variables of (void*) type do not require type cast. Signed-off-by: Su Hui Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230529015011.38811-1-suhui@nfschina.com --- drivers/mtd/devices/docg3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/devices/docg3.c b/drivers/mtd/devices/docg3.c index a7714e3de887..22e73dd6118b 100644 --- a/drivers/mtd/devices/docg3.c +++ b/drivers/mtd/devices/docg3.c @@ -1599,7 +1599,7 @@ static void doc_unregister_sysfs(struct platform_device *pdev, */ static int flashcontrol_show(struct seq_file *s, void *p) { - struct docg3 *docg3 = (struct docg3 *)s->private; + struct docg3 *docg3 = s->private; u8 fctrl; @@ -1621,7 +1621,7 @@ DEFINE_SHOW_ATTRIBUTE(flashcontrol); static int asic_mode_show(struct seq_file *s, void *p) { - struct docg3 *docg3 = (struct docg3 *)s->private; + struct docg3 *docg3 = s->private; int pctrl, mode; @@ -1658,7 +1658,7 @@ DEFINE_SHOW_ATTRIBUTE(asic_mode); static int device_id_show(struct seq_file *s, void *p) { - struct docg3 *docg3 = (struct docg3 *)s->private; + struct docg3 *docg3 = s->private; int id; mutex_lock(&docg3->cascade->lock); @@ -1672,7 +1672,7 @@ DEFINE_SHOW_ATTRIBUTE(device_id); static int protection_show(struct seq_file *s, void *p) { - struct docg3 *docg3 = (struct docg3 *)s->private; + struct docg3 *docg3 = s->private; int protect, dps0, dps0_low, dps0_high, dps1, dps1_low, dps1_high; mutex_lock(&docg3->cascade->lock); From cfc2928cb213d5c20b6313abb2d603c0c60d7637 Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Fri, 30 Jun 2023 19:52:32 +0530 Subject: [PATCH 032/105] dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register If the WP# signal of the flash device is either not connected or is wrongly tied to GND (that includes internal pull-downs), and the software sets the status register write disable (SRWD) bit in the status register then the status register permanently becomes read-only. To avoid this added a new boolean DT property "no-wp". If this property is set in the DT then the software avoids setting the SRWD during status register write operation. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20230630142233.63585-2-amit.kumar-mahapatra@amd.com Signed-off-by: Tudor Ambarus --- .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..97344969b02d 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. From 18d7d01a0a0eb32b78149c8259bf49504d5fa4e0 Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Fri, 30 Jun 2023 19:52:33 +0530 Subject: [PATCH 033/105] mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected Setting the status register write disable (SRWD) bit in the status register (SR) with WP# signal of the flash left floating or wrongly tied to GND (that includes internal pull-downs), will configure the SR permanently as read-only. If WP# signal is left floating or wrongly tied to GND, avoid setting SRWD bit while writing the SR during flash protection. Signed-off-by: Amit Kumar Mahapatra Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20230630142233.63585-3-amit.kumar-mahapatra@amd.com Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 +++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/debugfs.c | 1 + drivers/mtd/spi-nor/swp.c | 9 +++++++-- 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 5f29fac8669a..434c545c0ce4 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2844,6 +2844,9 @@ static void spi_nor_init_flags(struct spi_nor *nor) if (of_property_read_bool(np, "broken-flash-reset")) nor->flags |= SNOR_F_BROKEN_RESET; + if (of_property_read_bool(np, "no-wp")) + nor->flags |= SNOR_F_NO_WP; + if (flags & SPI_NOR_SWP_IS_VOLATILE) nor->flags |= SNOR_F_SWP_IS_VOLATILE; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 4fb5ff09c63a..55b5e7abce6e 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -132,6 +132,7 @@ enum spi_nor_option_flags { SNOR_F_SWP_IS_VOLATILE = BIT(13), SNOR_F_RWW = BIT(14), SNOR_F_ECC = BIT(15), + SNOR_F_NO_WP = BIT(16), }; struct spi_nor_read_command { diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index e11536fffe0f..6e163cb5b478 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -27,6 +27,7 @@ static const char *const snor_f_names[] = { SNOR_F_NAME(SWP_IS_VOLATILE), SNOR_F_NAME(RWW), SNOR_F_NAME(ECC), + SNOR_F_NAME(NO_WP), }; #undef SNOR_F_NAME diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 0ba716e84377..5ab9d5324860 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -214,8 +214,13 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) status_new = (status_old & ~mask & ~tb_mask) | val; - /* Disallow further writes if WP pin is asserted */ - status_new |= SR_SRWD; + /* + * Disallow further writes if WP# pin is neither left floating nor + * wrongly tied to GND (that includes internal pull-downs). + * WP# pin hard strapped to GND can be a valid use case. + */ + if (!(nor->flags & SNOR_F_NO_WP)) + status_new |= SR_SRWD; if (!use_top) status_new |= tb_mask; From 4b0cb4e7ab2f777c0dd07b6d381047db85801a89 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Fri, 16 Jun 2023 16:00:54 +0200 Subject: [PATCH 034/105] dt-bindings: mtd: spi-nor: clarify the need for spi-nor compatibles Most SPI NOR devices do not require a specific compatible, their ID can in general be discovered with the JEDEC READ ID opcode. In this case, only the "jedec,spi-nor" generic compatible is expected. Clarify this information in the compatible description to (i) help device-tree writers and (ii) prevent further attempts to extend this list with useless information. Signed-off-by: Miquel Raynal Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230616140054.2788684-1-miquel.raynal@bootlin.com [ta: s/JEDEC/JEDEC SFDP for clarity and s/JEDEC READ ID/READ ID as the opcode is not part of the JEDEC SFDP standard.] Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 97344969b02d..58f0cea160ef 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -43,8 +43,10 @@ properties: - const: jedec,spi-nor - const: jedec,spi-nor description: - Must also include "jedec,spi-nor" for any SPI NOR flash that can be - identified by the JEDEC READ ID opcode (0x9F). + SPI NOR flashes compatible with the JEDEC SFDP standard or which may be + identified with the READ ID opcode (0x9F) do not deserve a specific + compatible. They should instead only be matched against the generic + "jedec,spi-nor" compatible. reg: minItems: 1 From b798f7729ca66a620242435f0d325aefe0a13b31 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Thu, 13 Jul 2023 18:44:22 +0800 Subject: [PATCH 035/105] mtd: nand: omap: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230713104422.29222-1-frank.li@vivo.com --- drivers/mtd/nand/onenand/onenand_omap2.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/onenand/onenand_omap2.c b/drivers/mtd/nand/onenand/onenand_omap2.c index ff7af98604df..904df2d1538e 100644 --- a/drivers/mtd/nand/onenand/onenand_omap2.c +++ b/drivers/mtd/nand/onenand/onenand_omap2.c @@ -467,12 +467,6 @@ static int omap2_onenand_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "error getting memory resource\n"); - return -EINVAL; - } - r = of_property_read_u32(np, "reg", &val); if (r) { dev_err(dev, "reg not found in DT\n"); @@ -486,11 +480,11 @@ static int omap2_onenand_probe(struct platform_device *pdev) init_completion(&c->irq_done); init_completion(&c->dma_done); c->gpmc_cs = val; - c->phys_base = res->start; - c->onenand.base = devm_ioremap_resource(dev, res); + c->onenand.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(c->onenand.base)) return PTR_ERR(c->onenand.base); + c->phys_base = res->start; c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN); if (IS_ERR(c->int_gpiod)) { From 89550beb098e04b951df079483fb064eafc0e5fa Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Mon, 10 Jul 2023 11:14:39 +0530 Subject: [PATCH 036/105] mtd: rawnand: qcom: Implement exec_op() Implement exec_op() so we can later get rid of the legacy interface implementation. Co-developed-by: Sricharan Ramabadhran Signed-off-by: Sricharan Ramabadhran Signed-off-by: Md Sadre Alam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230710054440.23297-1-quic_mdalam@quicinc.com --- drivers/mtd/nand/raw/qcom_nandc.c | 534 +++++++++++++++++++++++++++++- 1 file changed, 531 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 72d6168d8a1b..852c6a203c78 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -157,6 +157,7 @@ #define OP_PAGE_PROGRAM_WITH_ECC 0x7 #define OP_PROGRAM_PAGE_SPARE 0x9 #define OP_BLOCK_ERASE 0xa +#define OP_CHECK_STATUS 0xc #define OP_FETCH_ID 0xb #define OP_RESET_DEVICE 0xd @@ -235,6 +236,8 @@ nandc_set_reg(chip, reg, \ */ #define NAND_ERASED_CW_SET BIT(4) +#define MAX_ADDRESS_CYCLE 5 + /* * This data type corresponds to the BAM transaction which will be used for all * NAND transfers. @@ -382,6 +385,9 @@ struct nandc_regs { * @reg_read_pos: marker for data read in reg_read_buf * * @cmd1/vld: some fixed controller register values + * + * @exec_opwrite: flag to select correct number of code word + * while reading status */ struct qcom_nand_controller { struct device *dev; @@ -432,6 +438,7 @@ struct qcom_nand_controller { int reg_read_pos; u32 cmd1, vld; + bool exec_opwrite; }; /* @@ -447,6 +454,29 @@ struct qcom_nand_boot_partition { u32 page_size; }; +/* + * Qcom op for each exec_op transfer + * + * @data_instr: data instruction pointer + * @data_instr_idx: data instruction index + * @rdy_timeout_ms: wait ready timeout in ms + * @rdy_delay_ns: Additional delay in ns + * @addr1_reg: Address1 register value + * @addr2_reg: Address2 register value + * @cmd_reg: CMD register value + * @flag: flag for misc instruction + */ +struct qcom_op { + const struct nand_op_instr *data_instr; + unsigned int data_instr_idx; + unsigned int rdy_timeout_ms; + unsigned int rdy_delay_ns; + u32 addr1_reg; + u32 addr2_reg; + u32 cmd_reg; + u8 flag; +}; + /* * NAND chip structure * @@ -1516,9 +1546,7 @@ static void pre_command(struct qcom_nand_host *host, int command) clear_read_regs(nandc); - if (command == NAND_CMD_RESET || command == NAND_CMD_READID || - command == NAND_CMD_PARAM || command == NAND_CMD_ERASE1) - clear_bam_transaction(nandc); + clear_bam_transaction(nandc); } /* @@ -2154,12 +2182,20 @@ static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, { struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; u8 *data_buf, *oob_buf = NULL; if (host->nr_boot_partitions) qcom_nandc_codeword_fixup(host, page); nand_read_page_op(chip, page, 0, NULL, 0); + nandc->buf_count = 0; + nandc->buf_start = 0; + host->use_ecc = true; + clear_read_regs(nandc); + set_address(host, 0, page); + update_rw_regs(host, ecc->steps, true, 0); + data_buf = buf; oob_buf = oob_required ? chip->oob_poi : NULL; @@ -2229,6 +2265,9 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, nand_prog_page_begin_op(chip, page, 0, NULL, 0); + set_address(host, 0, page); + nandc->buf_count = 0; + nandc->buf_start = 0; clear_read_regs(nandc); clear_bam_transaction(nandc); @@ -2867,8 +2906,497 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) return 0; } +static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 cmd, + struct qcom_op *q_op) +{ + int ret; + + switch (cmd) { + case NAND_CMD_RESET: + ret = OP_RESET_DEVICE; + break; + case NAND_CMD_READID: + ret = OP_FETCH_ID; + break; + case NAND_CMD_PARAM: + if (nandc->props->qpic_v2) + ret = OP_PAGE_READ_ONFI_READ; + else + ret = OP_PAGE_READ; + break; + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + ret = OP_BLOCK_ERASE; + break; + case NAND_CMD_STATUS: + ret = OP_CHECK_STATUS; + break; + case NAND_CMD_PAGEPROG: + ret = OP_PROGRAM_PAGE; + q_op->flag = OP_PROGRAM_PAGE; + nandc->exec_opwrite = true; + break; + } + + return ret; +} + +/* NAND framework ->exec_op() hooks and related helpers */ +static void qcom_parse_instructions(struct nand_chip *chip, + const struct nand_subop *subop, + struct qcom_op *q_op) +{ + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + const struct nand_op_instr *instr = NULL; + unsigned int op_id; + int i; + + memset(q_op, 0, sizeof(*q_op)); + + for (op_id = 0; op_id < subop->ninstrs; op_id++) { + unsigned int offset, naddrs; + const u8 *addrs; + + instr = &subop->instrs[op_id]; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + q_op->cmd_reg = qcom_op_cmd_mapping(nandc, instr->ctx.cmd.opcode, q_op); + q_op->rdy_delay_ns = instr->delay_ns; + break; + + case NAND_OP_ADDR_INSTR: + offset = nand_subop_get_addr_start_off(subop, op_id); + naddrs = nand_subop_get_num_addr_cyc(subop, op_id); + addrs = &instr->ctx.addr.addrs[offset]; + for (i = 0; i < MAX_ADDRESS_CYCLE; i++) { + if (i < 4) + q_op->addr1_reg |= (u32)addrs[i] << i * 8; + else + q_op->addr2_reg |= addrs[i]; + } + q_op->rdy_delay_ns = instr->delay_ns; + break; + + case NAND_OP_DATA_IN_INSTR: + q_op->data_instr = instr; + q_op->data_instr_idx = op_id; + q_op->rdy_delay_ns = instr->delay_ns; + fallthrough; + case NAND_OP_DATA_OUT_INSTR: + q_op->rdy_delay_ns = instr->delay_ns; + break; + + case NAND_OP_WAITRDY_INSTR: + q_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; + q_op->rdy_delay_ns = instr->delay_ns; + break; + } + } +} + +static void qcom_delay_ns(unsigned int ns) +{ + if (!ns) + return; + + if (ns < 10000) + ndelay(ns); + else + udelay(DIV_ROUND_UP(ns, 1000)); +} + +static int qcom_wait_rdy_poll(struct nand_chip *chip, unsigned int time_ms) +{ + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + unsigned long start = jiffies + msecs_to_jiffies(time_ms); + u32 flash; + + nandc_read_buffer_sync(nandc, true); + + do { + flash = le32_to_cpu(nandc->reg_read_buf[0]); + if (flash & FS_READY_BSY_N) + return 0; + cpu_relax(); + } while (time_after(start, jiffies)); + + dev_err(nandc->dev, "Timeout waiting for device to be ready:0x%08x\n", flash); + + return -ETIMEDOUT; +} + +static int qcom_read_status_exec(struct nand_chip *chip, + const struct nand_subop *subop) +{ + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + struct qcom_op q_op; + const struct nand_op_instr *instr = NULL; + unsigned int op_id = 0; + unsigned int len = 0; + int ret = 0, num_cw, i; + u32 flash_status; + + host->status = NAND_STATUS_READY | NAND_STATUS_WP; + + qcom_parse_instructions(chip, subop, &q_op); + + num_cw = nandc->exec_opwrite ? ecc->steps : 1; + nandc->exec_opwrite = false; + + nandc->buf_count = 0; + nandc->buf_start = 0; + host->use_ecc = false; + + clear_read_regs(nandc); + clear_bam_transaction(nandc); + + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + + ret = submit_descs(nandc); + if (ret) { + dev_err(nandc->dev, "failure in submitting status descriptor\n"); + free_descs(nandc); + goto err_out; + } + free_descs(nandc); + + nandc_read_buffer_sync(nandc, true); + + for (i = 0; i < num_cw; i++) { + flash_status = le32_to_cpu(nandc->reg_read_buf[i]); + + if (flash_status & FS_MPU_ERR) + host->status &= ~NAND_STATUS_WP; + + if (flash_status & FS_OP_ERR || + (i == (num_cw - 1) && (flash_status & FS_DEVICE_STS_ERR))) + host->status |= NAND_STATUS_FAIL; + } + + flash_status = host->status; + instr = q_op.data_instr; + op_id = q_op.data_instr_idx; + len = nand_subop_get_data_len(subop, op_id); + memcpy(instr->ctx.data.buf.in, &flash_status, len); + +err_out: + return ret; +} + +static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subop *subop) +{ + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_op q_op; + const struct nand_op_instr *instr = NULL; + unsigned int op_id = 0; + unsigned int len = 0; + int ret = 0; + + qcom_parse_instructions(chip, subop, &q_op); + + nandc->buf_count = 0; + nandc->buf_start = 0; + host->use_ecc = false; + + clear_read_regs(nandc); + clear_bam_transaction(nandc); + + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); + nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); + nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT, + nandc->props->is_bam ? 0 : DM_EN); + + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + + read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); + + ret = submit_descs(nandc); + if (ret) { + dev_err(nandc->dev, "failure in submitting read id descriptor\n"); + free_descs(nandc); + goto err_out; + } + free_descs(nandc); + + instr = q_op.data_instr; + op_id = q_op.data_instr_idx; + len = nand_subop_get_data_len(subop, op_id); + + nandc_read_buffer_sync(nandc, true); + memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len); + +err_out: + return ret; +} + +static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_subop *subop) +{ + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_op q_op; + int ret = 0; + + qcom_parse_instructions(chip, subop, &q_op); + + if (q_op.flag == OP_PROGRAM_PAGE) + goto wait_rdy; + + nandc->buf_count = 0; + nandc->buf_start = 0; + host->use_ecc = false; + + clear_read_regs(nandc); + clear_bam_transaction(nandc); + + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + + read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + + ret = submit_descs(nandc); + if (ret) { + dev_err(nandc->dev, "failure in submitting misc descriptor\n"); + free_descs(nandc); + goto err_out; + } + free_descs(nandc); + +wait_rdy: + qcom_delay_ns(q_op.rdy_delay_ns); + ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); + +err_out: + return ret; +} + +static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_subop *subop) +{ + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_op q_op; + const struct nand_op_instr *instr = NULL; + unsigned int op_id = 0; + unsigned int len = 0; + int ret = 0; + + qcom_parse_instructions(chip, subop, &q_op); + + q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; + + nandc->buf_count = 0; + nandc->buf_start = 0; + host->use_ecc = false; + clear_read_regs(nandc); + clear_bam_transaction(nandc); + + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + + nandc_set_reg(chip, NAND_ADDR0, 0); + nandc_set_reg(chip, NAND_ADDR1, 0); + nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE + | 512 << UD_SIZE_BYTES + | 5 << NUM_ADDR_CYCLES + | 0 << SPARE_SIZE_BYTES); + nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES + | 0 << CS_ACTIVE_BSY + | 17 << BAD_BLOCK_BYTE_NUM + | 1 << BAD_BLOCK_IN_SPARE_AREA + | 2 << WR_RD_BSY_GAP + | 0 << WIDE_FLASH + | 1 << DEV0_CFG1_ECC_DISABLE); + if (!nandc->props->qpic_v2) + nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); + + /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */ + if (!nandc->props->qpic_v2) { + nandc_set_reg(chip, NAND_DEV_CMD_VLD, + (nandc->vld & ~READ_START_VLD)); + nandc_set_reg(chip, NAND_DEV_CMD1, + (nandc->cmd1 & ~(0xFF << READ_ADDR)) + | NAND_CMD_PARAM << READ_ADDR); + } + + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + if (!nandc->props->qpic_v2) { + nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); + nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); + } + + instr = q_op.data_instr; + op_id = q_op.data_instr_idx; + len = nand_subop_get_data_len(subop, op_id); + + nandc_set_read_loc(chip, 0, 0, 0, len, 1); + + if (!nandc->props->qpic_v2) { + write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); + write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); + } + + nandc->buf_count = len; + memset(nandc->data_buffer, 0xff, nandc->buf_count); + + config_nand_single_cw_page_read(chip, false, 0); + + read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, + nandc->buf_count, 0); + + /* restore CMD1 and VLD regs */ + if (!nandc->props->qpic_v2) { + write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); + write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); + } + + ret = submit_descs(nandc); + if (ret) { + dev_err(nandc->dev, "failure in submitting param page descriptor\n"); + free_descs(nandc); + goto err_out; + } + free_descs(nandc); + + ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); + if (ret) + goto err_out; + + memcpy(instr->ctx.data.buf.in, nandc->data_buffer, len); + +err_out: + return ret; +} + +static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_subop *subop) +{ + struct qcom_nand_host *host = to_qcom_nand_host(chip); + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_op q_op; + int ret = 0; + + qcom_parse_instructions(chip, subop, &q_op); + + q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; + + nandc->buf_count = 0; + nandc->buf_start = 0; + host->use_ecc = false; + clear_read_regs(nandc); + clear_bam_transaction(nandc); + + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); + nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); + nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); + nandc_set_reg(chip, NAND_DEV0_CFG0, + host->cfg0_raw & ~(7 << CW_PER_PAGE)); + nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + + ret = submit_descs(nandc); + if (ret) { + dev_err(nandc->dev, "failure in submitting erase descriptor\n"); + free_descs(nandc); + goto err_out; + } + free_descs(nandc); + + ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); + if (ret) + goto err_out; + +err_out: + return ret; +} + +static const struct nand_op_parser qcom_op_parser = NAND_OP_PARSER( + NAND_OP_PARSER_PATTERN( + qcom_misc_cmd_type_exec, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), + NAND_OP_PARSER_PATTERN( + qcom_read_id_type_exec, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 8)), + NAND_OP_PARSER_PATTERN( + qcom_read_status_exec, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 1)), + NAND_OP_PARSER_PATTERN( + qcom_param_page_type_exec, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 512)), + NAND_OP_PARSER_PATTERN( + qcom_erase_cmd_type_exec, + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), + NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), + ); + +static int qcom_check_op(struct nand_chip *chip, + const struct nand_operation *op) +{ + const struct nand_op_instr *instr; + int op_id; + + for (op_id = 0; op_id < op->ninstrs; op_id++) { + instr = &op->instrs[op_id]; + + switch (instr->type) { + case NAND_OP_CMD_INSTR: + if (instr->ctx.cmd.opcode != NAND_CMD_RESET || + instr->ctx.cmd.opcode != NAND_CMD_READID || + instr->ctx.cmd.opcode != NAND_CMD_PARAM || + instr->ctx.cmd.opcode != NAND_CMD_ERASE1 || + instr->ctx.cmd.opcode != NAND_CMD_ERASE2 || + instr->ctx.cmd.opcode != NAND_CMD_STATUS || + instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG) + return -ENOTSUPP; + break; + default: + break; + } + } + + return 0; +} + +static int qcom_nand_exec_op(struct nand_chip *chip, + const struct nand_operation *op, + bool check_only) +{ + if (check_only) + return qcom_check_op(chip, op); + + return nand_op_parser_exec_op(chip, &qcom_op_parser, + op, check_only); +} + static const struct nand_controller_ops qcom_nandc_ops = { .attach_chip = qcom_nand_attach_chip, + .exec_op = qcom_nand_exec_op, }; static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) From 2e7f735b38a502c47894c8d5f6bd71c6957d0b62 Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Mon, 10 Jul 2023 11:14:40 +0530 Subject: [PATCH 037/105] mtd: rawnand: qcom: Remove legacy interface Remove legacy interface implementation Co-developed-by: Sricharan Ramabadhran Signed-off-by: Sricharan Ramabadhran Signed-off-by: Md Sadre Alam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230710054440.23297-2-quic_mdalam@quicinc.com --- drivers/mtd/nand/raw/qcom_nandc.c | 359 ------------------------------ 1 file changed, 359 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 852c6a203c78..b1e69d634d4a 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1303,155 +1303,6 @@ static void config_nand_cw_write(struct nand_chip *chip) write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); } -/* - * the following functions are used within chip->legacy.cmdfunc() to - * perform different NAND_CMD_* commands - */ - -/* sets up descriptors for NAND_CMD_PARAM */ -static int nandc_param(struct qcom_nand_host *host) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - /* - * NAND_CMD_PARAM is called before we know much about the FLASH chip - * in use. we configure the controller to perform a raw read of 512 - * bytes to read onfi params - */ - if (nandc->props->qpic_v2) - nandc_set_reg(chip, NAND_FLASH_CMD, OP_PAGE_READ_ONFI_READ | - PAGE_ACC | LAST_PAGE); - else - nandc_set_reg(chip, NAND_FLASH_CMD, OP_PAGE_READ | - PAGE_ACC | LAST_PAGE); - - nandc_set_reg(chip, NAND_ADDR0, 0); - nandc_set_reg(chip, NAND_ADDR1, 0); - nandc_set_reg(chip, NAND_DEV0_CFG0, 0 << CW_PER_PAGE - | 512 << UD_SIZE_BYTES - | 5 << NUM_ADDR_CYCLES - | 0 << SPARE_SIZE_BYTES); - nandc_set_reg(chip, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES - | 0 << CS_ACTIVE_BSY - | 17 << BAD_BLOCK_BYTE_NUM - | 1 << BAD_BLOCK_IN_SPARE_AREA - | 2 << WR_RD_BSY_GAP - | 0 << WIDE_FLASH - | 1 << DEV0_CFG1_ECC_DISABLE); - if (!nandc->props->qpic_v2) - nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); - - /* configure CMD1 and VLD for ONFI param probing in QPIC v1 */ - if (!nandc->props->qpic_v2) { - nandc_set_reg(chip, NAND_DEV_CMD_VLD, - (nandc->vld & ~READ_START_VLD)); - nandc_set_reg(chip, NAND_DEV_CMD1, - (nandc->cmd1 & ~(0xFF << READ_ADDR)) - | NAND_CMD_PARAM << READ_ADDR); - } - - nandc_set_reg(chip, NAND_EXEC_CMD, 1); - - if (!nandc->props->qpic_v2) { - nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); - nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); - } - - nandc_set_read_loc(chip, 0, 0, 0, 512, 1); - - if (!nandc->props->qpic_v2) { - write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); - write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); - } - - nandc->buf_count = 512; - memset(nandc->data_buffer, 0xff, nandc->buf_count); - - config_nand_single_cw_page_read(chip, false, 0); - - read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, - nandc->buf_count, 0); - - /* restore CMD1 and VLD regs */ - if (!nandc->props->qpic_v2) { - write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); - write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); - } - - return 0; -} - -/* sets up descriptors for NAND_CMD_ERASE1 */ -static int erase_block(struct qcom_nand_host *host, int page_addr) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - nandc_set_reg(chip, NAND_FLASH_CMD, - OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE); - nandc_set_reg(chip, NAND_ADDR0, page_addr); - nandc_set_reg(chip, NAND_ADDR1, 0); - nandc_set_reg(chip, NAND_DEV0_CFG0, - host->cfg0_raw & ~(7 << CW_PER_PAGE)); - nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); - nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus); - nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus); - - write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); - - read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); - - write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); - write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); - - return 0; -} - -/* sets up descriptors for NAND_CMD_READID */ -static int read_id(struct qcom_nand_host *host, int column) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - if (column == -1) - return 0; - - nandc_set_reg(chip, NAND_FLASH_CMD, OP_FETCH_ID); - nandc_set_reg(chip, NAND_ADDR0, column); - nandc_set_reg(chip, NAND_ADDR1, 0); - nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT, - nandc->props->is_bam ? 0 : DM_EN); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); - - write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); - - read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); - - return 0; -} - -/* sets up descriptors for NAND_CMD_RESET */ -static int reset(struct qcom_nand_host *host) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - nandc_set_reg(chip, NAND_FLASH_CMD, OP_RESET_DEVICE); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); - - write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); - - read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); - - return 0; -} - /* helpers to submit/free our list of dma descriptors */ static int submit_descs(struct qcom_nand_controller *nandc) { @@ -1534,150 +1385,6 @@ static void clear_read_regs(struct qcom_nand_controller *nandc) nandc_read_buffer_sync(nandc, false); } -static void pre_command(struct qcom_nand_host *host, int command) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - nandc->buf_count = 0; - nandc->buf_start = 0; - host->use_ecc = false; - host->last_command = command; - - clear_read_regs(nandc); - - clear_bam_transaction(nandc); -} - -/* - * this is called after NAND_CMD_PAGEPROG and NAND_CMD_ERASE1 to set our - * privately maintained status byte, this status byte can be read after - * NAND_CMD_STATUS is called - */ -static void parse_erase_write_errors(struct qcom_nand_host *host, int command) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct nand_ecc_ctrl *ecc = &chip->ecc; - int num_cw; - int i; - - num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1; - nandc_read_buffer_sync(nandc, true); - - for (i = 0; i < num_cw; i++) { - u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); - - if (flash_status & FS_MPU_ERR) - host->status &= ~NAND_STATUS_WP; - - if (flash_status & FS_OP_ERR || (i == (num_cw - 1) && - (flash_status & - FS_DEVICE_STS_ERR))) - host->status |= NAND_STATUS_FAIL; - } -} - -static void post_command(struct qcom_nand_host *host, int command) -{ - struct nand_chip *chip = &host->chip; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - switch (command) { - case NAND_CMD_READID: - nandc_read_buffer_sync(nandc, true); - memcpy(nandc->data_buffer, nandc->reg_read_buf, - nandc->buf_count); - break; - case NAND_CMD_PAGEPROG: - case NAND_CMD_ERASE1: - parse_erase_write_errors(host, command); - break; - default: - break; - } -} - -/* - * Implements chip->legacy.cmdfunc. It's only used for a limited set of - * commands. The rest of the commands wouldn't be called by upper layers. - * For example, NAND_CMD_READOOB would never be called because we have our own - * versions of read_oob ops for nand_ecc_ctrl. - */ -static void qcom_nandc_command(struct nand_chip *chip, unsigned int command, - int column, int page_addr) -{ - struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct nand_ecc_ctrl *ecc = &chip->ecc; - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - bool wait = false; - int ret = 0; - - pre_command(host, command); - - switch (command) { - case NAND_CMD_RESET: - ret = reset(host); - wait = true; - break; - - case NAND_CMD_READID: - nandc->buf_count = 4; - ret = read_id(host, column); - wait = true; - break; - - case NAND_CMD_PARAM: - ret = nandc_param(host); - wait = true; - break; - - case NAND_CMD_ERASE1: - ret = erase_block(host, page_addr); - wait = true; - break; - - case NAND_CMD_READ0: - /* we read the entire page for now */ - WARN_ON(column != 0); - - host->use_ecc = true; - set_address(host, 0, page_addr); - update_rw_regs(host, ecc->steps, true, 0); - break; - - case NAND_CMD_SEQIN: - WARN_ON(column != 0); - set_address(host, 0, page_addr); - break; - - case NAND_CMD_PAGEPROG: - case NAND_CMD_STATUS: - case NAND_CMD_NONE: - default: - break; - } - - if (ret) { - dev_err(nandc->dev, "failure executing command %d\n", - command); - free_descs(nandc); - return; - } - - if (wait) { - ret = submit_descs(nandc); - if (ret) - dev_err(nandc->dev, - "failure submitting descs for command %d\n", - command); - } - - free_descs(nandc); - - post_command(host, command); -} - /* * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS. @@ -2533,64 +2240,6 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs) return nand_prog_page_end_op(chip); } -/* - * the three functions below implement chip->legacy.read_byte(), - * chip->legacy.read_buf() and chip->legacy.write_buf() respectively. these - * aren't used for reading/writing page data, they are used for smaller data - * like reading id, status etc - */ -static uint8_t qcom_nandc_read_byte(struct nand_chip *chip) -{ - struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - u8 *buf = nandc->data_buffer; - u8 ret = 0x0; - - if (host->last_command == NAND_CMD_STATUS) { - ret = host->status; - - host->status = NAND_STATUS_READY | NAND_STATUS_WP; - - return ret; - } - - if (nandc->buf_start < nandc->buf_count) - ret = buf[nandc->buf_start++]; - - return ret; -} - -static void qcom_nandc_read_buf(struct nand_chip *chip, uint8_t *buf, int len) -{ - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); - - memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); - nandc->buf_start += real_len; -} - -static void qcom_nandc_write_buf(struct nand_chip *chip, const uint8_t *buf, - int len) -{ - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); - - memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); - - nandc->buf_start += real_len; -} - -/* we support only one external chip for now */ -static void qcom_nandc_select_chip(struct nand_chip *chip, int chipnr) -{ - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - - if (chipnr <= 0) - return; - - dev_warn(nandc->dev, "invalid chip select\n"); -} - /* * NAND controller page layout info * @@ -3663,14 +3312,6 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, mtd->owner = THIS_MODULE; mtd->dev.parent = dev; - chip->legacy.cmdfunc = qcom_nandc_command; - chip->legacy.select_chip = qcom_nandc_select_chip; - chip->legacy.read_byte = qcom_nandc_read_byte; - chip->legacy.read_buf = qcom_nandc_read_buf; - chip->legacy.write_buf = qcom_nandc_write_buf; - chip->legacy.set_features = nand_get_set_features_notsupp; - chip->legacy.get_features = nand_get_set_features_notsupp; - /* * the bad block marker is readable only when we read the last codeword * of a page with ECC disabled. currently, the nand_base and nand_bbt From bd60fcf27654d2acbb1f0d115daefaac6118b74c Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 3 Jul 2023 15:50:42 +1200 Subject: [PATCH 038/105] dt-bindings: mtd: Add AC5 specific binding Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to mode 3 so a specific compatible value is needed. Signed-off-by: Chris Packham Acked-by: Conor Dooley Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230703035044.2063303-2-chris.packham@alliedtelesis.co.nz --- .../devicetree/bindings/mtd/marvell,nand-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml index a10729bb1840..1ecea848e8b9 100644 --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml @@ -16,6 +16,7 @@ properties: - const: marvell,armada-8k-nand-controller - const: marvell,armada370-nand-controller - enum: + - marvell,ac5-nand-controller - marvell,armada370-nand-controller - marvell,pxa3xx-nand-controller - description: legacy bindings From 72b9a3fc4b601ab64181a036c3a78948f46b8608 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Mon, 3 Jul 2023 15:50:44 +1200 Subject: [PATCH 039/105] mtd: rawnand: marvell: add support for AC5 SoC Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only supports SDR modes up to 3. Marvell's SDK includes some predefined values for the ndtr registers. These haven't been incorporated as the existing code seems to get good values based on measurements taken with an oscilloscope. Signed-off-by: Chris Packham Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230703035044.2063303-4-chris.packham@alliedtelesis.co.nz --- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/mtd/nand/raw/marvell_nand.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5b871e2f5c5e..cbf8ae85e1ae 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -160,7 +160,7 @@ config MTD_NAND_MARVELL including: - PXA3xx processors (NFCv1) - 32-bit Armada platforms (XP, 37x, 38x, 39x) (NFCv2) - - 64-bit Aramda platforms (7k, 8k) (NFCv2) + - 64-bit Aramda platforms (7k, 8k, ac5) (NFCv2) config MTD_NAND_SLC_LPC32XX tristate "NXP LPC32xx SLC NAND controller" diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index 30c15e4e1cc0..b9a8dd324211 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -375,6 +375,7 @@ static inline struct marvell_nand_chip_sel *to_nand_sel(struct marvell_nand_chip * BCH error detection and correction algorithm, * NDCB3 register has been added * @use_dma: Use dma for data transfers + * @max_mode_number: Maximum timing mode supported by the controller */ struct marvell_nfc_caps { unsigned int max_cs_nb; @@ -383,6 +384,7 @@ struct marvell_nfc_caps { bool legacy_of_bindings; bool is_nfcv2; bool use_dma; + unsigned int max_mode_number; }; /** @@ -2376,6 +2378,9 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, if (IS_ERR(sdr)) return PTR_ERR(sdr); + if (nfc->caps->max_mode_number && nfc->caps->max_mode_number < conf->timings.mode) + return -EOPNOTSUPP; + /* * SDR timings are given in pico-seconds while NFC timings must be * expressed in NAND controller clock cycles, which is half of the @@ -3073,6 +3078,13 @@ static const struct marvell_nfc_caps marvell_armada_8k_nfc_caps = { .is_nfcv2 = true, }; +static const struct marvell_nfc_caps marvell_ac5_caps = { + .max_cs_nb = 2, + .max_rb_nb = 1, + .is_nfcv2 = true, + .max_mode_number = 3, +}; + static const struct marvell_nfc_caps marvell_armada370_nfc_caps = { .max_cs_nb = 4, .max_rb_nb = 2, @@ -3121,6 +3133,10 @@ static const struct of_device_id marvell_nfc_of_ids[] = { .compatible = "marvell,armada-8k-nand-controller", .data = &marvell_armada_8k_nfc_caps, }, + { + .compatible = "marvell,ac5-nand-controller", + .data = &marvell_ac5_caps, + }, { .compatible = "marvell,armada370-nand-controller", .data = &marvell_armada370_nfc_caps, From e0b3187f6e39a8447aa839237391221dc99169ae Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Wed, 12 Jul 2023 17:10:42 +0200 Subject: [PATCH 040/105] dt-bindings: mtd: Fix nand-controller.yaml license Binding files should be dual licensed. This file was initially written as a .txt file with no specific license, so was implicitely GPLv2. Significant part of this file and its conversion into yaml were written by Bootlin employees which agree to comply with the rules regarding the dual licensing so let's fix the SPDX tag to reflect the correct license by changing it from GPL to GPL + BSD-2-Clause. Signed-off-by: Miquel Raynal Acked-by: Maxime Ripard Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/linux-mtd/20230712151042.433593-1-miquel.raynal@bootlin.com --- Documentation/devicetree/bindings/mtd/nand-controller.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml index 83a4fe4cc29d..28167c0cf271 100644 --- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# From c3519aed2a3faf77b66350214fb5caa9a0905888 Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Tue, 11 Jul 2023 15:21:27 +0300 Subject: [PATCH 041/105] dt-bindings: nand: meson: support for 512B ECC step size Meson NAND supports both 512B and 1024B ECC step size, so replace 'const' for only 1024B step size with enum for both sizes. Signed-off-by: Arseniy Krasnov Acked-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230711122129.2635558-2-AVKrasnov@sberdevices.ru --- Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml index 787ef488dd5b..a98b5d61ea5d 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -50,7 +50,7 @@ patternProperties: const: hw nand-ecc-step-size: - const: 1024 + enum: [512, 1024] nand-ecc-strength: enum: [8, 16, 24, 30, 40, 50, 60] From de2a5d52f2c052814349013e8a77d1bc02717d74 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Jul 2023 00:16:41 +0200 Subject: [PATCH 042/105] dt-bindings: mtd: Add SEAMA partition bindings This types of NAND partitions appear in OpenWrt and U-Boot. Signed-off-by: Linus Walleij Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230713-seama-partitions-v4-1-69e577453d40@linaro.org --- .../bindings/mtd/partitions/seama.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/seama.yaml diff --git a/Documentation/devicetree/bindings/mtd/partitions/seama.yaml b/Documentation/devicetree/bindings/mtd/partitions/seama.yaml new file mode 100644 index 000000000000..4c1cbf43e81a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/seama.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/seama.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Seattle Image Partitions + +description: The SEAttle iMAge (SEAMA) partition is a type of partition + used for NAND flash devices. This type of flash image is found in some + D-Link routers such as DIR-645, DIR-842, DIR-859, DIR-860L, DIR-885L, + DIR890L and DCH-M225, as well as in WD and NEC routers on the ath79 + (MIPS), Broadcom BCM53xx, and RAMIPS platforms. This partition type + does not have children defined in the device tree, they need to be + detected by software. + +allOf: + - $ref: partition.yaml# + +maintainers: + - Linus Walleij + +properties: + compatible: + const: seama + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + compatible = "seama"; + reg = <0x0 0x800000>; + label = "firmware"; + }; + }; From 83e824a4a595132f9bd7ac4f5afff857bfc5991e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 18 Jul 2023 13:56:11 +0200 Subject: [PATCH 043/105] mtd: spi-nor: Correct flags for Winbond w25q128 The Winbond "w25q128" (actual vendor name W25Q128JV) has exactly the same flags as the sibling device "w25q128jv". The devices both require unlocking to enable write access. The actual product naming between devices vs the Linux strings in winbond.c: 0xef4018: "w25q128" W25Q128JV-IN/IQ/JQ 0xef7018: "w25q128jv" W25Q128JV-IM/JM The latter device, "w25q128jv" supports features named DTQ and QPI, otherwise it is the same. Not having the right flags has the annoying side effect that write access does not work. After this patch I can write to the flash on the Inteno XG6846 router. The flash memory also supports dual and quad SPI modes. This does not currently manifest, but by turning on SFDP parsing, the right SPI modes are emitted in /sys/kernel/debug/spi-nor/spi1.0/capabilities for this chip, so we also turn on this. Since we now have determined that SFDP parsing works on the device, we also detect the geometry using SFDP. After this dmesg and sysfs says: [ 1.062401] spi-nor spi1.0: w25q128 (16384 Kbytes) cat erasesize 65536 (16384*1024)/65536 = 256 sectors spi-nor sysfs: cat jedec_id ef4018 cat manufacturer winbond cat partname w25q128 hexdump -v -C sfdp 00000000 53 46 44 50 05 01 00 ff 00 05 01 10 80 00 00 ff 00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000040 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000050 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000060 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 00000080 e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb 00000090 fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 000000a0 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 000000b0 7a 75 7a 75 f7 a2 d5 5c 19 f7 4d ff e9 30 f8 80 Cc: stable@vger.kernel.org Suggested-by: Michael Walle Reviewed-by: Michael Walle Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230718-spi-nor-winbond-w25q128-v5-1-a73653ee46c3@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/winbond.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 834d6ba5ce70..63ba8e3a96f5 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -120,8 +120,9 @@ static const struct flash_info winbond_nor_parts[] = { NO_SFDP_FLAGS(SECT_4K) }, { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16) NO_SFDP_FLAGS(SECT_4K) }, - { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256) - NO_SFDP_FLAGS(SECT_4K) }, + { "w25q128", INFO(0xef4018, 0, 0, 0) + PARSE_SFDP + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) .fixups = &w25q256_fixups }, From d4996700abc18efcd7d933ecfbc5f066153e74ff Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 14 Jul 2023 18:07:57 +0300 Subject: [PATCH 044/105] mtd: spi-nor: rename method for enabling or disabling octal DTR Having an *_enable(..., bool enable) definition was misleading as the method is used both to enable and to disable the octal DTR mode. Splitting the method in the core in two, one to enable and another to disable the octal DTR mode does not make sense as the method is straight forward and we'd introduce code duplication. Update the core to use: int (*set_octal_dtr)(struct spi_nor *nor, bool enable); Manufacturer drivers use different sequences of commands to enable and disable the octal DTR mode, thus for clarity they shall implement it as: static int manufacturer_snor_set_octal_dtr(struct spi_nor *nor, bool enable) { return enable ? manufacturer_snor_octal_dtr_enable() : manufacturer_snor_octal_dtr_disable(); } Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20230714150757.15372-1-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 12 ++++++------ drivers/mtd/spi-nor/core.h | 4 ++-- drivers/mtd/spi-nor/micron-st.c | 4 ++-- drivers/mtd/spi-nor/spansion.c | 6 +++--- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 434c545c0ce4..273258f7e77f 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3090,17 +3090,17 @@ static int spi_nor_init_params(struct spi_nor *nor) return 0; } -/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed +/** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. * @nor: pointer to a 'struct spi_nor' * @enable: whether to enable or disable Octal DTR * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable) { int ret; - if (!nor->params->octal_dtr_enable) + if (!nor->params->set_octal_dtr) return 0; if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && @@ -3110,7 +3110,7 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) return 0; - ret = nor->params->octal_dtr_enable(nor, enable); + ret = nor->params->set_octal_dtr(nor, enable); if (ret) return ret; @@ -3171,7 +3171,7 @@ static int spi_nor_init(struct spi_nor *nor) { int err; - err = spi_nor_octal_dtr_enable(nor, true); + err = spi_nor_set_octal_dtr(nor, true); if (err) { dev_dbg(nor->dev, "octal mode not supported\n"); return err; @@ -3273,7 +3273,7 @@ static int spi_nor_suspend(struct mtd_info *mtd) int ret; /* Disable octal DTR mode if we enabled it. */ - ret = spi_nor_octal_dtr_enable(nor, false); + ret = spi_nor_set_octal_dtr(nor, false); if (ret) dev_err(nor->dev, "suspend() failed\n"); diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 55b5e7abce6e..f2fc2cf78e55 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -364,7 +364,7 @@ struct spi_nor_otp { * @erase_map: the erase map parsed from the SFDP Sector Map Parameter * Table. * @otp: SPI NOR OTP info. - * @octal_dtr_enable: enables SPI NOR octal DTR mode. + * @set_octal_dtr: enables or disables SPI NOR octal DTR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @convert_addr: converts an absolute address into something the flash @@ -398,7 +398,7 @@ struct spi_nor_flash_parameter { struct spi_nor_erase_map erase_map; struct spi_nor_otp otp; - int (*octal_dtr_enable)(struct spi_nor *nor, bool enable); + int (*set_octal_dtr)(struct spi_nor *nor, bool enable); int (*quad_enable)(struct spi_nor *nor); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); u32 (*convert_addr)(struct spi_nor *nor, u32 addr); diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 4b919756a205..f79e71d99124 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -120,7 +120,7 @@ static int micron_st_nor_octal_dtr_dis(struct spi_nor *nor) return 0; } -static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable) { return enable ? micron_st_nor_octal_dtr_en(nor) : micron_st_nor_octal_dtr_dis(nor); @@ -128,7 +128,7 @@ static int micron_st_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) static void mt35xu512aba_default_init(struct spi_nor *nor) { - nor->params->octal_dtr_enable = micron_st_nor_octal_dtr_enable; + nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr; } static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 36876aa849ed..6d6466a3436e 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -607,7 +607,7 @@ static struct spi_nor_fixups s25hx_t_fixups = { }; /** - * cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes. + * cypress_nor_set_octal_dtr() - Enable or disable octal DTR on Cypress flashes. * @nor: pointer to a 'struct spi_nor' * @enable: whether to enable or disable Octal DTR * @@ -616,7 +616,7 @@ static struct spi_nor_fixups s25hx_t_fixups = { * * Return: 0 on success, -errno otherwise. */ -static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable) { return enable ? cypress_nor_octal_dtr_en(nor) : cypress_nor_octal_dtr_dis(nor); @@ -667,7 +667,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, static void s28hx_t_late_init(struct spi_nor *nor) { - nor->params->octal_dtr_enable = cypress_nor_octal_dtr_enable; + nor->params->set_octal_dtr = cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); } From abfac0f3a457dab837fc74e47f00d829976fb0a6 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 21 Jul 2023 20:09:11 +0300 Subject: [PATCH 045/105] mtd: spi-nor: spansion: return method directly Remove unnecessary handling of method's return code and return the method directly. Link: https://lore.kernel.org/r/20230721170911.13502-1-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6d6466a3436e..314667d4b8a8 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -656,13 +656,7 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt) { - int ret; - - ret = cypress_nor_set_addr_mode_nbytes(nor); - if (ret) - return ret; - - return 0; + return cypress_nor_set_addr_mode_nbytes(nor); } static void s28hx_t_late_init(struct spi_nor *nor) From d534fd9787d5925d9637752410e3ea92ca7f4cfa Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:47 +0300 Subject: [PATCH 046/105] mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h). Introduce a new mfr_flag together with the infrastructure to allow manufacturer private data in the core. With this we remove the need to have if checks in the code at runtime and instead set the correct opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may be disabled by CFR3x[2] while CLPEF is always available. Therefore, the mfr_flag is also applied to S25Hx for safety. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-2-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/atmel.c | 8 +++- drivers/mtd/spi-nor/core.c | 23 +++++++---- drivers/mtd/spi-nor/core.h | 4 +- drivers/mtd/spi-nor/issi.c | 4 +- drivers/mtd/spi-nor/macronix.c | 4 +- drivers/mtd/spi-nor/micron-st.c | 4 +- drivers/mtd/spi-nor/spansion.c | 72 ++++++++++++++++++++++++++------- drivers/mtd/spi-nor/sst.c | 8 +++- drivers/mtd/spi-nor/winbond.c | 4 +- drivers/mtd/spi-nor/xilinx.c | 4 +- 10 files changed, 103 insertions(+), 32 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index 656dd80a0be7..58968c1e7d2f 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -48,9 +48,11 @@ static const struct spi_nor_locking_ops at25fs_nor_locking_ops = { .is_locked = at25fs_nor_is_locked, }; -static void at25fs_nor_late_init(struct spi_nor *nor) +static int at25fs_nor_late_init(struct spi_nor *nor) { nor->params->locking_ops = &at25fs_nor_locking_ops; + + return 0; } static const struct spi_nor_fixups at25fs_nor_fixups = { @@ -149,9 +151,11 @@ static const struct spi_nor_locking_ops atmel_nor_global_protection_ops = { .is_locked = atmel_nor_is_global_protected, }; -static void atmel_nor_global_protection_late_init(struct spi_nor *nor) +static int atmel_nor_global_protection_late_init(struct spi_nor *nor) { nor->params->locking_ops = &atmel_nor_global_protection_ops; + + return 0; } static const struct spi_nor_fixups atmel_nor_global_protection_fixups = { diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 273258f7e77f..614960c7d22c 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2900,16 +2900,23 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) * SFDP standard, or where SFDP tables are not defined at all. * Will replace the spi_nor_manufacturer_init_params() method. */ -static void spi_nor_late_init_params(struct spi_nor *nor) +static int spi_nor_late_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; + int ret; if (nor->manufacturer && nor->manufacturer->fixups && - nor->manufacturer->fixups->late_init) - nor->manufacturer->fixups->late_init(nor); + nor->manufacturer->fixups->late_init) { + ret = nor->manufacturer->fixups->late_init(nor); + if (ret) + return ret; + } - if (nor->info->fixups && nor->info->fixups->late_init) - nor->info->fixups->late_init(nor); + if (nor->info->fixups && nor->info->fixups->late_init) { + ret = nor->info->fixups->late_init(nor); + if (ret) + return ret; + } /* Default method kept for backward compatibility. */ if (!params->set_4byte_addr_mode) @@ -2927,6 +2934,8 @@ static void spi_nor_late_init_params(struct spi_nor *nor) if (nor->info->n_banks > 1) params->bank_size = div64_u64(params->size, nor->info->n_banks); + + return 0; } /** @@ -3085,9 +3094,7 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } - spi_nor_late_init_params(nor); - - return 0; + return spi_nor_late_init_params(nor); } /** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f2fc2cf78e55..9217379b9cfe 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -378,6 +378,7 @@ struct spi_nor_otp { * than reading the status register to indicate they * are ready for a new command * @locking_ops: SPI NOR locking methods. + * @priv: flash's private data. */ struct spi_nor_flash_parameter { u64 bank_size; @@ -406,6 +407,7 @@ struct spi_nor_flash_parameter { int (*ready)(struct spi_nor *nor); const struct spi_nor_locking_ops *locking_ops; + void *priv; }; /** @@ -432,7 +434,7 @@ struct spi_nor_fixups { const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt); int (*post_sfdp)(struct spi_nor *nor); - void (*late_init)(struct spi_nor *nor); + int (*late_init)(struct spi_nor *nor); }; /** diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 400e2b42f45a..accdf7aa2bfd 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -29,7 +29,7 @@ static const struct spi_nor_fixups is25lp256_fixups = { .post_bfpt = is25lp256_post_bfpt_fixups, }; -static void pm25lv_nor_late_init(struct spi_nor *nor) +static int pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map = &nor->params->erase_map; int i; @@ -38,6 +38,8 @@ static void pm25lv_nor_late_init(struct spi_nor *nor) for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) if (map->erase_type[i].size == 4096) map->erase_type[i].opcode = SPINOR_OP_BE_4K_PMC; + + return 0; } static const struct spi_nor_fixups pm25lv_nor_fixups = { diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 04888258e891..eb149e517c1f 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -110,10 +110,12 @@ static void macronix_nor_default_init(struct spi_nor *nor) nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; } -static void macronix_nor_late_init(struct spi_nor *nor) +static int macronix_nor_late_init(struct spi_nor *nor) { if (!nor->params->set_4byte_addr_mode) nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b; + + return 0; } static const struct spi_nor_fixups macronix_nor_fixups = { diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index f79e71d99124..6ad080c52ab5 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -429,7 +429,7 @@ static void micron_st_nor_default_init(struct spi_nor *nor) nor->params->quad_enable = NULL; } -static void micron_st_nor_late_init(struct spi_nor *nor) +static int micron_st_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; @@ -438,6 +438,8 @@ static void micron_st_nor_late_init(struct spi_nor *nor) if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_wren_en4b_ex4b; + + return 0; } static const struct spi_nor_fixups micron_st_nor_fixups = { diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 314667d4b8a8..6b2532ed053c 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,14 +4,17 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ +#include #include #include "core.h" /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ #define USE_CLSR BIT(0) +#define USE_CLPEF BIT(1) #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_VREG 0x00800000 @@ -57,22 +60,32 @@ SPI_MEM_OP_DUMMY(ndummy, 0), \ SPI_MEM_OP_DATA_IN(1, buf, 0)) -#define SPANSION_CLSR_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0), \ +#define SPANSION_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) +/** + * struct spansion_nor_params - Spansion private parameters. + * @clsr: Clear Status Register or Clear Program and Erase Failure Flag + * opcode. + */ +struct spansion_nor_params { + u8 clsr; +}; + /** * spansion_nor_clear_sr() - Clear the Status Register. * @nor: pointer to 'struct spi_nor'. */ static void spansion_nor_clear_sr(struct spi_nor *nor) { + const struct spansion_nor_params *priv_params = nor->params->priv; int ret; if (nor->spimem) { - struct spi_mem_op op = SPANSION_CLSR_OP; + struct spi_mem_op op = SPANSION_OP(priv_params->clsr); spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); @@ -528,9 +541,11 @@ static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) return 0; } -static void s25fs256t_late_init(struct spi_nor *nor) +static int s25fs256t_late_init(struct spi_nor *nor) { cypress_nor_ecc_init(nor); + + return 0; } static struct spi_nor_fixups s25fs256t_fixups = { @@ -586,7 +601,7 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) return cypress_nor_get_page_size(nor); } -static void s25hx_t_late_init(struct spi_nor *nor) +static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; @@ -598,6 +613,8 @@ static void s25hx_t_late_init(struct spi_nor *nor) /* Replace ready() with multi die version */ if (params->n_dice) params->ready = cypress_nor_sr_ready_and_clear; + + return 0; } static struct spi_nor_fixups s25hx_t_fixups = { @@ -659,10 +676,12 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, return cypress_nor_set_addr_mode_nbytes(nor); } -static void s28hx_t_late_init(struct spi_nor *nor) +static int s28hx_t_late_init(struct spi_nor *nor) { nor->params->set_octal_dtr = cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); + + return 0; } static const struct spi_nor_fixups s28hx_t_fixups = { @@ -786,47 +805,54 @@ static const struct flash_info spansion_nor_parts[] = { FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, { "s25fs256t", INFO6(0x342b19, 0x0f0890, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups = &s25fs256t_fixups }, { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, { "s25hl02gt", INFO6(0x342a1c, 0x0f0090, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups = &s25hx_t_fixups }, { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) PARSE_SFDP - MFR_FLAGS(USE_CLSR) + MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, { "s25hs02gt", INFO6(0x342b1c, 0x0f0090, 0, 0) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups = &s25hx_t_fixups }, { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) FLAGS(SPI_NOR_NO_ERASE) }, { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) PARSE_SFDP + MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, }; @@ -870,17 +896,35 @@ static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) return !(nor->bouncebuf[0] & SR_WIP); } -static void spansion_nor_late_init(struct spi_nor *nor) +static int spansion_nor_late_init(struct spi_nor *nor) { - if (nor->params->size > SZ_16M) { + struct spi_nor_flash_parameter *params = nor->params; + struct spansion_nor_params *priv_params; + u8 mfr_flags = nor->info->mfr_flags; + + if (params->size > SZ_16M) { nor->flags |= SNOR_F_4B_OPCODES; /* No small sector erase for 4-byte command set */ nor->erase_opcode = SPINOR_OP_SE; nor->mtd.erasesize = nor->info->sector_size; } - if (nor->info->mfr_flags & USE_CLSR) - nor->params->ready = spansion_nor_sr_ready_and_clear; + if (mfr_flags & (USE_CLSR | USE_CLPEF)) { + priv_params = devm_kmalloc(nor->dev, sizeof(*priv_params), + GFP_KERNEL); + if (!priv_params) + return -ENOMEM; + + if (mfr_flags & USE_CLSR) + priv_params->clsr = SPINOR_OP_CLSR; + else if (mfr_flags & USE_CLPEF) + priv_params->clsr = SPINOR_OP_CLPEF; + + params->priv = priv_params; + params->ready = spansion_nor_sr_ready_and_clear; + } + + return 0; } static const struct spi_nor_fixups spansion_nor_fixups = { diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 688eb20c763e..09fdc7023e09 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -49,9 +49,11 @@ static const struct spi_nor_locking_ops sst26vf_nor_locking_ops = { .is_locked = sst26vf_nor_is_locked, }; -static void sst26vf_nor_late_init(struct spi_nor *nor) +static int sst26vf_nor_late_init(struct spi_nor *nor) { nor->params->locking_ops = &sst26vf_nor_locking_ops; + + return 0; } static const struct spi_nor_fixups sst26vf_nor_fixups = { @@ -203,10 +205,12 @@ out: return ret; } -static void sst_nor_late_init(struct spi_nor *nor) +static int sst_nor_late_init(struct spi_nor *nor) { if (nor->info->mfr_flags & SST_WRITE) nor->mtd._write = sst_nor_write; + + return 0; } static const struct spi_nor_fixups sst_nor_fixups = { diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 63ba8e3a96f5..cd99c9a1c568 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -217,7 +217,7 @@ static const struct spi_nor_otp_ops winbond_nor_otp_ops = { .is_locked = spi_nor_otp_is_locked_sr2, }; -static void winbond_nor_late_init(struct spi_nor *nor) +static int winbond_nor_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; @@ -233,6 +233,8 @@ static void winbond_nor_late_init(struct spi_nor *nor) * from BFPT, if any. */ params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode; + + return 0; } static const struct spi_nor_fixups winbond_nor_fixups = { diff --git a/drivers/mtd/spi-nor/xilinx.c b/drivers/mtd/spi-nor/xilinx.c index 7175de8aa336..00d53eae5ee8 100644 --- a/drivers/mtd/spi-nor/xilinx.c +++ b/drivers/mtd/spi-nor/xilinx.c @@ -155,10 +155,12 @@ static int xilinx_nor_setup(struct spi_nor *nor, return 0; } -static void xilinx_nor_late_init(struct spi_nor *nor) +static int xilinx_nor_late_init(struct spi_nor *nor) { nor->params->setup = xilinx_nor_setup; nor->params->ready = xilinx_nor_sr_ready; + + return 0; } static const struct spi_nor_fixups xilinx_nor_fixups = { From 1e611e104b9acb6310b8c684d5acee0e11ca7bd1 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:48 +0300 Subject: [PATCH 047/105] mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT CFR2V[7] is assigned to Flash's address mode (3- or 4-ybte) and must not be changed when writing MEMLAT (CFR2V[3:0]). CFR2V shall be used in a read, update, write back fashion. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Signed-off-by: Takahiro Kuwano Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230726075257.12985-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6b2532ed053c..6460d2247bdf 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ +#include #include #include @@ -28,6 +29,7 @@ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 @@ -161,8 +163,18 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) int ret; u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; + op = (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, + SPINOR_REG_CYPRESS_CFR2V, 0, buf); + + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + /* Use 24 dummy cycles for memory array reads. */ - *buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; + *buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; + *buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, + SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR2V, 1, buf); From c0aa05123f116c709c816130ef4e55a6748e5e1a Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:49 +0300 Subject: [PATCH 048/105] mtd: spi-nor: spansion: prepare octal dtr methods for multi chip support Infineon's multi-chip package (MCP) devices require the octal DTR configuration to be set for each die. Split common code in dedicated methods to ease the octal DDR MCP support addition. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-4-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 50 +++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6460d2247bdf..51eabddf2b16 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -156,7 +156,7 @@ static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor) return 1; } -static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf = nor->bouncebuf; @@ -164,8 +164,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; op = (struct spi_mem_op) - CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 0, buf); + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) @@ -176,8 +175,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) *buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op = (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR2V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); if (ret) @@ -185,13 +183,33 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) nor->read_dummy = 24; + return 0; +} + +static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) +{ + struct spi_mem_op op; + u8 *buf = nor->bouncebuf; + /* Set the octal and DTR enable bits. */ buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; op = (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 1, buf); + CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, + addr, 1, buf); - ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); + return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); +} + +static int cypress_nor_octal_dtr_en(struct spi_nor *nor) +{ + u8 *buf = nor->bouncebuf; + int ret; + + ret = cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + if (ret) + return ret; + + ret = cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; @@ -209,11 +227,10 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) return 0; } -static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) { struct spi_mem_op op; u8 *buf = nor->bouncebuf; - int ret; /* * The register is 1-byte wide, but 1-byte transactions are not allowed @@ -223,9 +240,16 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; buf[1] = 0; op = (struct spi_mem_op) - CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, - SPINOR_REG_CYPRESS_CFR5V, 2, buf); - ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); + CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); + return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR); +} + +static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) +{ + u8 *buf = nor->bouncebuf; + int ret; + + ret = cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); if (ret) return ret; From 362f786ea00aa21a19ab4f1f836aa0bf9d0aab88 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:50 +0300 Subject: [PATCH 049/105] mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset All the Infineon flashes that currently support octal DTR mode define the optional SCCR SFDP table, thus all retrieve vreg_offset. Switch all the available octal DTR Infineon flashes to use the volatile register offset to set the configuration registers. The goal is to have a single pair of methods for both single/multi-chip package devices. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-5-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 51eabddf2b16..94d98b5b0ff1 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -6,6 +6,7 @@ #include #include +#include #include #include "core.h" @@ -37,8 +38,6 @@ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3) #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5 0x6 -#define SPINOR_REG_CYPRESS_CFR5V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR5) #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) @@ -202,14 +201,18 @@ static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) static int cypress_nor_octal_dtr_en(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params = nor->params; u8 *buf = nor->bouncebuf; + u64 addr; int ret; - ret = cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V); + addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; + ret = cypress_nor_set_memlat(nor, addr); if (ret) return ret; - ret = cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_set_octal_dtr_bits(nor, addr); if (ret) return ret; @@ -247,9 +250,11 @@ static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { u8 *buf = nor->bouncebuf; + u64 addr; int ret; - ret = cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V); + addr = nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_set_single_spi_bits(nor, addr); if (ret) return ret; @@ -714,7 +719,15 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, static int s28hx_t_late_init(struct spi_nor *nor) { - nor->params->set_octal_dtr = cypress_nor_set_octal_dtr; + struct spi_nor_flash_parameter *params = nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + params->set_octal_dtr = cypress_nor_set_octal_dtr; cypress_nor_ecc_init(nor); return 0; From 463d7cfd08d8cfe5def3070f2f115d7680433183 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:51 +0300 Subject: [PATCH 050/105] mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset s28hx is the sole user of cypress_nor_set_octal_dtr, which already uses vreg_offset to set octal DTR. Switch the ready method to use vreg_offset as well. This is a preparation patch. The goal is to use the same s28hx methods for the multi die version of the flash. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-6-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 94d98b5b0ff1..6d8dd800ba65 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -728,6 +728,7 @@ static int s28hx_t_late_init(struct spi_nor *nor) } params->set_octal_dtr = cypress_nor_set_octal_dtr; + params->ready = cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); return 0; From 7d896a94bf74ba0cf3a9d16d9cef98062e2017d2 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:52 +0300 Subject: [PATCH 051/105] mtd: spi-nor: spansion: add MCP support in set_octal_dtr() Infineon multi-chip package (MCP) devices require the Octal DTR configuraion to be set on each die. We can access to configuration registers in each die by using params->n_dice and params->vreg_offset[] populated from SFDP. Add MCP support in set_octal_dtr(). Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-7-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6d8dd800ba65..b3a710985f84 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -204,17 +204,19 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) const struct spi_nor_flash_parameter *params = nor->params; u8 *buf = nor->bouncebuf; u64 addr; - int ret; + int i, ret; - addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2; - ret = cypress_nor_set_memlat(nor, addr); - if (ret) - return ret; + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; + ret = cypress_nor_set_memlat(nor, addr); + if (ret) + return ret; - addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret = cypress_nor_set_octal_dtr_bits(nor, addr); - if (ret) - return ret; + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_set_octal_dtr_bits(nor, addr); + if (ret) + return ret; + } /* Read flash ID to make sure the switch was successful. */ ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, @@ -249,14 +251,17 @@ static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) { + const struct spi_nor_flash_parameter *params = nor->params; u8 *buf = nor->bouncebuf; u64 addr; - int ret; + int i, ret; - addr = nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5; - ret = cypress_nor_set_single_spi_bits(nor, addr); - if (ret) - return ret; + for (i = 0; i < params->n_dice; i++) { + addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; + ret = cypress_nor_set_single_spi_bits(nor, addr); + if (ret) + return ret; + } /* Read flash ID to make sure the switch was successful. */ ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); From eff9604390d6bb275fff1fd359f8b5e521690efa Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:53 +0300 Subject: [PATCH 052/105] mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP S28HS02GT uses RD_ANY_REG_OP to read status of each die. In Octal DTR mode, RD_ANY_REG_OP needs dummy cycles (same as params->rdsr_dummy) and data length should be 2. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-8-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index b3a710985f84..d7aa0a90949a 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -102,11 +102,17 @@ static void spansion_nor_clear_sr(struct spi_nor *nor) static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr) { + struct spi_nor_flash_parameter *params = nor->params; struct spi_mem_op op = - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, addr, + CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, 0, nor->bouncebuf); int ret; + if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { + op.dummy.nbytes = params->rdsr_dummy; + op.data.nbytes = 2; + } + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); if (ret) return ret; From 68a86d18339081a11be86e27fcaf3bc986d8fab7 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano Date: Wed, 26 Jul 2023 10:52:54 +0300 Subject: [PATCH 053/105] mtd: spi-nor: spansion: add support for S28HS02GT Add support for S28HS02GT. Infineon S28HS02GT is a 2Gb, multi-chip package, Octal SPI Flash. Signed-off-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-9-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index d7aa0a90949a..1c5671a3751a 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -693,22 +693,23 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable) static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params = nor->params; /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. */ - if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) - nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = + if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) + params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = SPINOR_OP_CYPRESS_RD_FAST; /* This flash is also missing the 4-byte Page Program opcode bit. */ - spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); /* * Since xSPI Page Program opcode is backward compatible with * Legacy SPI, use Legacy SPI opcode there as well. */ - spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); /* @@ -716,7 +717,11 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) * address bytes needed for Read Status Register command as 0 but the * actual value for that is 4. */ - nor->params->rdsr_addr_nbytes = 4; + params->rdsr_addr_nbytes = 4; + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size == SZ_256M) + params->n_dice = 2; return cypress_nor_get_page_size(nor); } @@ -916,6 +921,11 @@ static const struct flash_info spansion_nor_parts[] = { MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, + { "s28hs02gt", INFO(0x345b1c, 0, 0, 0) + PARSE_SFDP + MFR_FLAGS(USE_CLPEF) + .fixups = &s28hx_t_fixups, + }, }; /** From 39133e5f559e748904aeb6b74063882242076a61 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 26 Jul 2023 10:52:55 +0300 Subject: [PATCH 054/105] mtd: spi-nor: spansion: let SFDP determine the flash and sector size sector_size is used to determine the flash size and the erase size in case of uniform erase. n_sectors is used to determine the flash_size. But the flash size and the erase sizes are determined when parsing SFDP, let SFDP determine them. Tested-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-10-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 1c5671a3751a..30a3ffbfa381 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -873,11 +873,11 @@ static const struct flash_info spansion_nor_parts[] = { PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s25fs256t_fixups }, - { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256) + { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, - { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512) + { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, @@ -886,11 +886,11 @@ static const struct flash_info spansion_nor_parts[] = { MFR_FLAGS(USE_CLPEF) FLAGS(NO_CHIP_ERASE) .fixups = &s25hx_t_fixups }, - { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256) + { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, - { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512) + { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s25hx_t_fixups }, @@ -901,22 +901,22 @@ static const struct flash_info spansion_nor_parts[] = { .fixups = &s25hx_t_fixups }, { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1) FLAGS(SPI_NOR_NO_ERASE) }, - { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256) + { "s28hl512t", INFO(0x345a1a, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, - { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512) + { "s28hl01gt", INFO(0x345a1b, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, - { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256) + { "s28hs512t", INFO(0x345b1a, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, }, - { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512) + { "s28hs01gt", INFO(0x345b1b, 0, 0, 0) PARSE_SFDP MFR_FLAGS(USE_CLPEF) .fixups = &s28hx_t_fixups, From fb63bfad1e8f9f893c2bd5fa3eecb92aa632a3e8 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 26 Jul 2023 10:52:56 +0300 Subject: [PATCH 055/105] mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for quad_enable() All s25hx_t flashes have single or multi chip flavors and already use n_dice and vreg_offset in cypress_nor_sr_ready_and_clear. Switch s25hx_t to always use vreg_offset for the quad_enable() method, so that we use the same code base for both single and multi chip package flashes. Tested-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-11-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 30a3ffbfa381..6abef5b515a1 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -24,8 +24,6 @@ #define SPINOR_REG_CYPRESS_STR1V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) #define SPINOR_REG_CYPRESS_CFR1 0x2 -#define SPINOR_REG_CYPRESS_CFR1V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR1) #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ @@ -348,10 +346,6 @@ static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) u8 i; int ret; - if (!params->n_dice) - return cypress_nor_quad_enable_volatile_reg(nor, - SPINOR_REG_CYPRESS_CFR1V); - for (i = 0; i < params->n_dice; i++) { addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; ret = cypress_nor_quad_enable_volatile_reg(nor, addr); @@ -657,15 +651,17 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; - + params->ready = cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); - /* Replace ready() with multi die version */ - if (params->n_dice) - params->ready = cypress_nor_sr_ready_and_clear; - return 0; } From aa517a29d6457e8afcbe8e7e9eb8813594c39d1f Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 26 Jul 2023 10:52:57 +0300 Subject: [PATCH 056/105] mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use vreg_offset All users of cypress_nor_get_page_size() but S25FS256T retrieve n_dice and vreg_offset from SFDP. S25FS256T does not define the SCCR map to retrive the vreg_offset, but it does support it: SPINOR_REG_CYPRESS_VREG. Switch cypress_nor_get_page_size() to always use vreg_offset so that we use the same code base for both single and multi chip package flashes. cypress_nor_get_page_size() is now called in the post_sfdp() hook instead of post_bfpt(), as vreg_offset and n_dice are parsed after BFPT. Consequently the null checks on n_dice and vreg_offset are moved to the post_sfdp() hook. Tested-by: Takahiro Kuwano Link: https://lore.kernel.org/r/20230726075257.12985-12-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 113 ++++++++++++++------------------- 1 file changed, 48 insertions(+), 65 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6abef5b515a1..a23eb2ae9488 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -32,8 +32,6 @@ #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 -#define SPINOR_REG_CYPRESS_CFR3V \ - (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3) #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5 0x6 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) @@ -467,28 +465,17 @@ static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor) return 0; } -static int cypress_nor_get_page_size_single_chip(struct spi_nor *nor) -{ - struct spi_mem_op op = - CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, - SPINOR_REG_CYPRESS_CFR3V, 0, - nor->bouncebuf); - int ret; - - ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); - if (ret) - return ret; - - if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ) - nor->params->page_size = 512; - else - nor->params->page_size = 256; - - return 0; -} - - -static int cypress_nor_get_page_size_mcp(struct spi_nor *nor) +/** + * cypress_nor_get_page_size() - Get flash page size configuration. + * @nor: pointer to a 'struct spi_nor' + * + * The BFPT table advertises a 512B or 256B page size depending on part but the + * page size is actually configurable (with the default being 256B). Read from + * CFR3V[4] and set the correct size. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_get_page_size(struct spi_nor *nor) { struct spi_mem_op op = CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, @@ -518,23 +505,6 @@ static int cypress_nor_get_page_size_mcp(struct spi_nor *nor) return 0; } -/** - * cypress_nor_get_page_size() - Get flash page size configuration. - * @nor: pointer to a 'struct spi_nor' - * - * The BFPT table advertises a 512B or 256B page size depending on part but the - * page size is actually configurable (with the default being 256B). Read from - * CFR3V[4] and set the correct size. - * - * Return: 0 on success, -errno otherwise. - */ -static int cypress_nor_get_page_size(struct spi_nor *nor) -{ - if (nor->params->n_dice) - return cypress_nor_get_page_size_mcp(nor); - return cypress_nor_get_page_size_single_chip(nor); -} - static void cypress_nor_ecc_init(struct spi_nor *nor) { /* @@ -571,20 +541,32 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor, if (nor->bouncebuf[0]) return -ENODEV; - return cypress_nor_get_page_size(nor); + return 0; } static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; + /* + * S25FS256T does not define the SCCR map, but we would like to use the + * same code base for both single and multi chip package devices, thus + * set the vreg_offset and n_dice to be able to do so. + */ + params->vreg_offset = devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL); + if (!params->vreg_offset) + return -ENOMEM; + + params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG; + params->n_dice = 1; + /* PP_1_1_4_4B is supported but missing in 4BAIT. */ params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4_4B, SNOR_PROTO_1_1_4); - return 0; + return cypress_nor_get_page_size(nor); } static int s25fs256t_late_init(struct spi_nor *nor) @@ -619,10 +601,20 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor, static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) { - struct spi_nor_erase_type *erase_type = - nor->params->erase_map.erase_type; + struct spi_nor_flash_parameter *params = nor->params; + struct spi_nor_erase_type *erase_type = params->erase_map.erase_type; unsigned int i; + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size == SZ_256M) + params->n_dice = 2; + /* * In some parts, 3byte erase opcodes are advertised by 4BAIT. * Convert them to 4byte erase opcodes. @@ -640,10 +632,6 @@ static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) } } - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (nor->params->size == SZ_256M) - nor->params->n_dice = 2; - return cypress_nor_get_page_size(nor); } @@ -651,12 +639,6 @@ static int s25hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - /* Fast Read 4B requires mode cycles */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; params->ready = cypress_nor_sr_ready_and_clear; @@ -690,6 +672,17 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable) static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; + + if (!params->n_dice || !params->vreg_offset) { + dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", + __func__); + return -EOPNOTSUPP; + } + + /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ + if (params->size == SZ_256M) + params->n_dice = 2; + /* * On older versions of the flash the xSPI Profile 1.0 table has the * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. @@ -715,10 +708,6 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) */ params->rdsr_addr_nbytes = 4; - /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ - if (params->size == SZ_256M) - params->n_dice = 2; - return cypress_nor_get_page_size(nor); } @@ -733,12 +722,6 @@ static int s28hx_t_late_init(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; - if (!params->n_dice || !params->vreg_offset) { - dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", - __func__); - return -EOPNOTSUPP; - } - params->set_octal_dtr = cypress_nor_set_octal_dtr; params->ready = cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); From 350301a3d73b217ab3d87ae42d8fcce2795fe097 Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Mon, 17 Jul 2023 08:34:00 +0300 Subject: [PATCH 057/105] dt-bindings: nand: meson: make ECC properties dependent ECC properties 'nand-ecc-strength' and 'nand-ecc-step-size' depends on each other, so they must be both either set or not set. In first case ECC core will try to use these values if possible (by checking ECC caps provided by driver), in second case ECC core will select most optimal values for both properties. Signed-off-by: Arseniy Krasnov Acked-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230717053402.1203724-2-AVKrasnov@sberdevices.ru --- Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml index a98b5d61ea5d..1c79815e1f7f 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -66,6 +66,10 @@ patternProperties: unevaluatedProperties: false + dependencies: + nand-ecc-strength: ['nand-ecc-step-size'] + nand-ecc-step-size: ['nand-ecc-strength'] + required: - compatible From 0e1db39336d8be4ddeb9f0d99720056f3ff41310 Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Mon, 17 Jul 2023 08:34:01 +0300 Subject: [PATCH 058/105] mtd: rawnand: meson: support for 512B ECC step size Meson NAND supports both 512B and 1024B ECC step size. Signed-off-by: Arseniy Krasnov Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230717053402.1203724-3-AVKrasnov@sberdevices.ru --- drivers/mtd/nand/raw/meson_nand.c | 45 +++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index 91eeac49d18f..9bdea97abe4c 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -135,6 +135,7 @@ struct meson_nfc_nand_chip { struct meson_nand_ecc { u32 bch; u32 strength; + u32 size; }; struct meson_nfc_data { @@ -190,7 +191,8 @@ struct meson_nfc { }; enum { - NFC_ECC_BCH8_1K = 2, + NFC_ECC_BCH8_512 = 1, + NFC_ECC_BCH8_1K, NFC_ECC_BCH24_1K, NFC_ECC_BCH30_1K, NFC_ECC_BCH40_1K, @@ -198,15 +200,16 @@ enum { NFC_ECC_BCH60_1K, }; -#define MESON_ECC_DATA(b, s) { .bch = (b), .strength = (s)} +#define MESON_ECC_DATA(b, s, sz) { .bch = (b), .strength = (s), .size = (sz) } static struct meson_nand_ecc meson_ecc[] = { - MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8), - MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24), - MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30), - MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40), - MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50), - MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60), + MESON_ECC_DATA(NFC_ECC_BCH8_512, 8, 512), + MESON_ECC_DATA(NFC_ECC_BCH8_1K, 8, 1024), + MESON_ECC_DATA(NFC_ECC_BCH24_1K, 24, 1024), + MESON_ECC_DATA(NFC_ECC_BCH30_1K, 30, 1024), + MESON_ECC_DATA(NFC_ECC_BCH40_1K, 40, 1024), + MESON_ECC_DATA(NFC_ECC_BCH50_1K, 50, 1024), + MESON_ECC_DATA(NFC_ECC_BCH60_1K, 60, 1024), }; static int meson_nand_calc_ecc_bytes(int step_size, int strength) @@ -224,8 +227,27 @@ static int meson_nand_calc_ecc_bytes(int step_size, int strength) NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps, meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60); -NAND_ECC_CAPS_SINGLE(meson_axg_ecc_caps, - meson_nand_calc_ecc_bytes, 1024, 8); + +static const int axg_stepinfo_strengths[] = { 8 }; +static const struct nand_ecc_step_info axg_stepinfo_1024 = { + .stepsize = 1024, + .strengths = axg_stepinfo_strengths, + .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) +}; + +static const struct nand_ecc_step_info axg_stepinfo_512 = { + .stepsize = 512, + .strengths = axg_stepinfo_strengths, + .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) +}; + +static const struct nand_ecc_step_info axg_stepinfo[] = { axg_stepinfo_1024, axg_stepinfo_512 }; + +static const struct nand_ecc_caps meson_axg_ecc_caps = { + .stepinfos = axg_stepinfo, + .nstepinfos = ARRAY_SIZE(axg_stepinfo), + .calc_ecc_bytes = meson_nand_calc_ecc_bytes, +}; static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) { @@ -1257,7 +1279,8 @@ static int meson_nand_bch_mode(struct nand_chip *nand) return -EINVAL; for (i = 0; i < ARRAY_SIZE(meson_ecc); i++) { - if (meson_ecc[i].strength == nand->ecc.strength) { + if (meson_ecc[i].strength == nand->ecc.strength && + meson_ecc[i].size == nand->ecc.size) { meson_chip->bch_mode = meson_ecc[i].bch; return 0; } From 6680d8b67921fc732a59792dec6d3f94c031451c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 19 Jul 2023 10:43:24 +0200 Subject: [PATCH 059/105] mtd: rawnand: brcmnand: propagate init error -EPROBE_DEFER up MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MTD subsystem may return -EPROBE_DEFER if something isn't ready yet. It's important to pass that error up so device will get probed later. Signed-off-by: RafaÅ‚ MiÅ‚ecki Acked-by: Florian Fainelli Acked-by: William Zhang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230719084324.14799-1-zajec5@gmail.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 39661e23d7d4..03764b589ec5 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -3245,6 +3245,10 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) ret = brcmnand_init_cs(host, NULL); if (ret) { + if (ret == -EPROBE_DEFER) { + of_node_put(child); + goto err; + } devm_kfree(dev, host); continue; /* Try all chip-selects */ } From c2fc6b6947905eee832e9ef445df4803f0056cc6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:47:49 -0600 Subject: [PATCH 060/105] mtd: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Reviewed-by: Linus Walleij Acked-by: Heiko Stuebner Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230714174751.4060439-1-robh@kernel.org --- drivers/mtd/devices/mchp23k256.c | 2 +- drivers/mtd/devices/mchp48l640.c | 2 +- drivers/mtd/devices/mtd_dataflash.c | 1 - drivers/mtd/maps/physmap-bt1-rom.c | 1 - drivers/mtd/maps/physmap-gemini.c | 2 +- drivers/mtd/maps/physmap-ixp4xx.c | 2 +- drivers/mtd/maps/physmap-ixp4xx.h | 1 + drivers/mtd/maps/physmap-versatile.c | 2 +- drivers/mtd/maps/sun_uflash.c | 2 +- drivers/mtd/nand/ecc-mxic.c | 2 +- drivers/mtd/nand/ecc.c | 2 +- drivers/mtd/nand/onenand/onenand_omap2.c | 2 +- drivers/mtd/nand/raw/ams-delta.c | 2 +- drivers/mtd/nand/raw/davinci_nand.c | 1 - drivers/mtd/nand/raw/denali_dt.c | 1 - drivers/mtd/nand/raw/fsl_ifc_nand.c | 1 + drivers/mtd/nand/raw/fsl_upm.c | 3 ++- drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 2 +- drivers/mtd/nand/raw/ingenic/ingenic_ecc.c | 1 + drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c | 1 - drivers/mtd/nand/raw/marvell_nand.c | 3 ++- drivers/mtd/nand/raw/meson_nand.c | 1 - drivers/mtd/nand/raw/mpc5121_nfc.c | 4 ++-- drivers/mtd/nand/raw/mtk_nand.c | 1 - drivers/mtd/nand/raw/mxc_nand.c | 1 - drivers/mtd/nand/raw/ndfc.c | 3 ++- drivers/mtd/nand/raw/omap2.c | 2 +- drivers/mtd/nand/raw/pl35x-nand-controller.c | 4 +--- drivers/mtd/nand/raw/qcom_nandc.c | 2 +- drivers/mtd/nand/raw/rockchip-nand-controller.c | 1 - drivers/mtd/nand/raw/s3c2410.c | 1 - drivers/mtd/nand/raw/sh_flctl.c | 1 - drivers/mtd/nand/raw/socrates_nand.c | 3 ++- drivers/mtd/nand/raw/sunxi_nand.c | 1 - drivers/mtd/nand/raw/xway_nand.c | 3 ++- drivers/mtd/spi-nor/controllers/nxp-spifi.c | 1 - 36 files changed, 29 insertions(+), 36 deletions(-) diff --git a/drivers/mtd/devices/mchp23k256.c b/drivers/mtd/devices/mchp23k256.c index 3a6ea7a6a30c..d533475fda15 100644 --- a/drivers/mtd/devices/mchp23k256.c +++ b/drivers/mtd/devices/mchp23k256.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #define MAX_CMD_SIZE 4 diff --git a/drivers/mtd/devices/mchp48l640.c b/drivers/mtd/devices/mchp48l640.c index 40cd5041174c..f576e6a890e8 100644 --- a/drivers/mtd/devices/mchp48l640.c +++ b/drivers/mtd/devices/mchp48l640.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include struct mchp48_caps { unsigned int size; diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c index 1d3b2a94581f..0c1b93303618 100644 --- a/drivers/mtd/devices/mtd_dataflash.c +++ b/drivers/mtd/devices/mtd_dataflash.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/mtd/maps/physmap-bt1-rom.c b/drivers/mtd/maps/physmap-bt1-rom.c index 58782cfaf71c..60dccc48f99e 100644 --- a/drivers/mtd/maps/physmap-bt1-rom.c +++ b/drivers/mtd/maps/physmap-bt1-rom.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mtd/maps/physmap-gemini.c b/drivers/mtd/maps/physmap-gemini.c index d4a46e159d38..9d3b4bf84a1a 100644 --- a/drivers/mtd/maps/physmap-gemini.c +++ b/drivers/mtd/maps/physmap-gemini.c @@ -8,10 +8,10 @@ */ #include #include -#include #include #include #include +#include #include #include #include diff --git a/drivers/mtd/maps/physmap-ixp4xx.c b/drivers/mtd/maps/physmap-ixp4xx.c index 6a054229a8a0..c561468f95f6 100644 --- a/drivers/mtd/maps/physmap-ixp4xx.c +++ b/drivers/mtd/maps/physmap-ixp4xx.c @@ -11,7 +11,7 @@ */ #include #include -#include +#include #include #include #include "physmap-ixp4xx.h" diff --git a/drivers/mtd/maps/physmap-ixp4xx.h b/drivers/mtd/maps/physmap-ixp4xx.h index b0fc49b7f3ed..46824c57e58a 100644 --- a/drivers/mtd/maps/physmap-ixp4xx.h +++ b/drivers/mtd/maps/physmap-ixp4xx.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include +#include #include #ifdef CONFIG_MTD_PHYSMAP_IXP4XX diff --git a/drivers/mtd/maps/physmap-versatile.c b/drivers/mtd/maps/physmap-versatile.c index a1b8b7b25f88..8e15d514c82d 100644 --- a/drivers/mtd/maps/physmap-versatile.c +++ b/drivers/mtd/maps/physmap-versatile.c @@ -9,9 +9,9 @@ #include #include #include -#include #include #include +#include #include #include #include "physmap-versatile.h" diff --git a/drivers/mtd/maps/sun_uflash.c b/drivers/mtd/maps/sun_uflash.c index 860b19f77090..2bfdf1b7e18a 100644 --- a/drivers/mtd/maps/sun_uflash.c +++ b/drivers/mtd/maps/sun_uflash.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/ecc-mxic.c b/drivers/mtd/nand/ecc-mxic.c index 22a760e6024e..47e10945b8d2 100644 --- a/drivers/mtd/nand/ecc-mxic.c +++ b/drivers/mtd/nand/ecc-mxic.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/ecc.c b/drivers/mtd/nand/ecc.c index 5250764cedee..8f996e8d61b8 100644 --- a/drivers/mtd/nand/ecc.c +++ b/drivers/mtd/nand/ecc.c @@ -95,9 +95,9 @@ #include #include +#include #include #include -#include #include static LIST_HEAD(on_host_hw_engines); diff --git a/drivers/mtd/nand/onenand/onenand_omap2.c b/drivers/mtd/nand/onenand/onenand_omap2.c index ff7af98604df..7db53b59605d 100644 --- a/drivers/mtd/nand/onenand/onenand_omap2.c +++ b/drivers/mtd/nand/onenand/onenand_omap2.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/ams-delta.c b/drivers/mtd/nand/raw/ams-delta.c index fa621ffa6490..919816a7aca7 100644 --- a/drivers/mtd/nand/raw/ams-delta.c +++ b/drivers/mtd/nand/raw/ams-delta.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 415d6aaa8255..e75d81cf8c21 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 915047e3fbc2..edac8749bb93 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index fa537fee6701..20bb1e0cb5eb 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c index 086426139173..5bf73efe42e7 100644 --- a/drivers/mtd/nand/raw/fsl_upm.c +++ b/drivers/mtd/nand/raw/fsl_upm.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c index 500e7a28d2e4..e71ad2fcec23 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include "gpmi-nand.h" diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c b/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c index 9054559e52dd..525c34c281b6 100644 --- a/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c +++ b/drivers/mtd/nand/raw/ingenic/ingenic_ecc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c index b9f135297aa0..6748226b8bd1 100644 --- a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c +++ b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c index 30c15e4e1cc0..7d0204ea305b 100644 --- a/drivers/mtd/nand/raw/marvell_nand.c +++ b/drivers/mtd/nand/raw/marvell_nand.c @@ -77,9 +77,10 @@ #include #include #include -#include +#include #include #include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index d3faf8086631..ef821b43b3d4 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #define NFC_REG_CMD 0x00 diff --git a/drivers/mtd/nand/raw/mpc5121_nfc.c b/drivers/mtd/nand/raw/mpc5121_nfc.c index ab05ee65702c..6e8e790f84e7 100644 --- a/drivers/mtd/nand/raw/mpc5121_nfc.c +++ b/drivers/mtd/nand/raw/mpc5121_nfc.c @@ -21,10 +21,10 @@ #include #include #include +#include #include -#include #include -#include +#include #include diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c index b2fa6b2074ab..b6eb8cb6b5e9 100644 --- a/drivers/mtd/nand/raw/mtk_nand.c +++ b/drivers/mtd/nand/raw/mtk_nand.c @@ -16,7 +16,6 @@ #include #include #include -#include #include /* NAND controller register definition */ diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 3d4b2e8294ea..0cd98d5714fc 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -20,7 +20,6 @@ #include #include #include -#include #define DRIVER_NAME "mxc_nand" diff --git a/drivers/mtd/nand/raw/ndfc.c b/drivers/mtd/nand/raw/ndfc.c index 57f3db32122d..3bb32a7c6d67 100644 --- a/drivers/mtd/nand/raw/ndfc.c +++ b/drivers/mtd/nand/raw/ndfc.c @@ -22,8 +22,9 @@ #include #include #include +#include #include -#include +#include #include #define NDFC_MAX_CS 4 diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c index db22b3af16d8..e057c03a197d 100644 --- a/drivers/mtd/nand/raw/omap2.c +++ b/drivers/mtd/nand/raw/omap2.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c index 28b7bd7e22eb..8da5fee321b5 100644 --- a/drivers/mtd/nand/raw/pl35x-nand-controller.c +++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c @@ -23,9 +23,7 @@ #include #include #include -#include -#include -#include +#include #include #include #include diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 72d6168d8a1b..df245353b12b 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -3,6 +3,7 @@ * Copyright (c) 2016, The Linux Foundation. All rights reserved. */ #include +#include #include #include #include @@ -12,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/mtd/nand/raw/rockchip-nand-controller.c b/drivers/mtd/nand/raw/rockchip-nand-controller.c index 2312e27362cb..0ec03ffb4846 100644 --- a/drivers/mtd/nand/raw/rockchip-nand-controller.c +++ b/drivers/mtd/nand/raw/rockchip-nand-controller.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c index ac80aaf5b4e3..3d3d5c9814ff 100644 --- a/drivers/mtd/nand/raw/s3c2410.c +++ b/drivers/mtd/nand/raw/s3c2410.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/drivers/mtd/nand/raw/sh_flctl.c index 63bf20c41719..08211e96ce64 100644 --- a/drivers/mtd/nand/raw/sh_flctl.c +++ b/drivers/mtd/nand/raw/sh_flctl.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mtd/nand/raw/socrates_nand.c b/drivers/mtd/nand/raw/socrates_nand.c index a8b720ffe9e8..76d50eb9f1db 100644 --- a/drivers/mtd/nand/raw/socrates_nand.c +++ b/drivers/mtd/nand/raw/socrates_nand.c @@ -8,8 +8,9 @@ #include #include #include +#include #include -#include +#include #include #define FPGA_NAND_CMD_MASK (0x7 << 28) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 9884304634f6..c6cd7713bee7 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/mtd/nand/raw/xway_nand.c b/drivers/mtd/nand/raw/xway_nand.c index 6b1e2a2bba15..51d802a165ed 100644 --- a/drivers/mtd/nand/raw/xway_nand.c +++ b/drivers/mtd/nand/raw/xway_nand.c @@ -7,7 +7,8 @@ #include #include -#include +#include +#include #include diff --git a/drivers/mtd/spi-nor/controllers/nxp-spifi.c b/drivers/mtd/spi-nor/controllers/nxp-spifi.c index 794c7b7d5c92..337e83bf3362 100644 --- a/drivers/mtd/spi-nor/controllers/nxp-spifi.c +++ b/drivers/mtd/spi-nor/controllers/nxp-spifi.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include From d2236f6219fac62ee22d971e06a04148f4eb8cca Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 19 Jul 2023 11:33:54 +0100 Subject: [PATCH 061/105] mtdblock: make warning messages ratelimited When exercising various dev interfaces with stress-ng the mtdblock drivers can be (ab)used to generate a lot of warning messages. Make these rate limited to reduce the kernel log from being spammed with the same messages. Signed-off-by: Colin Ian King Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230719103354.2829366-1-colin.i.king@gmail.com --- drivers/mtd/mtdblock.c | 2 +- drivers/mtd/mtdblock_ro.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c index fa476fb4dffb..9751416c2a91 100644 --- a/drivers/mtd/mtdblock.c +++ b/drivers/mtd/mtdblock.c @@ -262,7 +262,7 @@ static int mtdblock_open(struct mtd_blktrans_dev *mbd) } if (mtd_type_is_nand(mbd->mtd)) - pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", + pr_warn_ratelimited("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", mbd->tr->name, mbd->mtd->name); /* OK, it's not open. Create cache info for it */ diff --git a/drivers/mtd/mtdblock_ro.c b/drivers/mtd/mtdblock_ro.c index 66ffc9f1ead2..ef6299af60e4 100644 --- a/drivers/mtd/mtdblock_ro.c +++ b/drivers/mtd/mtdblock_ro.c @@ -49,7 +49,7 @@ static void mtdblock_add_mtd(struct mtd_blktrans_ops *tr, struct mtd_info *mtd) dev->readonly = 1; if (mtd_type_is_nand(mtd)) - pr_warn("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", + pr_warn_ratelimited("%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\n", tr->name, mtd->name); if (add_mtd_blktrans_dev(dev)) From a6de66607a19095a1bc74aaefff44c9a5ca11da0 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:05 +0200 Subject: [PATCH 062/105] mtd: rawnand: qcom: Use the BIT() macro Fix the following checkpatch warning: "CHECK: Prefer using the BIT macro" Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-2-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index b1e69d634d4a..023c8b36426b 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -123,8 +123,8 @@ /* NAND_ERASED_CW_DETECT_CFG bits */ #define ERASED_CW_ECC_MASK 1 #define AUTO_DETECT_RES 0 -#define MASK_ECC (1 << ERASED_CW_ECC_MASK) -#define RESET_ERASED_DET (1 << AUTO_DETECT_RES) +#define MASK_ECC BIT(ERASED_CW_ECC_MASK) +#define RESET_ERASED_DET BIT(AUTO_DETECT_RES) #define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES) #define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC) #define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC) From 428771b61afdea898abd8724777cc36912566017 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:06 +0200 Subject: [PATCH 063/105] mtd: rawnand: qcom: Use u8 instead of uint8_t Fix the following checkpatch warning: "CHECK: Prefer kernel type 'u8' over 'uint8_t'" Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-3-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 023c8b36426b..0136df01738e 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -212,7 +212,7 @@ nandc_set_reg(chip, reg, \ /* Returns the dma address for reg read buffer */ #define reg_buf_dma_addr(chip, vaddr) \ ((chip)->reg_read_dma + \ - ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf)) + ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf)) #define QPIC_PER_CW_CMD_ELEMENTS 32 #define QPIC_PER_CW_CMD_SGL 32 @@ -1884,7 +1884,7 @@ static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page) } /* implements ecc->read_page() */ -static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, +static int qcom_nandc_read_page(struct nand_chip *chip, u8 *buf, int oob_required, int page) { struct qcom_nand_host *host = to_qcom_nand_host(chip); @@ -1912,7 +1912,7 @@ static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, } /* implements ecc->read_page_raw() */ -static int qcom_nandc_read_page_raw(struct nand_chip *chip, uint8_t *buf, +static int qcom_nandc_read_page_raw(struct nand_chip *chip, u8 *buf, int oob_required, int page) { struct mtd_info *mtd = nand_to_mtd(chip); @@ -1958,7 +1958,7 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page) } /* implements ecc->write_page() */ -static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, +static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { struct qcom_nand_host *host = to_qcom_nand_host(chip); @@ -2035,7 +2035,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, /* implements ecc->write_page_raw() */ static int qcom_nandc_write_page_raw(struct nand_chip *chip, - const uint8_t *buf, int oob_required, + const u8 *buf, int oob_required, int page) { struct mtd_info *mtd = nand_to_mtd(chip); From 062d8acb1941d4555efbccf0e54214b2f85c02d3 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:07 +0200 Subject: [PATCH 064/105] mtd: rawnand: qcom: Fix alignment with open parenthesis Fix the following checkpatch warning: "CHECK: Alignment should match open parenthesis" Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-4-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 0136df01738e..54a7b49bda87 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2348,7 +2348,7 @@ static int qcom_nand_ooblayout_ecc(struct mtd_info *mtd, int section, } static int qcom_nand_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) + struct mtd_oob_region *oobregion) { struct nand_chip *chip = mtd_to_nand(mtd); struct qcom_nand_host *host = to_qcom_nand_host(chip); @@ -2593,7 +2593,7 @@ static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 cmd, /* NAND framework ->exec_op() hooks and related helpers */ static void qcom_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, - struct qcom_op *q_op) + struct qcom_op *q_op) { struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); const struct nand_op_instr *instr = NULL; @@ -3089,19 +3089,17 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) */ nandc->buf_size = 532; - nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, - GFP_KERNEL); + nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL); if (!nandc->data_buffer) return -ENOMEM; - nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), - GFP_KERNEL); + nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL); if (!nandc->regs) return -ENOMEM; - nandc->reg_read_buf = devm_kcalloc(nandc->dev, - MAX_REG_RD, sizeof(*nandc->reg_read_buf), - GFP_KERNEL); + nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD, + sizeof(*nandc->reg_read_buf), + GFP_KERNEL); if (!nandc->reg_read_buf) return -ENOMEM; From 3b645b384bb3d1f30c3ac4b8fd5fcdf9d5493f93 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:08 +0200 Subject: [PATCH 065/105] mtd: rawnand: qcom: Fix the spacing Fix following checkpatch warning: "CHECK: Please don't use multiple blank lines" "CHECK: Please use a blank line after function/struct/union/enum declarations" Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-5-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 54a7b49bda87..554cca3801da 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1997,7 +1997,6 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf, oob_size = ecc->bytes; } - write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0); @@ -2373,6 +2372,7 @@ qcom_nandc_calc_ecc_bytes(int step_size, int strength) { return strength == 4 ? 12 : 16; } + NAND_ECC_CAPS_SINGLE(qcom_nandc_ecc_caps, qcom_nandc_calc_ecc_bytes, NANDC_STEP_SIZE, 4, 8); From fd29ba6707f9b81e8c79a25f25d76a1d39fd60c9 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:09 +0200 Subject: [PATCH 066/105] mtd: rawnand: qcom: Fix wrong indentation The main "for" loop in qcom_read_status_exec() does guard the following to if's which are badly indented. Fix the indentation. Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-6-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 554cca3801da..3adc40ef5cf6 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2722,12 +2722,12 @@ static int qcom_read_status_exec(struct nand_chip *chip, for (i = 0; i < num_cw; i++) { flash_status = le32_to_cpu(nandc->reg_read_buf[i]); - if (flash_status & FS_MPU_ERR) - host->status &= ~NAND_STATUS_WP; + if (flash_status & FS_MPU_ERR) + host->status &= ~NAND_STATUS_WP; - if (flash_status & FS_OP_ERR || - (i == (num_cw - 1) && (flash_status & FS_DEVICE_STS_ERR))) - host->status |= NAND_STATUS_FAIL; + if (flash_status & FS_OP_ERR || + (i == (num_cw - 1) && (flash_status & FS_DEVICE_STS_ERR))) + host->status |= NAND_STATUS_FAIL; } flash_status = host->status; From 548b7509d92d1349b01ed2293dcdde88f3d7a907 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:10 +0200 Subject: [PATCH 067/105] mtd: rawnand: qcom: Fix a typo Fix the following checkpatch warning: CHECK: 'tranasction' may be misspelled - perhaps 'transaction'? Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-7-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 3adc40ef5cf6..cb6ccaa19224 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -3144,7 +3144,7 @@ static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) /* * Initially allocate BAM transaction to read ONFI param page. * After detecting all the devices, this BAM transaction will - * be freed and the next BAM tranasction will be allocated with + * be freed and the next BAM transaction will be allocated with * maximum codeword size */ nandc->max_cwperpage = 1; From e260efea80e9cab8ad9dea1a03db11225df720f3 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:11 +0200 Subject: [PATCH 068/105] mtd: rawnand: qcom: Early structure initialization Instead of allocating a structure on the stack with random data and then expect the callee to perform the initialization (which is, in general, error prone), prefer zeroing the structure explicitly at allocation and provide the already zeroed area, so no explicit memset operation is needed. It is probably safer to do so, so we limit the timeframe when dirty data could actually be accessed by mistake. Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-8-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index cb6ccaa19224..4fc8dafa8f03 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2600,8 +2600,6 @@ static void qcom_parse_instructions(struct nand_chip *chip, unsigned int op_id; int i; - memset(q_op, 0, sizeof(*q_op)); - for (op_id = 0; op_id < subop->ninstrs; op_id++) { unsigned int offset, naddrs; const u8 *addrs; @@ -2681,7 +2679,7 @@ static int qcom_read_status_exec(struct nand_chip *chip, struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; - struct qcom_op q_op; + struct qcom_op q_op = {}; const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; @@ -2744,7 +2742,7 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo { struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct qcom_op q_op; + struct qcom_op q_op = {}; const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; @@ -2795,7 +2793,7 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub { struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct qcom_op q_op; + struct qcom_op q_op = {}; int ret = 0; qcom_parse_instructions(chip, subop, &q_op); @@ -2838,7 +2836,7 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ { struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct qcom_op q_op; + struct qcom_op q_op = {}; const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; @@ -2935,7 +2933,7 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su { struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct qcom_op q_op; + struct qcom_op q_op = {}; int ret = 0; qcom_parse_instructions(chip, subop, &q_op); From e2532429312d089cf0d13bcb411433d85aef98f0 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Sun, 16 Jul 2023 16:46:12 +0200 Subject: [PATCH 069/105] mtd: rawnand: qcom: Fix address parsing within ->exec_op() The naddrs variable is initialized but not used. Fixing this could have been a matter of dropping the variable, but the right way to do it looks a bit more complex: we can avoid useless writes to the q_op structure by using it. In practice we could even have possible out-of-bound bugs with the existing implementation. Let's fix all that by just performing the right number of assignments in the addr{1,2}_reg fields. Fixes: 89550beb098e ("mtd: rawnand: qcom: Implement exec_op()") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307131959.PdPSC86K-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202307131730.NOYbcjBr-lkp@intel.com/ Signed-off-by: Miquel Raynal Acked-by: Manivannan Sadhasivam Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/linux-mtd/20230716144612.32132-9-miquel.raynal@bootlin.com --- drivers/mtd/nand/raw/qcom_nandc.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 4fc8dafa8f03..dc8ca60fc2e2 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2616,12 +2616,13 @@ static void qcom_parse_instructions(struct nand_chip *chip, offset = nand_subop_get_addr_start_off(subop, op_id); naddrs = nand_subop_get_num_addr_cyc(subop, op_id); addrs = &instr->ctx.addr.addrs[offset]; - for (i = 0; i < MAX_ADDRESS_CYCLE; i++) { - if (i < 4) - q_op->addr1_reg |= (u32)addrs[i] << i * 8; - else - q_op->addr2_reg |= addrs[i]; - } + + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++) + q_op->addr1_reg |= addrs[i] << (i * 8); + + if (naddrs > 4) + q_op->addr2_reg |= addrs[4]; + q_op->rdy_delay_ns = instr->delay_ns; break; From 4622daf4b5c89cd6a689910c523b8185b8a20338 Mon Sep 17 00:00:00 2001 From: Arseniy Krasnov Date: Fri, 28 Jul 2023 12:38:10 +0300 Subject: [PATCH 070/105] mtd: rawnand: meson: fix build error Fixes the following build error: drivers/mtd/nand/raw/meson_nand.c:244:59: error: initializer element is not a compile-time constant static const struct nand_ecc_step_info axg_stepinfo[] = { axg_stepinfo_1024, axg_stepinfo_512 }; ^~~~~~~~~~~~~~~~~ Fixes: 0e1db39336d8 ("mtd: rawnand: meson: support for 512B ECC step size") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307281007.MMuVjmJ9-lkp@intel.com/ Signed-off-by: Arseniy Krasnov Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230728093810.2985324-1-AVKrasnov@sberdevices.ru --- drivers/mtd/nand/raw/meson_nand.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/meson_nand.c b/drivers/mtd/nand/raw/meson_nand.c index 9bdea97abe4c..04c3fdf713e7 100644 --- a/drivers/mtd/nand/raw/meson_nand.c +++ b/drivers/mtd/nand/raw/meson_nand.c @@ -229,20 +229,20 @@ NAND_ECC_CAPS_SINGLE(meson_gxl_ecc_caps, meson_nand_calc_ecc_bytes, 1024, 8, 24, 30, 40, 50, 60); static const int axg_stepinfo_strengths[] = { 8 }; -static const struct nand_ecc_step_info axg_stepinfo_1024 = { - .stepsize = 1024, - .strengths = axg_stepinfo_strengths, - .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) -}; -static const struct nand_ecc_step_info axg_stepinfo_512 = { - .stepsize = 512, - .strengths = axg_stepinfo_strengths, - .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) +static const struct nand_ecc_step_info axg_stepinfo[] = { + { + .stepsize = 1024, + .strengths = axg_stepinfo_strengths, + .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) + }, + { + .stepsize = 512, + .strengths = axg_stepinfo_strengths, + .nstrengths = ARRAY_SIZE(axg_stepinfo_strengths) + }, }; -static const struct nand_ecc_step_info axg_stepinfo[] = { axg_stepinfo_1024, axg_stepinfo_512 }; - static const struct nand_ecc_caps meson_axg_ecc_caps = { .stepinfos = axg_stepinfo, .nstepinfos = ARRAY_SIZE(axg_stepinfo), From e9714c22c1a8238a85d069b1517941fc723312f7 Mon Sep 17 00:00:00 2001 From: Alexander Usyskin Date: Mon, 31 Jul 2023 14:58:36 +0300 Subject: [PATCH 071/105] mtd: fix use-after-free in mtd release I case of partition device_unregister() in mtd_device_release() calls mtd_release() which frees mtd_info structure for partition. All code after device_unregister in mtd_device_release thus uses already freed memory. Move part of code to mtd_release() and restict mtd->dev cleanup to non-partion object. For partition object such cleanup have no sense as partition mtd_info is removed. Cc: Miquel Raynal Cc: Zhang Xiaoxu Fixes: 19bfa9ebebb5 ("mtd: use refcount to prevent corruption") Reviewed-by: Tomas Winkler Signed-off-by: Alexander Usyskin Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230731115836.542747-1-alexander.usyskin@intel.com --- drivers/mtd/mtdcore.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 2466ea466466..46f15f676491 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -93,6 +93,9 @@ static void mtd_release(struct device *dev) struct mtd_info *mtd = dev_get_drvdata(dev); dev_t index = MTD_DEVT(mtd->index); + idr_remove(&mtd_idr, mtd->index); + of_node_put(mtd_get_of_node(mtd)); + if (mtd_is_partition(mtd)) release_mtd_partition(mtd); @@ -103,6 +106,7 @@ static void mtd_release(struct device *dev) static void mtd_device_release(struct kref *kref) { struct mtd_info *mtd = container_of(kref, struct mtd_info, refcnt); + bool is_partition = mtd_is_partition(mtd); debugfs_remove_recursive(mtd->dbg.dfs_dir); @@ -111,11 +115,13 @@ static void mtd_device_release(struct kref *kref) device_unregister(&mtd->dev); - /* Clear dev so mtd can be safely re-registered later if desired */ - memset(&mtd->dev, 0, sizeof(mtd->dev)); - - idr_remove(&mtd_idr, mtd->index); - of_node_put(mtd_get_of_node(mtd)); + /* + * Clear dev so mtd can be safely re-registered later if desired. + * Should not be done for partition, + * as it was already destroyed in device_unregister(). + */ + if (!is_partition) + memset(&mtd->dev, 0, sizeof(mtd->dev)); module_put(THIS_MODULE); } From 264725e35fbc3b67e053a405e022393a6017e6da Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Mon, 31 Jul 2023 11:09:03 +0200 Subject: [PATCH 072/105] mtd: Clean refcounting with MTD_PARTITIONED_MASTER The logic is way too convoluted, let's clean the kref_get/put section to clarify what this block does when using CONFIG_MTD_PARTITIONED_MASTER: - Iterate through all the parent mtd devices - Grab a reference over them all but the master - Only grab the master whith CONFIG_MTD_PARTITIONED_MASTER Same logic must apply in the put path, otherwise it would be broken. Cc: Tomas Winkler Cc: Alexander Usyskin Cc: Zhang Xiaoxu Fixes: 19bfa9ebebb5 ("mtd: use refcount to prevent corruption") Signed-off-by: Miquel Raynal Tested-by: Alexander Usyskin Link: https://lore.kernel.org/linux-mtd/20230731090903.770277-1-miquel.raynal@bootlin.com --- drivers/mtd/mtdcore.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 46f15f676491..9bd661be3ae9 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1247,14 +1247,15 @@ int __get_mtd_device(struct mtd_info *mtd) return -ENODEV; } - kref_get(&mtd->refcnt); - - while (mtd->parent) { - if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER) || mtd->parent != master) - kref_get(&mtd->parent->refcnt); + while (mtd) { + if (mtd != master) + kref_get(&mtd->refcnt); mtd = mtd->parent; } + if (IS_ENABLED(CONFIG_MTD_PARTITIONED_MASTER)) + kref_get(&master->refcnt); + return 0; } EXPORT_SYMBOL_GPL(__get_mtd_device); @@ -1338,10 +1339,12 @@ void __put_mtd_device(struct mtd_info *mtd) { struct mtd_info *master = mtd_get_master(mtd); - while (mtd != master) { + while (mtd) { + /* kref_put() can relese mtd, so keep a reference mtd->parent */ struct mtd_info *parent = mtd->parent; - kref_put(&mtd->refcnt, mtd_device_release); + if (mtd != master) + kref_put(&mtd->refcnt, mtd_device_release); mtd = parent; } From 31cbe3a7e217ba8ec482ae821092e57d96275d5b Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Wed, 2 Aug 2023 09:35:00 +0800 Subject: [PATCH 073/105] mtd: rawnand: brcmnand: Use devm_platform_ioremap_resource_byname() Convert platform_get_resource_byname() + devm_ioremap_resource() to a single call to devm_platform_ioremap_resource_byname(), as this is exactly what this function does. Signed-off-by: Li Zetao Reviewed-by: Florian Fainelli Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230802013500.1030853-1-lizetao1@huawei.com --- drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c | 4 +--- drivers/mtd/nand/raw/brcmnand/iproc_nand.c | 7 ++----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c b/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c index 71ddcc611f6e..9596629000f4 100644 --- a/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/bcm63138_nand.c @@ -61,15 +61,13 @@ static int bcm63138_nand_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct bcm63138_nand_soc *priv; struct brcmnand_soc *soc; - struct resource *res; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; soc = &priv->soc; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-int-base"); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_ioremap_resource_byname(pdev, "nand-int-base"); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c index d32950847a62..089c70fc6edf 100644 --- a/drivers/mtd/nand/raw/brcmnand/iproc_nand.c +++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c @@ -103,7 +103,6 @@ static int iproc_nand_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct iproc_nand_soc *priv; struct brcmnand_soc *soc; - struct resource *res; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -112,13 +111,11 @@ static int iproc_nand_probe(struct platform_device *pdev) spin_lock_init(&priv->idm_lock); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-idm"); - priv->idm_base = devm_ioremap_resource(dev, res); + priv->idm_base = devm_platform_ioremap_resource_byname(pdev, "iproc-idm"); if (IS_ERR(priv->idm_base)) return PTR_ERR(priv->idm_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iproc-ext"); - priv->ext_base = devm_ioremap_resource(dev, res); + priv->ext_base = devm_platform_ioremap_resource_byname(pdev, "iproc-ext"); if (IS_ERR(priv->ext_base)) return PTR_ERR(priv->ext_base); From 3549fecd10d24bcf9840ba2f7d6a0b5f57feed6f Mon Sep 17 00:00:00 2001 From: Zhu Wang Date: Thu, 3 Aug 2023 16:50:56 +0800 Subject: [PATCH 074/105] mtd: rawnand: vf610_nfc: Do not check 0 for platform_get_irq() Since platform_get_irq() never returned zero, so it need not to check whether it returned zero, and we use the return error code of platform_get_irq() to replace the current return error code, for that platform_get_irq() may return -EINVAL or -ENXIO. Signed-off-by: Zhu Wang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230803085056.30888-1-wangzhu9@huawei.com --- drivers/mtd/nand/raw/vf610_nfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 86522048e271..dcdf33dbaef2 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -827,8 +827,8 @@ static int vf610_nfc_probe(struct platform_device *pdev) mtd->name = DRV_NAME; irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -EINVAL; + if (irq < 0) + return irq; nfc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(nfc->regs)) From f01d8155a92e33cdaa85d20bfbe6c441907b3c1f Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Fri, 18 Aug 2023 14:42:23 +0800 Subject: [PATCH 075/105] mtd: spi-nor: Check bus width while setting QE bit spi_nor_write_16bit_sr_and_check() should also check if bus width is 4 before setting QE bit. Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Suggested-by: Michael Walle Suggested-by: Tudor Ambarus Signed-off-by: Hsin-Yi Wang Reviewed-by: Michael Walle Link: https://lore.kernel.org/r/20230818064524.1229100-2-hsinyi@chromium.org Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 614960c7d22c..1b0c6770c14e 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -870,21 +870,22 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) ret = spi_nor_read_cr(nor, &sr_cr[1]); if (ret) return ret; - } else if (nor->params->quad_enable) { + } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 && + spi_nor_get_protocol_width(nor->write_proto) == 4 && + nor->params->quad_enable) { /* * If the Status Register 2 Read command (35h) is not * supported, we should at least be sure we don't * change the value of the SR2 Quad Enable bit. * - * We can safely assume that when the Quad Enable method is - * set, the value of the QE bit is one, as a consequence of the - * nor->params->quad_enable() call. + * When the Quad Enable method is set and the buswidth is 4, we + * can safely assume that the value of the QE bit is one, as a + * consequence of the nor->params->quad_enable() call. * - * We can safely assume that the Quad Enable bit is present in - * the Status Register 2 at BIT(1). According to the JESD216 - * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit - * Write Status (01h) command is available just for the cases - * in which the QE bit is described in SR2 at BIT(1). + * According to the JESD216 revB standard, BFPT DWORDS[15], + * bits 22:20, the 16-bit Write Status (01h) command is + * available just for the cases in which the QE bit is + * described in SR2 at BIT(1). */ sr_cr[1] = SR2_QUAD_EN_BIT1; } else { From 9d0164c6500e3b78b329c5eca7909eba61e972d3 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 8 Aug 2023 09:50:01 +0200 Subject: [PATCH 076/105] mtd: spi-nor: Add support for sst26vf032b flash Describe this new part. The datasheet is public. Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/SST26VF032B-SST26VF032BA-2.5V-3.0V-32-Mbit-Serial-Quad-IO-%28SQI%29-Flash-Memory-20005218K.pdf Here are the sfdp tables plus base testing to show it works. $ cat /sys/bus/spi/devices/spi0.0/spi-nor/partname sst26vf032b $ cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id bf2642 $ cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer sst $ xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450060102ff00060110300000ff81000106000100ffbf0001180002 0001fffffffffffffffffffffffffffffffffd20f1ffffffff0144eb086b 083b80bbfeffffffffff00ffffff440b0c200dd80fd810d820914824806f 1d81ed0f773830b030b0f7ffffff29c25cfff030c080ffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffff0004fff37f0000f57f0000f9ff 3d00f57f0000f37f0000ffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffbf2642ffb95ffdff30f260f332ff0a122346ff0f19320f1919ffffff ffffffff00669938ff05013506040232b03072428de89888a585c09faf5a ffff06ec060c0003080bffffffffff07ffff0202ff060300fdfd040600fc 0300fefe0202070e $ md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp e7efddddb3d5ee89ca37bf6b6e789645 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp $ dd if=/dev/urandom of=./qspi_test bs=1M count=1 1+0 records in 1+0 records out $ mtd_debug write /dev/mtd0 0 1048576 qspi_test Copied 1048576 bytes from qspi_test to address 0x00000000 in flash $ mtd_debug erase /dev/mtd0 0 1048576 Erased 1048576 bytes from address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 1048576 qspi_read Copied 1048576 bytes from address 0x00000000 in flash to qspi_read $ hexdump qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0100000 $ mtd_debug write /dev/mtd0 0 1048576 qspi_test Copied 1048576 bytes from qspi_test to address 0x00000000 in flash $ mtd_debug read /dev/mtd0 0 1048576 qspi_read Copied 1048576 bytes from address 0x00000000 in flash to qspi_read $ sha1sum qspi_test qspi_read 2f2f191c7a937eca5db21a1c39e79e7327587cc1 qspi_test 2f2f191c7a937eca5db21a1c39e79e7327587cc1 qspi_read Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20230808075001.223150-1-miquel.raynal@bootlin.com Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/sst.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 09fdc7023e09..197d2c1101ed 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -113,6 +113,10 @@ static const struct flash_info sst_nor_parts[] = { SPI_NOR_QUAD_READ) }, { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) }, + { "sst26vf032b", INFO(0xbf2642, 0, 0, 0) + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) + PARSE_SFDP + .fixups = &sst26vf_nor_fixups }, { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) From 69d50d0461a182872b7f7892702fa3a1ba95950d Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Fri, 18 Aug 2023 15:46:41 +0800 Subject: [PATCH 077/105] mtd: spi-nor: nxp-spifi: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enable (and possibly prepare) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clock explicitly, so drop the label "dis_clks" and "dis_clk_reg". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Link: https://lore.kernel.org/r/20230818074642.308166-12-lizetao1@huawei.com Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/controllers/nxp-spifi.c | 33 ++++----------------- 1 file changed, 6 insertions(+), 27 deletions(-) diff --git a/drivers/mtd/spi-nor/controllers/nxp-spifi.c b/drivers/mtd/spi-nor/controllers/nxp-spifi.c index 794c7b7d5c92..0c21b76adbcc 100644 --- a/drivers/mtd/spi-nor/controllers/nxp-spifi.c +++ b/drivers/mtd/spi-nor/controllers/nxp-spifi.c @@ -395,30 +395,18 @@ static int nxp_spifi_probe(struct platform_device *pdev) if (IS_ERR(spifi->flash_base)) return PTR_ERR(spifi->flash_base); - spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi"); + spifi->clk_spifi = devm_clk_get_enabled(&pdev->dev, "spifi"); if (IS_ERR(spifi->clk_spifi)) { - dev_err(&pdev->dev, "spifi clock not found\n"); + dev_err(&pdev->dev, "spifi clock not found or unable to enable\n"); return PTR_ERR(spifi->clk_spifi); } - spifi->clk_reg = devm_clk_get(&pdev->dev, "reg"); + spifi->clk_reg = devm_clk_get_enabled(&pdev->dev, "reg"); if (IS_ERR(spifi->clk_reg)) { - dev_err(&pdev->dev, "reg clock not found\n"); + dev_err(&pdev->dev, "reg clock not found or unable to enable\n"); return PTR_ERR(spifi->clk_reg); } - ret = clk_prepare_enable(spifi->clk_reg); - if (ret) { - dev_err(&pdev->dev, "unable to enable reg clock\n"); - return ret; - } - - ret = clk_prepare_enable(spifi->clk_spifi); - if (ret) { - dev_err(&pdev->dev, "unable to enable spifi clock\n"); - goto dis_clk_reg; - } - spifi->dev = &pdev->dev; platform_set_drvdata(pdev, spifi); @@ -431,24 +419,17 @@ static int nxp_spifi_probe(struct platform_device *pdev) flash_np = of_get_next_available_child(pdev->dev.of_node, NULL); if (!flash_np) { dev_err(&pdev->dev, "no SPI flash device to configure\n"); - ret = -ENODEV; - goto dis_clks; + return -ENODEV; } ret = nxp_spifi_setup_flash(spifi, flash_np); of_node_put(flash_np); if (ret) { dev_err(&pdev->dev, "unable to setup flash chip\n"); - goto dis_clks; + return ret; } return 0; - -dis_clks: - clk_disable_unprepare(spifi->clk_spifi); -dis_clk_reg: - clk_disable_unprepare(spifi->clk_reg); - return ret; } static int nxp_spifi_remove(struct platform_device *pdev) @@ -456,8 +437,6 @@ static int nxp_spifi_remove(struct platform_device *pdev) struct nxp_spifi *spifi = platform_get_drvdata(pdev); mtd_device_unregister(&spifi->nor.mtd); - clk_disable_unprepare(spifi->clk_spifi); - clk_disable_unprepare(spifi->clk_reg); return 0; } From 847178fe4ccdf7f70beddd91eb15481afee0a224 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:37 +0530 Subject: [PATCH 078/105] mtd: rawnand: qcom: Remove superfluous initialization of "ret" In all the cases, "ret" variable is assigned a value before returning it. So there is no need to explicitly initialize it with 0. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-2-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index dc8ca60fc2e2..4e0984b4341c 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1554,7 +1554,7 @@ check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf, struct mtd_info *mtd = nand_to_mtd(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; u8 *cw_data_buf, *cw_oob_buf; - int cw, data_size, oob_size, ret = 0; + int cw, data_size, oob_size, ret; if (!data_buf) data_buf = nand_get_data_buf(chip); @@ -2684,7 +2684,7 @@ static int qcom_read_status_exec(struct nand_chip *chip, const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; - int ret = 0, num_cw, i; + int ret, num_cw, i; u32 flash_status; host->status = NAND_STATUS_READY | NAND_STATUS_WP; @@ -2747,7 +2747,7 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; - int ret = 0; + int ret; qcom_parse_instructions(chip, subop, &q_op); @@ -2795,7 +2795,7 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_op q_op = {}; - int ret = 0; + int ret; qcom_parse_instructions(chip, subop, &q_op); @@ -2841,7 +2841,7 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ const struct nand_op_instr *instr = NULL; unsigned int op_id = 0; unsigned int len = 0; - int ret = 0; + int ret; qcom_parse_instructions(chip, subop, &q_op); @@ -2935,7 +2935,7 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct qcom_op q_op = {}; - int ret = 0; + int ret; qcom_parse_instructions(chip, subop, &q_op); From d68b7e5f49b81944656eeb70fae1b733f5ac26d8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:38 +0530 Subject: [PATCH 079/105] mtd: rawnand: qcom: Rename variables in qcom_op_cmd_mapping() qcom_op_cmd_mapping() function accepts opcode and returns the corresponding command register. So let's rename the local variables and parameters to reflect the same. Reported-by: Miquel Raynal Closes: https://lore.kernel.org/all/20230804190750.3367a044@xps-13/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-3-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 4e0984b4341c..515ce45a738b 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2555,39 +2555,39 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) return 0; } -static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 cmd, +static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 opcode, struct qcom_op *q_op) { - int ret; + int cmd; - switch (cmd) { + switch (opcode) { case NAND_CMD_RESET: - ret = OP_RESET_DEVICE; + cmd = OP_RESET_DEVICE; break; case NAND_CMD_READID: - ret = OP_FETCH_ID; + cmd = OP_FETCH_ID; break; case NAND_CMD_PARAM: if (nandc->props->qpic_v2) - ret = OP_PAGE_READ_ONFI_READ; + cmd = OP_PAGE_READ_ONFI_READ; else - ret = OP_PAGE_READ; + cmd = OP_PAGE_READ; break; case NAND_CMD_ERASE1: case NAND_CMD_ERASE2: - ret = OP_BLOCK_ERASE; + cmd = OP_BLOCK_ERASE; break; case NAND_CMD_STATUS: - ret = OP_CHECK_STATUS; + cmd = OP_CHECK_STATUS; break; case NAND_CMD_PAGEPROG: - ret = OP_PROGRAM_PAGE; + cmd = OP_PROGRAM_PAGE; q_op->flag = OP_PROGRAM_PAGE; nandc->exec_opwrite = true; break; } - return ret; + return cmd; } /* NAND framework ->exec_op() hooks and related helpers */ From dd3c8f4ab2035bdba41c840a7daaf1cc735f36bb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:39 +0530 Subject: [PATCH 080/105] mtd: rawnand: qcom: Handle unsupported opcode in qcom_op_cmd_mapping() Handle the scenario where the caller has passed an unsupported opcode to qcom_op_cmd_mapping(). In that case, log the error and return the -EOPNOTSUPP errono. Also, let's propagate this error code all the way up. This also fixes the following smatch warning: drivers/mtd/nand/raw/qcom_nandc.c:2941 qcom_op_cmd_mapping() error: uninitialized symbol 'ret'. Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202308032022.SnXkKyFs-lkp@intel.com/ Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-4-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 35 ++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 515ce45a738b..81084044c636 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2585,20 +2585,23 @@ static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 opcode, q_op->flag = OP_PROGRAM_PAGE; nandc->exec_opwrite = true; break; + default: + dev_err(nandc->dev, "Opcode not supported: %u\n", opcode); + return -EOPNOTSUPP; } return cmd; } /* NAND framework ->exec_op() hooks and related helpers */ -static void qcom_parse_instructions(struct nand_chip *chip, +static int qcom_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, struct qcom_op *q_op) { struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); const struct nand_op_instr *instr = NULL; unsigned int op_id; - int i; + int i, ret; for (op_id = 0; op_id < subop->ninstrs; op_id++) { unsigned int offset, naddrs; @@ -2608,7 +2611,11 @@ static void qcom_parse_instructions(struct nand_chip *chip, switch (instr->type) { case NAND_OP_CMD_INSTR: - q_op->cmd_reg = qcom_op_cmd_mapping(nandc, instr->ctx.cmd.opcode, q_op); + ret = qcom_op_cmd_mapping(nandc, instr->ctx.cmd.opcode, q_op); + if (ret < 0) + return ret; + + q_op->cmd_reg = ret; q_op->rdy_delay_ns = instr->delay_ns; break; @@ -2641,6 +2648,8 @@ static void qcom_parse_instructions(struct nand_chip *chip, break; } } + + return 0; } static void qcom_delay_ns(unsigned int ns) @@ -2689,7 +2698,9 @@ static int qcom_read_status_exec(struct nand_chip *chip, host->status = NAND_STATUS_READY | NAND_STATUS_WP; - qcom_parse_instructions(chip, subop, &q_op); + ret = qcom_parse_instructions(chip, subop, &q_op); + if (ret) + return ret; num_cw = nandc->exec_opwrite ? ecc->steps : 1; nandc->exec_opwrite = false; @@ -2749,7 +2760,9 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo unsigned int len = 0; int ret; - qcom_parse_instructions(chip, subop, &q_op); + ret = qcom_parse_instructions(chip, subop, &q_op); + if (ret) + return ret; nandc->buf_count = 0; nandc->buf_start = 0; @@ -2797,7 +2810,9 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub struct qcom_op q_op = {}; int ret; - qcom_parse_instructions(chip, subop, &q_op); + ret = qcom_parse_instructions(chip, subop, &q_op); + if (ret) + return ret; if (q_op.flag == OP_PROGRAM_PAGE) goto wait_rdy; @@ -2843,7 +2858,9 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ unsigned int len = 0; int ret; - qcom_parse_instructions(chip, subop, &q_op); + ret = qcom_parse_instructions(chip, subop, &q_op); + if (ret) + return ret; q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; @@ -2937,7 +2954,9 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su struct qcom_op q_op = {}; int ret; - qcom_parse_instructions(chip, subop, &q_op); + ret = qcom_parse_instructions(chip, subop, &q_op); + if (ret) + return ret; q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; From b4bb4800313de0d8faa5615d4943615ff56c1cc2 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:40 +0530 Subject: [PATCH 081/105] mtd: rawnand: qcom: Fix the opcode check in qcom_check_op() qcom_check_op() function checks for the invalid opcode for the instruction types. Currently, it just returns -ENOTSUPP for all opcodes of NAND_OP_CMD_INSTR type due to the use of "||" operator instead of "&&". Fix it! This also fixes the following smatch warning: drivers/mtd/nand/raw/qcom_nandc.c:3036 qcom_check_op() warn: was && intended here instead of ||? Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202308032022.SnXkKyFs-lkp@intel.com/ Fixes: 89550beb098e ("mtd: rawnand: qcom: Implement exec_op()") Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-5-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 81084044c636..2ade27e50c43 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -3033,12 +3033,12 @@ static int qcom_check_op(struct nand_chip *chip, switch (instr->type) { case NAND_OP_CMD_INSTR: - if (instr->ctx.cmd.opcode != NAND_CMD_RESET || - instr->ctx.cmd.opcode != NAND_CMD_READID || - instr->ctx.cmd.opcode != NAND_CMD_PARAM || - instr->ctx.cmd.opcode != NAND_CMD_ERASE1 || - instr->ctx.cmd.opcode != NAND_CMD_ERASE2 || - instr->ctx.cmd.opcode != NAND_CMD_STATUS || + if (instr->ctx.cmd.opcode != NAND_CMD_RESET && + instr->ctx.cmd.opcode != NAND_CMD_READID && + instr->ctx.cmd.opcode != NAND_CMD_PARAM && + instr->ctx.cmd.opcode != NAND_CMD_ERASE1 && + instr->ctx.cmd.opcode != NAND_CMD_ERASE2 && + instr->ctx.cmd.opcode != NAND_CMD_STATUS && instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG) return -ENOTSUPP; break; From ab15aabac028afd4889745239a1860a76598e79f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:41 +0530 Subject: [PATCH 082/105] mtd: rawnand: qcom: Use EOPNOTSUPP instead of ENOTSUPP Checkpatch complains over the usage of ENOTSUPP for new patches as below: WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP So let's fix the error code which is already present in qcom_check_op(). Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-6-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 2ade27e50c43..412dc9a2e751 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -3040,7 +3040,7 @@ static int qcom_check_op(struct nand_chip *chip, instr->ctx.cmd.opcode != NAND_CMD_ERASE2 && instr->ctx.cmd.opcode != NAND_CMD_STATUS && instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG) - return -ENOTSUPP; + return -EOPNOTSUPP; break; default: break; From cf82436dd831a87c87f3d625a527a9ee35ae6f4d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:42 +0530 Subject: [PATCH 083/105] mtd: rawnand: qcom: Wrap qcom_nand_exec_op() to 80 columns Both the function arguments and the definition could be wrapped to 80 columns to save line space. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-7-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 412dc9a2e751..19c03d0ddc86 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -3051,14 +3051,12 @@ static int qcom_check_op(struct nand_chip *chip, } static int qcom_nand_exec_op(struct nand_chip *chip, - const struct nand_operation *op, - bool check_only) + const struct nand_operation *op, bool check_only) { if (check_only) return qcom_check_op(chip, op); - return nand_op_parser_exec_op(chip, &qcom_op_parser, - op, check_only); + return nand_op_parser_exec_op(chip, &qcom_op_parser, op, check_only); } static const struct nand_controller_ops qcom_nandc_ops = { From bb7a103d4594bbec8fc74d10da2dd227e21cae35 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:43 +0530 Subject: [PATCH 084/105] mtd: rawnand: qcom: Unmap sg_list and free desc within submic_descs() There are two types of dma descriptors being used in this driver allocated by, prepare_bam_async_desc() and prep_adm_dma_desc() helper functions. These functions map and prepare the descriptors to be used for dma transfers. And all the descriptors are submitted inside the submit_descs() function. Once the transfer completion happens, those descriptors should be unmapped and freed as a part of cleanup. Currently, free_descs() function is doing the said cleanup of descriptors. But the callers of submit_descs() are required to call free_descs() in both the success and error cases. Since there are no other transactions need to be done after submit_descs(), let's just move the contents of free_descs() inside submit_descs() itself. This makes sure that the cleanup is handled within the submit_descs() thereby offloading the cleanup part from callers. While at it, let's also rename the return variable from "r" to "ret". Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-8-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 65 ++++++++++--------------------- 1 file changed, 20 insertions(+), 45 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 19c03d0ddc86..483233fe5df7 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1306,30 +1306,30 @@ static void config_nand_cw_write(struct nand_chip *chip) /* helpers to submit/free our list of dma descriptors */ static int submit_descs(struct qcom_nand_controller *nandc) { - struct desc_info *desc; + struct desc_info *desc, *n; dma_cookie_t cookie = 0; struct bam_transaction *bam_txn = nandc->bam_txn; - int r; + int ret = 0; if (nandc->props->is_bam) { if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) { - r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); - if (r) - return r; + ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); + if (ret) + goto err_unmap_free_desc; } if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) { - r = prepare_bam_async_desc(nandc, nandc->tx_chan, + ret = prepare_bam_async_desc(nandc, nandc->tx_chan, DMA_PREP_INTERRUPT); - if (r) - return r; + if (ret) + goto err_unmap_free_desc; } if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) { - r = prepare_bam_async_desc(nandc, nandc->cmd_chan, + ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, DMA_PREP_CMD); - if (r) - return r; + if (ret) + goto err_unmap_free_desc; } } @@ -1351,19 +1351,17 @@ static int submit_descs(struct qcom_nand_controller *nandc) if (!wait_for_completion_timeout(&bam_txn->txn_done, QPIC_NAND_COMPLETION_TIMEOUT)) - return -ETIMEDOUT; + ret = -ETIMEDOUT; } else { if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) - return -ETIMEDOUT; + ret = -ETIMEDOUT; } - return 0; -} - -static void free_descs(struct qcom_nand_controller *nandc) -{ - struct desc_info *desc, *n; - +err_unmap_free_desc: + /* + * Unmap the dma sg_list and free the desc allocated by both + * prepare_bam_async_desc() and prep_adm_dma_desc() functions. + */ list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { list_del(&desc->node); @@ -1376,6 +1374,8 @@ static void free_descs(struct qcom_nand_controller *nandc) kfree(desc); } + + return ret; } /* reset the register read buffer for next NAND operation */ @@ -1521,7 +1521,6 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); ret = submit_descs(nandc); - free_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to read raw cw %d\n", cw); return ret; @@ -1775,8 +1774,6 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf, } ret = submit_descs(nandc); - free_descs(nandc); - if (ret) { dev_err(nandc->dev, "failure to read page/oob\n"); return ret; @@ -1815,8 +1812,6 @@ static int copy_last_cw(struct qcom_nand_host *host, int page) if (ret) dev_err(nandc->dev, "failed to copy last codeword\n"); - free_descs(nandc); - return ret; } @@ -2024,8 +2019,6 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf, if (ret) dev_err(nandc->dev, "failure to write page\n"); - free_descs(nandc); - if (!ret) ret = nand_prog_page_end_op(chip); @@ -2100,8 +2093,6 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, if (ret) dev_err(nandc->dev, "failure to write raw page\n"); - free_descs(nandc); - if (!ret) ret = nand_prog_page_end_op(chip); @@ -2149,9 +2140,6 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) config_nand_cw_write(chip); ret = submit_descs(nandc); - - free_descs(nandc); - if (ret) { dev_err(nandc->dev, "failure to write oob\n"); return -EIO; @@ -2228,9 +2216,6 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs) config_nand_cw_write(chip); ret = submit_descs(nandc); - - free_descs(nandc); - if (ret) { dev_err(nandc->dev, "failure to update BBM\n"); return -EIO; @@ -2722,10 +2707,8 @@ static int qcom_read_status_exec(struct nand_chip *chip, ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting status descriptor\n"); - free_descs(nandc); goto err_out; } - free_descs(nandc); nandc_read_buffer_sync(nandc, true); @@ -2787,10 +2770,8 @@ static int qcom_read_id_type_exec(struct nand_chip *chip, const struct nand_subo ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting read id descriptor\n"); - free_descs(nandc); goto err_out; } - free_descs(nandc); instr = q_op.data_instr; op_id = q_op.data_instr_idx; @@ -2835,10 +2816,8 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting misc descriptor\n"); - free_descs(nandc); goto err_out; } - free_descs(nandc); wait_rdy: qcom_delay_ns(q_op.rdy_delay_ns); @@ -2932,10 +2911,8 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting param page descriptor\n"); - free_descs(nandc); goto err_out; } - free_descs(nandc); ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); if (ret) @@ -2981,10 +2958,8 @@ static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_su ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure in submitting erase descriptor\n"); - free_descs(nandc); goto err_out; } - free_descs(nandc); ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); if (ret) From c56de1e5b916154afcaa9f4df46f685cae75f173 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:44 +0530 Subject: [PATCH 085/105] mtd: rawnand: qcom: Simplify the call to nand_prog_page_end_op() Now that the dma desc cleanup is moved inside submit_descs(), let's simplify the call to nand_prog_page_end_op() inside qcom_nandc_write_page() and qcom_nandc_write_page_raw() to match other functions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-9-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 483233fe5df7..f3eeb926401a 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2016,13 +2016,12 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const u8 *buf, } ret = submit_descs(nandc); - if (ret) + if (ret) { dev_err(nandc->dev, "failure to write page\n"); + return ret; + } - if (!ret) - ret = nand_prog_page_end_op(chip); - - return ret; + return nand_prog_page_end_op(chip); } /* implements ecc->write_page_raw() */ @@ -2090,13 +2089,12 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, } ret = submit_descs(nandc); - if (ret) + if (ret) { dev_err(nandc->dev, "failure to write raw page\n"); + return ret; + } - if (!ret) - ret = nand_prog_page_end_op(chip); - - return ret; + return nand_prog_page_end_op(chip); } /* From dcd1e618b6cb59b87eedcbaae184dfa982689b01 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:45 +0530 Subject: [PATCH 086/105] mtd: rawnand: qcom: Do not override the error no of submit_descs() Just use the error no returned by submit_descs() instead of overriding it with -EIO. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230805174146.57006-10-manivannan.sadhasivam@linaro.org --- drivers/mtd/nand/raw/qcom_nandc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index f3eeb926401a..18e3d1ec6122 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2140,7 +2140,7 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page) ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to write oob\n"); - return -EIO; + return ret; } return nand_prog_page_end_op(chip); @@ -2216,7 +2216,7 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs) ret = submit_descs(nandc); if (ret) { dev_err(nandc->dev, "failure to update BBM\n"); - return -EIO; + return ret; } return nand_prog_page_end_op(chip); From 93ca966b4a2022c2f70ca08b6769e0276a630fa0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Sat, 5 Aug 2023 23:11:46 +0530 Subject: [PATCH 087/105] mtd: rawnand: qcom: Sort includes alphabetically Sort includes in alphabetical order. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Miquel Raynal --- drivers/mtd/nand/raw/qcom_nandc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 18e3d1ec6122..992e56572287 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2,19 +2,19 @@ /* * Copyright (c) 2016, The Linux Foundation. All rights reserved. */ -#include -#include #include -#include -#include +#include +#include #include +#include +#include +#include #include -#include #include +#include #include #include -#include -#include +#include /* NANDc reg offsets */ #define NAND_FLASH_CMD 0x00 From f504551b7f153c52e52154b989266c11a17590f3 Mon Sep 17 00:00:00 2001 From: Ruan Jinjie Date: Tue, 8 Aug 2023 11:29:43 +0800 Subject: [PATCH 088/105] mtd: rawnand: Propagate error and simplify ternary operators for brcmstb_nand_wait_for_completion() As bcmnand_ctrl_poll_status() return negative errno, so return true if sts < 0. The < 0 case does not exist for wait_for_completion_timeout(), so return true if sts = 0 and zero otherwise. Both of the true return of them can be considered as a -ETIMEDOUT err, so return -ETIMEDOUT if err is true to propagate err from its caller. Signed-off-by: Ruan Jinjie Reviewed-by: William Zhang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230808032943.3890545-1-ruanjinjie@huawei.com --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 03764b589ec5..440bef477930 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1666,13 +1666,13 @@ static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip) disable_ctrl_irqs(ctrl); sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); - err = (sts < 0) ? true : false; + err = sts < 0; } else { unsigned long timeo = msecs_to_jiffies( NAND_POLL_STATUS_TIMEOUT_MS); /* wait for completion interrupt */ sts = wait_for_completion_timeout(&ctrl->done, timeo); - err = (sts <= 0) ? true : false; + err = !sts; } return err; @@ -1688,6 +1688,7 @@ static int brcmnand_waitfunc(struct nand_chip *chip) if (ctrl->cmd_pending) err = brcmstb_nand_wait_for_completion(chip); + ctrl->cmd_pending = 0; if (err) { u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) >> brcmnand_cmd_shift(ctrl); @@ -1696,8 +1697,8 @@ static int brcmnand_waitfunc(struct nand_chip *chip) "timeout waiting for command %#02x\n", cmd); dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); + return -ETIMEDOUT; } - ctrl->cmd_pending = 0; return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & INTFC_FLASH_STATUS; } From a5a88125d00612586e941ae13e7fcf36ba8f18a7 Mon Sep 17 00:00:00 2001 From: Yi Yang Date: Thu, 17 Aug 2023 19:58:39 +0800 Subject: [PATCH 089/105] mtd: rawnand: fsmc: handle clk prepare error in fsmc_nand_resume() In fsmc_nand_resume(), the return value of clk_prepare_enable() should be checked since it might fail. Fixes: e25da1c07dfb ("mtd: fsmc_nand: Add clk_{un}prepare() support") Signed-off-by: Yi Yang Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230817115839.10192-1-yiyang13@huawei.com --- drivers/mtd/nand/raw/fsmc_nand.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index 7b4742420dfc..2e33ae77502a 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -1200,9 +1200,14 @@ static int fsmc_nand_suspend(struct device *dev) static int fsmc_nand_resume(struct device *dev) { struct fsmc_nand_data *host = dev_get_drvdata(dev); + int ret; if (host) { - clk_prepare_enable(host->clk); + ret = clk_prepare_enable(host->clk); + if (ret) { + dev_err(dev, "failed to enable clk\n"); + return ret; + } if (host->dev_timings) fsmc_nand_setup(host, host->dev_timings); nand_reset(&host->nand, 0); From b9e002a34420e5ba25d4283be870c48e0c9e005f Mon Sep 17 00:00:00 2001 From: Justin Stitt Date: Thu, 17 Aug 2023 17:52:21 +0000 Subject: [PATCH 090/105] mtd: rawnand: fix -Wvoid-pointer-to-enum-cast warning When building with clang 18 I see the following warning: | drivers/mtd/nand/raw/vf610_nfc.c:853:17: warning: cast to smaller integer | type 'enum vf610_nfc_variant' from 'const void *' [-Wvoid-pointer-to-enum-cast] | 853 | nfc->variant = (enum vf610_nfc_variant)of_id->data; This is due to the fact that `of_id->data` is a void* while `enum vf610_nfc_variant` has the size of an int. Cast `of_id->data` to a uintptr_t to silence the above warning for clang builds using W=1. Link: https://github.com/ClangBuiltLinux/linux/issues/1910 Reported-by: Nathan Chancellor Signed-off-by: Justin Stitt Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230817-void-drivers-mtd-nand-raw-vf610_nfc-v2-1-870a7c948c44@google.com --- drivers/mtd/nand/raw/vf610_nfc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index dcdf33dbaef2..039a44c054a4 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -850,7 +850,7 @@ static int vf610_nfc_probe(struct platform_device *pdev) goto err_disable_clk; } - nfc->variant = (enum vf610_nfc_variant)of_id->data; + nfc->variant = (uintptr_t)of_id->data; for_each_available_child_of_node(nfc->dev->of_node, child) { if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) { From a417ab334dccb603f6296cbf04c9f8059bc252eb Mon Sep 17 00:00:00 2001 From: Justin Stitt Date: Wed, 16 Aug 2023 18:26:44 +0000 Subject: [PATCH 091/105] mtd: maps: fix -Wvoid-pointer-to-enum-cast warning When building with clang 18 I see the following warning: | drivers/mtd/maps/physmap-versatile.c:209:25: warning: cast to smaller | integer type 'enum versatile_flashprot' from 'const void *' [-Wvoid-pointer-to-enum-cast] | 209 | versatile_flashprot = (enum versatile_flashprot)devid->data; This is due to the fact that `devid->data` is a void* while `enum versatile_flashprot` has the size of an int. Cast `devid->data` to a uintptr_t to silence the above warning for clang builds using W=1. Link: https://github.com/ClangBuiltLinux/linux/issues/1910 Reported-by: Nathan Chancellor Signed-off-by: Justin Stitt Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230816-void-drivers-mtd-maps-physmap-versatile-v2-1-433a25272bfa@google.com --- drivers/mtd/maps/physmap-versatile.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/maps/physmap-versatile.c b/drivers/mtd/maps/physmap-versatile.c index 8e15d514c82d..2e779111bf79 100644 --- a/drivers/mtd/maps/physmap-versatile.c +++ b/drivers/mtd/maps/physmap-versatile.c @@ -206,7 +206,7 @@ int of_flash_probe_versatile(struct platform_device *pdev, if (!sysnp) return -ENODEV; - versatile_flashprot = (enum versatile_flashprot)devid->data; + versatile_flashprot = (uintptr_t)devid->data; rmap = syscon_node_to_regmap(sysnp); of_node_put(sysnp); if (IS_ERR(rmap)) From 318207ffe487bde07e0ef229a9a51c896d66341e Mon Sep 17 00:00:00 2001 From: Md Sadre Alam Date: Fri, 18 Aug 2023 20:21:00 +0530 Subject: [PATCH 092/105] mtd: rawnand: qcom: Clear buf_count and buf_start in raw read Initialize buf_count and buf_start to 0 before starting the raw read. If we will not initialize then read staus will get updated with wrong value and we will see failure for even successful raw read transaction. Signed-off-by: Sricharan Ramabadhran Signed-off-by: Md Sadre Alam Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230818145101.23825-3-quic_mdalam@quicinc.com --- drivers/mtd/nand/raw/qcom_nandc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 992e56572287..985c4f4e6180 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1471,6 +1471,9 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, int raw_cw = cw; nand_read_page_op(chip, page, 0, NULL, 0); + nandc->buf_count = 0; + nandc->buf_start = 0; + clear_read_regs(nandc); host->use_ecc = false; if (nandc->props->qpic_v2) From a82990c8a409365bbc995dcb41218225cb4b809a Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 18 Aug 2023 20:21:01 +0530 Subject: [PATCH 093/105] mtd: rawnand: qcom: Add read/read_start ops in exec_op path READ/READ_START opcodes are not set in exec_op path. Fixing that here. While there, Steps to program the controller is common for erase/reset/read/program page. So use a common pattern and pull them under one function. Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230818145101.23825-4-quic_mdalam@quicinc.com --- drivers/mtd/nand/raw/qcom_nandc.c | 94 ++++++++++++------------------- 1 file changed, 35 insertions(+), 59 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 985c4f4e6180..0ee1caf021f7 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2541,9 +2541,11 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) return 0; } -static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 opcode, +static int qcom_op_cmd_mapping(struct nand_chip *chip, u8 opcode, struct qcom_op *q_op) { + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct qcom_nand_host *host = to_qcom_nand_host(chip); int cmd; switch (opcode) { @@ -2571,6 +2573,13 @@ static int qcom_op_cmd_mapping(struct qcom_nand_controller *nandc, u8 opcode, q_op->flag = OP_PROGRAM_PAGE; nandc->exec_opwrite = true; break; + case NAND_CMD_READ0: + case NAND_CMD_READSTART: + if (host->use_ecc) + cmd = OP_PAGE_READ_WITH_ECC; + else + cmd = OP_PAGE_READ; + break; default: dev_err(nandc->dev, "Opcode not supported: %u\n", opcode); return -EOPNOTSUPP; @@ -2584,7 +2593,6 @@ static int qcom_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, struct qcom_op *q_op) { - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); const struct nand_op_instr *instr = NULL; unsigned int op_id; int i, ret; @@ -2597,7 +2605,7 @@ static int qcom_parse_instructions(struct nand_chip *chip, switch (instr->type) { case NAND_OP_CMD_INSTR: - ret = qcom_op_cmd_mapping(nandc, instr->ctx.cmd.opcode, q_op); + ret = qcom_op_cmd_mapping(chip, instr->ctx.cmd.opcode, q_op); if (ret < 0) return ret; @@ -2791,13 +2799,25 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_op q_op = {}; int ret; + int instrs = 1; ret = qcom_parse_instructions(chip, subop, &q_op); if (ret) return ret; - if (q_op.flag == OP_PROGRAM_PAGE) + if (q_op.flag == OP_PROGRAM_PAGE) { goto wait_rdy; + } else if (q_op.cmd_reg == OP_BLOCK_ERASE) { + q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; + nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); + nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); + nandc_set_reg(chip, NAND_DEV0_CFG0, + host->cfg0_raw & ~(7 << CW_PER_PAGE)); + nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); + instrs = 3; + } else { + return 0; + } nandc->buf_count = 0; nandc->buf_start = 0; @@ -2809,9 +2829,12 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); nandc_set_reg(chip, NAND_EXEC_CMD, 1); - write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); + (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0, + 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc, + NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); ret = submit_descs(nandc); @@ -2925,56 +2948,7 @@ err_out: return ret; } -static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_subop *subop) -{ - struct qcom_nand_host *host = to_qcom_nand_host(chip); - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); - struct qcom_op q_op = {}; - int ret; - - ret = qcom_parse_instructions(chip, subop, &q_op); - if (ret) - return ret; - - q_op.cmd_reg |= PAGE_ACC | LAST_PAGE; - - nandc->buf_count = 0; - nandc->buf_start = 0; - host->use_ecc = false; - clear_read_regs(nandc); - clear_bam_transaction(nandc); - - nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); - nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); - nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); - nandc_set_reg(chip, NAND_DEV0_CFG0, - host->cfg0_raw & ~(7 << CW_PER_PAGE)); - nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); - nandc_set_reg(chip, NAND_EXEC_CMD, 1); - - write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); - write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); - - ret = submit_descs(nandc); - if (ret) { - dev_err(nandc->dev, "failure in submitting erase descriptor\n"); - goto err_out; - } - - ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); - if (ret) - goto err_out; - -err_out: - return ret; -} - static const struct nand_op_parser qcom_op_parser = NAND_OP_PARSER( - NAND_OP_PARSER_PATTERN( - qcom_misc_cmd_type_exec, - NAND_OP_PARSER_PAT_CMD_ELEM(false), - NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), NAND_OP_PARSER_PATTERN( qcom_read_id_type_exec, NAND_OP_PARSER_PAT_CMD_ELEM(false), @@ -2991,10 +2965,10 @@ static const struct nand_op_parser qcom_op_parser = NAND_OP_PARSER( NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 512)), NAND_OP_PARSER_PATTERN( - qcom_erase_cmd_type_exec, - NAND_OP_PARSER_PAT_CMD_ELEM(false), - NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), + qcom_misc_cmd_type_exec, NAND_OP_PARSER_PAT_CMD_ELEM(false), + NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYCLE), + NAND_OP_PARSER_PAT_CMD_ELEM(true), NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), ); @@ -3015,7 +2989,9 @@ static int qcom_check_op(struct nand_chip *chip, instr->ctx.cmd.opcode != NAND_CMD_ERASE1 && instr->ctx.cmd.opcode != NAND_CMD_ERASE2 && instr->ctx.cmd.opcode != NAND_CMD_STATUS && - instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG) + instr->ctx.cmd.opcode != NAND_CMD_PAGEPROG && + instr->ctx.cmd.opcode != NAND_CMD_READ0 && + instr->ctx.cmd.opcode != NAND_CMD_READSTART) return -EOPNOTSUPP; break; default: From a36201ac7c1b800043164824f21aa45abe629500 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:27 +0800 Subject: [PATCH 094/105] mtd: rawnand: arasan: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "disable_bus_clk" and "disable_controller_clk". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-3-lizetao1@huawei.com --- drivers/mtd/nand/raw/arasan-nand-controller.c | 29 ++++--------------- 1 file changed, 5 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 906eef70cb6d..4621ec549cc7 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -1440,45 +1440,29 @@ static int anfc_probe(struct platform_device *pdev) anfc_reset(nfc); - nfc->controller_clk = devm_clk_get(&pdev->dev, "controller"); + nfc->controller_clk = devm_clk_get_enabled(&pdev->dev, "controller"); if (IS_ERR(nfc->controller_clk)) return PTR_ERR(nfc->controller_clk); - nfc->bus_clk = devm_clk_get(&pdev->dev, "bus"); + nfc->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus"); if (IS_ERR(nfc->bus_clk)) return PTR_ERR(nfc->bus_clk); - ret = clk_prepare_enable(nfc->controller_clk); + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); if (ret) return ret; - ret = clk_prepare_enable(nfc->bus_clk); - if (ret) - goto disable_controller_clk; - - ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); - if (ret) - goto disable_bus_clk; - ret = anfc_parse_cs(nfc); if (ret) - goto disable_bus_clk; + return ret; ret = anfc_chips_init(nfc); if (ret) - goto disable_bus_clk; + return ret; platform_set_drvdata(pdev, nfc); return 0; - -disable_bus_clk: - clk_disable_unprepare(nfc->bus_clk); - -disable_controller_clk: - clk_disable_unprepare(nfc->controller_clk); - - return ret; } static void anfc_remove(struct platform_device *pdev) @@ -1486,9 +1470,6 @@ static void anfc_remove(struct platform_device *pdev) struct arasan_nfc *nfc = platform_get_drvdata(pdev); anfc_chips_cleanup(nfc); - - clk_disable_unprepare(nfc->bus_clk); - clk_disable_unprepare(nfc->controller_clk); } static const struct of_device_id anfc_ids[] = { From ee0152d0b4e624205c24845d3ca57015a941b361 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:28 +0800 Subject: [PATCH 095/105] mtd: rawnand: fsmc: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. The label "disable_clk" no longer makes sense, rename it to "disable_fsmc". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-4-lizetao1@huawei.com --- drivers/mtd/nand/raw/fsmc_nand.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index 2e33ae77502a..811982da3557 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -1066,16 +1066,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) host->regs_va = base + FSMC_NOR_REG_SIZE + (host->bank * FSMC_NAND_BANK_SZ); - host->clk = devm_clk_get(&pdev->dev, NULL); + host->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(host->clk)) { dev_err(&pdev->dev, "failed to fetch block clock\n"); return PTR_ERR(host->clk); } - ret = clk_prepare_enable(host->clk); - if (ret) - return ret; - /* * This device ID is actually a common AMBA ID as used on the * AMBA PrimeCell bus. However it is not a PrimeCell. @@ -1111,7 +1107,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) if (!host->read_dma_chan) { dev_err(&pdev->dev, "Unable to get read dma channel\n"); ret = -ENODEV; - goto disable_clk; + goto disable_fsmc; } host->write_dma_chan = dma_request_channel(mask, filter, NULL); if (!host->write_dma_chan) { @@ -1155,9 +1151,8 @@ release_dma_write_chan: release_dma_read_chan: if (host->mode == USE_DMA_ACCESS) dma_release_channel(host->read_dma_chan); -disable_clk: +disable_fsmc: fsmc_nand_disable(host); - clk_disable_unprepare(host->clk); return ret; } @@ -1182,7 +1177,6 @@ static void fsmc_nand_remove(struct platform_device *pdev) dma_release_channel(host->write_dma_chan); dma_release_channel(host->read_dma_chan); } - clk_disable_unprepare(host->clk); } } From 03f2cde57d86b20dc0f3ddc10f394c00ab77ee02 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:29 +0800 Subject: [PATCH 096/105] mtd: rawnand: intel: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "err_disable_unprepare_clk". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-5-lizetao1@huawei.com --- drivers/mtd/nand/raw/intel-nand-controller.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/nand/raw/intel-nand-controller.c b/drivers/mtd/nand/raw/intel-nand-controller.c index a9909eb08124..cb5d88f42297 100644 --- a/drivers/mtd/nand/raw/intel-nand-controller.c +++ b/drivers/mtd/nand/raw/intel-nand-controller.c @@ -626,16 +626,10 @@ static int ebu_nand_probe(struct platform_device *pdev) goto err_of_node_put; } - ebu_host->clk = devm_clk_get(dev, NULL); + ebu_host->clk = devm_clk_get_enabled(dev, NULL); if (IS_ERR(ebu_host->clk)) { ret = dev_err_probe(dev, PTR_ERR(ebu_host->clk), - "failed to get clock\n"); - goto err_of_node_put; - } - - ret = clk_prepare_enable(ebu_host->clk); - if (ret) { - dev_err(dev, "failed to enable clock: %d\n", ret); + "failed to get and enable clock\n"); goto err_of_node_put; } @@ -643,7 +637,7 @@ static int ebu_nand_probe(struct platform_device *pdev) if (IS_ERR(ebu_host->dma_tx)) { ret = dev_err_probe(dev, PTR_ERR(ebu_host->dma_tx), "failed to request DMA tx chan!.\n"); - goto err_disable_unprepare_clk; + goto err_of_node_put; } ebu_host->dma_rx = dma_request_chan(dev, "rx"); @@ -698,8 +692,6 @@ err_clean_nand: nand_cleanup(&ebu_host->chip); err_cleanup_dma: ebu_dma_cleanup(ebu_host); -err_disable_unprepare_clk: - clk_disable_unprepare(ebu_host->clk); err_of_node_put: of_node_put(chip_np); @@ -716,7 +708,6 @@ static void ebu_nand_remove(struct platform_device *pdev) nand_cleanup(&ebu_host->chip); ebu_nand_disable(&ebu_host->chip); ebu_dma_cleanup(ebu_host); - clk_disable_unprepare(ebu_host->clk); } static const struct of_device_id ebu_nand_match[] = { From 7714579d041feef8675d9decf7d0764aaf2fab05 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:30 +0800 Subject: [PATCH 097/105] mtd: rawnand: lpc32xx_slc: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "unprepare_clk". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-6-lizetao1@huawei.com --- drivers/mtd/nand/raw/lpc32xx_slc.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c index 2201264d3c37..1c5fa855b9f2 100644 --- a/drivers/mtd/nand/raw/lpc32xx_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_slc.c @@ -871,15 +871,12 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) mtd->dev.parent = &pdev->dev; /* Get NAND clock */ - host->clk = devm_clk_get(&pdev->dev, NULL); + host->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(host->clk)) { dev_err(&pdev->dev, "Clock failure\n"); res = -ENOENT; goto enable_wp; } - res = clk_prepare_enable(host->clk); - if (res) - goto enable_wp; /* Set NAND IO addresses and command/ready functions */ chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base); @@ -907,13 +904,13 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) GFP_KERNEL); if (host->data_buf == NULL) { res = -ENOMEM; - goto unprepare_clk; + goto enable_wp; } res = lpc32xx_nand_dma_setup(host); if (res) { res = -EIO; - goto unprepare_clk; + goto enable_wp; } /* Find NAND device */ @@ -934,8 +931,6 @@ cleanup_nand: nand_cleanup(chip); release_dma: dma_release_channel(host->dma_chan); -unprepare_clk: - clk_disable_unprepare(host->clk); enable_wp: lpc32xx_wp_enable(host); @@ -962,7 +957,6 @@ static void lpc32xx_nand_remove(struct platform_device *pdev) tmp &= ~SLCCFG_CE_LOW; writel(tmp, SLC_CTRL(host->io_base)); - clk_disable_unprepare(host->clk); lpc32xx_wp_enable(host); } From 008b239fe2c5feee1004643d2886a3bce530edf2 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:31 +0800 Subject: [PATCH 098/105] mtd: rawnand: mpc5121: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly. Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-7-lizetao1@huawei.com --- drivers/mtd/nand/raw/mpc5121_nfc.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/raw/mpc5121_nfc.c b/drivers/mtd/nand/raw/mpc5121_nfc.c index ab05ee65702c..426d6c7d405f 100644 --- a/drivers/mtd/nand/raw/mpc5121_nfc.c +++ b/drivers/mtd/nand/raw/mpc5121_nfc.c @@ -595,8 +595,6 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd) struct nand_chip *chip = mtd_to_nand(mtd); struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip); - clk_disable_unprepare(prv->clk); - if (prv->csreg) iounmap(prv->csreg); } @@ -717,17 +715,12 @@ static int mpc5121_nfc_probe(struct platform_device *op) } /* Enable NFC clock */ - clk = devm_clk_get(dev, "ipg"); + clk = devm_clk_get_enabled(dev, "ipg"); if (IS_ERR(clk)) { - dev_err(dev, "Unable to acquire NFC clock!\n"); + dev_err(dev, "Unable to acquire and enable NFC clock!\n"); retval = PTR_ERR(clk); goto error; } - retval = clk_prepare_enable(clk); - if (retval) { - dev_err(dev, "Unable to enable NFC clock!\n"); - goto error; - } prv->clk = clk; /* Reset NAND Flash controller */ From 2b34e8bd2f582be6342a9baae31a519698392444 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:32 +0800 Subject: [PATCH 099/105] mtd: rawnand: mtk: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "clk_disable". And both mtk_nfc_enable_clk() and mtk_nfc_disable_clk() now have a single user, which is the resume or suspend callback, so drop this two helper function and just move related operations in the resume or suspend function. Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-8-lizetao1@huawei.com --- drivers/mtd/nand/raw/mtk_nand.c | 62 ++++++++++----------------------- 1 file changed, 19 insertions(+), 43 deletions(-) diff --git a/drivers/mtd/nand/raw/mtk_nand.c b/drivers/mtd/nand/raw/mtk_nand.c index b2fa6b2074ab..9a0e597c65d3 100644 --- a/drivers/mtd/nand/raw/mtk_nand.c +++ b/drivers/mtd/nand/raw/mtk_nand.c @@ -1119,32 +1119,6 @@ static irqreturn_t mtk_nfc_irq(int irq, void *id) return IRQ_HANDLED; } -static int mtk_nfc_enable_clk(struct device *dev, struct mtk_nfc_clk *clk) -{ - int ret; - - ret = clk_prepare_enable(clk->nfi_clk); - if (ret) { - dev_err(dev, "failed to enable nfi clk\n"); - return ret; - } - - ret = clk_prepare_enable(clk->pad_clk); - if (ret) { - dev_err(dev, "failed to enable pad clk\n"); - clk_disable_unprepare(clk->nfi_clk); - return ret; - } - - return 0; -} - -static void mtk_nfc_disable_clk(struct mtk_nfc_clk *clk) -{ - clk_disable_unprepare(clk->nfi_clk); - clk_disable_unprepare(clk->pad_clk); -} - static int mtk_nfc_ooblayout_free(struct mtd_info *mtd, int section, struct mtd_oob_region *oob_region) { @@ -1546,40 +1520,36 @@ static int mtk_nfc_probe(struct platform_device *pdev) goto release_ecc; } - nfc->clk.nfi_clk = devm_clk_get(dev, "nfi_clk"); + nfc->clk.nfi_clk = devm_clk_get_enabled(dev, "nfi_clk"); if (IS_ERR(nfc->clk.nfi_clk)) { dev_err(dev, "no clk\n"); ret = PTR_ERR(nfc->clk.nfi_clk); goto release_ecc; } - nfc->clk.pad_clk = devm_clk_get(dev, "pad_clk"); + nfc->clk.pad_clk = devm_clk_get_enabled(dev, "pad_clk"); if (IS_ERR(nfc->clk.pad_clk)) { dev_err(dev, "no pad clk\n"); ret = PTR_ERR(nfc->clk.pad_clk); goto release_ecc; } - ret = mtk_nfc_enable_clk(dev, &nfc->clk); - if (ret) - goto release_ecc; - irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = -EINVAL; - goto clk_disable; + goto release_ecc; } ret = devm_request_irq(dev, irq, mtk_nfc_irq, 0x0, "mtk-nand", nfc); if (ret) { dev_err(dev, "failed to request nfi irq\n"); - goto clk_disable; + goto release_ecc; } ret = dma_set_mask(dev, DMA_BIT_MASK(32)); if (ret) { dev_err(dev, "failed to set dma mask\n"); - goto clk_disable; + goto release_ecc; } platform_set_drvdata(pdev, nfc); @@ -1587,14 +1557,11 @@ static int mtk_nfc_probe(struct platform_device *pdev) ret = mtk_nfc_nand_chips_init(dev, nfc); if (ret) { dev_err(dev, "failed to init nand chips\n"); - goto clk_disable; + goto release_ecc; } return 0; -clk_disable: - mtk_nfc_disable_clk(&nfc->clk); - release_ecc: mtk_ecc_release(nfc->ecc); @@ -1619,7 +1586,6 @@ static void mtk_nfc_remove(struct platform_device *pdev) } mtk_ecc_release(nfc->ecc); - mtk_nfc_disable_clk(&nfc->clk); } #ifdef CONFIG_PM_SLEEP @@ -1627,7 +1593,8 @@ static int mtk_nfc_suspend(struct device *dev) { struct mtk_nfc *nfc = dev_get_drvdata(dev); - mtk_nfc_disable_clk(&nfc->clk); + clk_disable_unprepare(nfc->clk.nfi_clk); + clk_disable_unprepare(nfc->clk.pad_clk); return 0; } @@ -1642,9 +1609,18 @@ static int mtk_nfc_resume(struct device *dev) udelay(200); - ret = mtk_nfc_enable_clk(dev, &nfc->clk); - if (ret) + ret = clk_prepare_enable(nfc->clk.nfi_clk); + if (ret) { + dev_err(dev, "failed to enable nfi clk\n"); return ret; + } + + ret = clk_prepare_enable(nfc->clk.pad_clk); + if (ret) { + dev_err(dev, "failed to enable pad clk\n"); + clk_disable_unprepare(nfc->clk.nfi_clk); + return ret; + } /* reset NAND chip if VCC was powered off */ list_for_each_entry(chip, &nfc->chips, node) { From 7ec53e2beb98201baeb834cde52f0e6d60baf1a8 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:33 +0800 Subject: [PATCH 100/105] mtd: rawnand: stm32_fmc2: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "err_clk_disable". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-9-lizetao1@huawei.com --- drivers/mtd/nand/raw/stm32_fmc2_nand.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 2f9e43f64dd7..88811139aaf5 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -1951,21 +1951,17 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev) init_completion(&nfc->complete); - nfc->clk = devm_clk_get(nfc->cdev, NULL); - if (IS_ERR(nfc->clk)) + nfc->clk = devm_clk_get_enabled(nfc->cdev, NULL); + if (IS_ERR(nfc->clk)) { + dev_err(dev, "can not get and enable the clock\n"); return PTR_ERR(nfc->clk); - - ret = clk_prepare_enable(nfc->clk); - if (ret) { - dev_err(dev, "can not enable the clock\n"); - return ret; } rstc = devm_reset_control_get(dev, NULL); if (IS_ERR(rstc)) { ret = PTR_ERR(rstc); if (ret == -EPROBE_DEFER) - goto err_clk_disable; + return ret; } else { reset_control_assert(rstc); reset_control_deassert(rstc); @@ -2018,9 +2014,6 @@ err_release_dma: sg_free_table(&nfc->dma_data_sg); sg_free_table(&nfc->dma_ecc_sg); -err_clk_disable: - clk_disable_unprepare(nfc->clk); - return ret; } @@ -2045,8 +2038,6 @@ static void stm32_fmc2_nfc_remove(struct platform_device *pdev) sg_free_table(&nfc->dma_data_sg); sg_free_table(&nfc->dma_ecc_sg); - clk_disable_unprepare(nfc->clk); - stm32_fmc2_nfc_wp_enable(nand); } From a95da2721268e237eab6b2eeb9c6d117943d642f Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:34 +0800 Subject: [PATCH 101/105] mtd: rawnand: sunxi: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "out_mod_clk_unprepare" and "out_ahb_clk_unprepare". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-10-lizetao1@huawei.com --- drivers/mtd/nand/raw/sunxi_nand.c | 29 ++++++----------------------- 1 file changed, 6 insertions(+), 23 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index db36bd755b8d..cff177f3320b 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -2095,37 +2095,26 @@ static int sunxi_nfc_probe(struct platform_device *pdev) if (irq < 0) return irq; - nfc->ahb_clk = devm_clk_get(dev, "ahb"); + nfc->ahb_clk = devm_clk_get_enabled(dev, "ahb"); if (IS_ERR(nfc->ahb_clk)) { dev_err(dev, "failed to retrieve ahb clk\n"); return PTR_ERR(nfc->ahb_clk); } - ret = clk_prepare_enable(nfc->ahb_clk); - if (ret) - return ret; - - nfc->mod_clk = devm_clk_get(dev, "mod"); + nfc->mod_clk = devm_clk_get_enabled(dev, "mod"); if (IS_ERR(nfc->mod_clk)) { dev_err(dev, "failed to retrieve mod clk\n"); - ret = PTR_ERR(nfc->mod_clk); - goto out_ahb_clk_unprepare; + return PTR_ERR(nfc->mod_clk); } - ret = clk_prepare_enable(nfc->mod_clk); - if (ret) - goto out_ahb_clk_unprepare; - nfc->reset = devm_reset_control_get_optional_exclusive(dev, "ahb"); - if (IS_ERR(nfc->reset)) { - ret = PTR_ERR(nfc->reset); - goto out_mod_clk_unprepare; - } + if (IS_ERR(nfc->reset)) + return PTR_ERR(nfc->reset); ret = reset_control_deassert(nfc->reset); if (ret) { dev_err(dev, "reset err %d\n", ret); - goto out_mod_clk_unprepare; + return ret; } nfc->caps = of_device_get_match_data(&pdev->dev); @@ -2164,10 +2153,6 @@ out_release_dmac: dma_release_channel(nfc->dmac); out_ahb_reset_reassert: reset_control_assert(nfc->reset); -out_mod_clk_unprepare: - clk_disable_unprepare(nfc->mod_clk); -out_ahb_clk_unprepare: - clk_disable_unprepare(nfc->ahb_clk); return ret; } @@ -2182,8 +2167,6 @@ static void sunxi_nfc_remove(struct platform_device *pdev) if (nfc->dmac) dma_release_channel(nfc->dmac); - clk_disable_unprepare(nfc->mod_clk); - clk_disable_unprepare(nfc->ahb_clk); } static const struct sunxi_nfc_caps sunxi_nfc_a10_caps = { From 4195b6420b43808ad2f984b345cb90a2842817c4 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:35 +0800 Subject: [PATCH 102/105] mtd: rawnand: vf610_nfc: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "err_disable_clk". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal --- drivers/mtd/nand/raw/vf610_nfc.c | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 039a44c054a4..3f783b8f76c9 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -834,21 +834,15 @@ static int vf610_nfc_probe(struct platform_device *pdev) if (IS_ERR(nfc->regs)) return PTR_ERR(nfc->regs); - nfc->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(nfc->clk)) + nfc->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(nfc->clk)) { + dev_err(nfc->dev, "Unable to get and enable clock!\n"); return PTR_ERR(nfc->clk); - - err = clk_prepare_enable(nfc->clk); - if (err) { - dev_err(nfc->dev, "Unable to enable clock!\n"); - return err; } of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev); - if (!of_id) { - err = -ENODEV; - goto err_disable_clk; - } + if (!of_id) + return -ENODEV; nfc->variant = (uintptr_t)of_id->data; @@ -858,9 +852,8 @@ static int vf610_nfc_probe(struct platform_device *pdev) if (nand_get_flash_node(chip)) { dev_err(nfc->dev, "Only one NAND chip supported!\n"); - err = -EINVAL; of_node_put(child); - goto err_disable_clk; + return -EINVAL; } nand_set_flash_node(chip, child); @@ -869,8 +862,7 @@ static int vf610_nfc_probe(struct platform_device *pdev) if (!nand_get_flash_node(chip)) { dev_err(nfc->dev, "NAND chip sub-node missing!\n"); - err = -ENODEV; - goto err_disable_clk; + return -ENODEV; } chip->options |= NAND_NO_SUBPAGE_WRITE; @@ -880,7 +872,7 @@ static int vf610_nfc_probe(struct platform_device *pdev) err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, nfc); if (err) { dev_err(nfc->dev, "Error requesting IRQ!\n"); - goto err_disable_clk; + return err; } vf610_nfc_preinit_controller(nfc); @@ -892,7 +884,7 @@ static int vf610_nfc_probe(struct platform_device *pdev) /* Scan the NAND chip */ err = nand_scan(chip, 1); if (err) - goto err_disable_clk; + return err; platform_set_drvdata(pdev, nfc); @@ -904,8 +896,6 @@ static int vf610_nfc_probe(struct platform_device *pdev) err_cleanup_nand: nand_cleanup(chip); -err_disable_clk: - clk_disable_unprepare(nfc->clk); return err; } @@ -918,7 +908,6 @@ static void vf610_nfc_remove(struct platform_device *pdev) ret = mtd_device_unregister(nand_to_mtd(chip)); WARN_ON(ret); nand_cleanup(chip); - clk_disable_unprepare(nfc->clk); } #ifdef CONFIG_PM_SLEEP From 2c11ea7bee3126f89d0e1b6fec0956b20017ce83 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:37 +0800 Subject: [PATCH 103/105] mtd: rawnand: orion: Use helper function devm_clk_get_optional_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get_optional() and clk_prepare_enable() can now be replaced by devm_clk_get_optional_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "no_dev". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-13-lizetao1@huawei.com --- drivers/mtd/nand/raw/orion_nand.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/drivers/mtd/nand/raw/orion_nand.c b/drivers/mtd/nand/raw/orion_nand.c index 7e0313889b50..2951d81614fd 100644 --- a/drivers/mtd/nand/raw/orion_nand.c +++ b/drivers/mtd/nand/raw/orion_nand.c @@ -169,16 +169,10 @@ static int __init orion_nand_probe(struct platform_device *pdev) platform_set_drvdata(pdev, info); /* Not all platforms can gate the clock, so it is optional. */ - info->clk = devm_clk_get_optional(&pdev->dev, NULL); + info->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); if (IS_ERR(info->clk)) return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), - "failed to get clock!\n"); - - ret = clk_prepare_enable(info->clk); - if (ret) { - dev_err(&pdev->dev, "failed to prepare clock!\n"); - return ret; - } + "failed to get and enable clock!\n"); /* * This driver assumes that the default ECC engine should be TYPE_SOFT. @@ -189,19 +183,13 @@ static int __init orion_nand_probe(struct platform_device *pdev) ret = nand_scan(nc, 1); if (ret) - goto no_dev; + return ret; mtd->name = "orion_nand"; ret = mtd_device_register(mtd, board->parts, board->nr_parts); - if (ret) { + if (ret) nand_cleanup(nc); - goto no_dev; - } - return 0; - -no_dev: - clk_disable_unprepare(info->clk); return ret; } @@ -215,8 +203,6 @@ static void orion_nand_remove(struct platform_device *pdev) WARN_ON(ret); nand_cleanup(chip); - - clk_disable_unprepare(info->clk); } #ifdef CONFIG_OF From 000412e4bb7e32b787fba1bf69a53bc4424476bf Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 21 Aug 2023 11:17:26 +0800 Subject: [PATCH 104/105] mtd: spear_smi: Use helper function devm_clk_get_enabled() Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be replaced by devm_clk_get_enabled() when driver enables (and possibly prepares) the clocks for the whole lifetime of the device. Moreover, it is no longer necessary to unprepare and disable the clocks explicitly, so drop the label "err_irq". Reviewed-by: Miquel Raynal Signed-off-by: Li Zetao Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230821031737.1973183-2-lizetao1@huawei.com --- drivers/mtd/devices/spear_smi.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/devices/spear_smi.c b/drivers/mtd/devices/spear_smi.c index 93bca5225116..0a35e5236ae5 100644 --- a/drivers/mtd/devices/spear_smi.c +++ b/drivers/mtd/devices/spear_smi.c @@ -993,21 +993,17 @@ static int spear_smi_probe(struct platform_device *pdev) dev->num_flashes = MAX_NUM_FLASH_CHIP; } - dev->clk = devm_clk_get(&pdev->dev, NULL); + dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { ret = PTR_ERR(dev->clk); goto err; } - ret = clk_prepare_enable(dev->clk); - if (ret) - goto err; - ret = devm_request_irq(&pdev->dev, irq, spear_smi_int_handler, 0, pdev->name, dev); if (ret) { dev_err(&dev->pdev->dev, "SMI IRQ allocation failed\n"); - goto err_irq; + goto err; } mutex_init(&dev->lock); @@ -1020,14 +1016,11 @@ static int spear_smi_probe(struct platform_device *pdev) ret = spear_smi_setup_banks(pdev, i, pdata->np[i]); if (ret) { dev_err(&dev->pdev->dev, "bank setup failed\n"); - goto err_irq; + goto err; } } return 0; - -err_irq: - clk_disable_unprepare(dev->clk); err: return ret; } @@ -1056,8 +1049,6 @@ static int spear_smi_remove(struct platform_device *pdev) WARN_ON(mtd_device_unregister(&flash->mtd)); } - clk_disable_unprepare(dev->clk); - return 0; } From b9283ac01a277e73111dbd06d1974ace30e40f16 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Aug 2023 11:38:52 +0200 Subject: [PATCH 105/105] dt-bindings: mtd: amlogic,meson-nand: drop unneeded quotes Drop unneeded quotes over simple string values to fix recently enabled yamllint warning: [error] string value is redundantly quoted with any quotes (quoted-strings) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230826093852.9334-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml index 1c79815e1f7f..57b6957c8415 100644 --- a/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/amlogic,meson-nand.yaml @@ -67,8 +67,8 @@ patternProperties: unevaluatedProperties: false dependencies: - nand-ecc-strength: ['nand-ecc-step-size'] - nand-ecc-step-size: ['nand-ecc-strength'] + nand-ecc-strength: [nand-ecc-step-size] + nand-ecc-step-size: [nand-ecc-strength] required: