drm/amd/display: Add z10 restore checks for DC interfaces
DMCUB has a deferred z10 restore process that needs signalling from driver to occur. This needs to be done on any interface that programs the hardware state or sequences where we expect to have the same hardware state as before. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1482,6 +1482,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
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return stream_mask;
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}
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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void dc_z10_restore(struct dc *dc)
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{
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if (dc->hwss.z10_restore)
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dc->hwss.z10_restore(dc);
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}
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#endif
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/*
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* Applies given context to HW and copy it into current context.
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* It's up to the user to release the src context afterwards.
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@ -1495,6 +1502,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
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struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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dc_z10_restore(dc);
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#endif
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dc_allow_idle_optimizations(dc, false);
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#endif
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@ -2569,6 +2579,10 @@ static void commit_planes_for_stream(struct dc *dc,
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int i, j;
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struct pipe_ctx *top_pipe_to_program = NULL;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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dc_z10_restore(dc);
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#endif
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if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
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/* Optimize seamless boot flag keeps clocks and watermarks high until
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* first flip. After first flip, optimization is required to lower
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@ -3024,6 +3038,9 @@ void dc_set_power_state(
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case DC_ACPI_CM_POWER_STATE_D0:
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dc_resource_state_construct(dc, dc->current_state);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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dc_z10_restore(dc);
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#endif
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if (dc->ctx->dmub_srv)
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dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
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@ -2706,6 +2706,10 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
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return false;
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link->psr_settings.psr_allow_active = allow_active;
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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if (!allow_active)
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dc_z10_restore(dc);
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#endif
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if (psr != NULL && link->psr_settings.psr_feature_enabled) {
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if (force_static && psr->funcs->psr_force_static)
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@ -294,6 +294,9 @@ bool dc_stream_set_cursor_attributes(
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stream->cursor_attributes = *attributes;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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dc_z10_restore(dc);
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#endif
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/* disable idle optimizations while updating cursor */
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if (dc->idle_optimizations_allowed) {
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dc_allow_idle_optimizations(dc, false);
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@ -355,6 +358,9 @@ bool dc_stream_set_cursor_position(
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dc = stream->ctx->dc;
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res_ctx = &dc->current_state->res_ctx;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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dc_z10_restore(dc);
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#endif
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/* disable idle optimizations if enabling cursor */
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if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
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@ -1326,6 +1326,9 @@ void dc_hardware_release(struct dc *dc);
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#endif
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bool dc_set_psr_allow_active(struct dc *dc, bool enable);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
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void dc_z10_restore(struct dc *dc);
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#endif
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bool dc_enable_dmub_notifications(struct dc *dc);
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