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iio: adc: ti-adc084s021: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 3691e5a694 ("iio: adc: add driver for the ti-adc084s021 chip")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Acked-by: Mårten Lindahl <marten.lindahl@axis.com>
Link: https://lore.kernel.org/r/20220508175712.647246-30-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:09 +01:00
parent 1e6bb81c23
commit bb102fd600
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/adc/ti-adc084s021.c
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@ -32,10 +32,10 @@ struct adc084s021 {
s64 ts __aligned(8); s64 ts __aligned(8);
} scan; } scan;
/* /*
* DMA (thus cache coherency maintenance) requires the * DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache line. * transfer buffers to live in their own cache line.
*/ */
u16 tx_buf[4] ____cacheline_aligned; u16 tx_buf[4] __aligned(IIO_DMA_MINALIGN);
__be16 rx_buf[5]; /* First 16-bits are trash */ __be16 rx_buf[5]; /* First 16-bits are trash */
}; };