iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i2c: cadence: Avoid fifo clear after start

Browse Source 
[ Upstream commit c2e55b449de7298a751ed0256251019d302af453 ]

The Driver unintentionally programs ctrl reg to clear the fifo, which
happens after the start of transaction. Previously, this was not an issue
as it involved read-modified-write. However, this issue breaks i2c reads
on QEMU, as i2c-read is executed before guest starts programming control
register.

Fixes: ff0cf7bca630 ("i2c: cadence: Remove unnecessary register reads")
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Sai Pavan Boddu 2024-05-03 15:12:08 +05:30 committed by Greg Kroah-Hartman
parent ec3468221e
commit bb220136ae
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/i2c/busses/i2c-cadence.c
View File

@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
if (hold_clear) {
ctrl_reg &= ~CDNS_I2C_CR_HOLD;
ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
/*
* In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size
* register reaches '0'. This is an IP bug which causes transfer size