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clk: mediatek: Add MT8188 vencsys clock support

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Add MT8188 vencsys clock controllers which provide clock gate
control for video encoder.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230331123621.16167-15-Garmin.Chang@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Garmin.Chang 2023-03-31 20:36:16 +08:00 committed by Stephen Boyd
parent cfa4609f9b
commit bb87c1109c
3 changed files with 62 additions and 0 deletions
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7
drivers/clk/mediatek/Kconfig
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@ -734,6 +734,13 @@ config COMMON_CLK_MT8188_VDOSYS
help
This driver supports MediaTek MT8188 vdosys0/1 (multimedia) clocks.
config COMMON_CLK_MT8188_VENCSYS
tristate "Clock driver for MediaTek MT8188 vencsys"
depends on COMMON_CLK_MT8188_VPPSYS
default COMMON_CLK_MT8188_VPPSYS
help
This driver supports MediaTek MT8188 vencsys clocks.
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST

1
drivers/clk/mediatek/Makefile
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@ -108,6 +108,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_IPESYS) += clk-mt8188-ipe.o
obj-$(CONFIG_COMMON_CLK_MT8188_MFGCFG) += clk-mt8188-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8188_VDECSYS) += clk-mt8188-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o

54
drivers/clk/mediatek/clk-mt8188-venc.c Normal file
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@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Garmin Chang <garmin.chang@mediatek.com>
*/
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-gate.h"
#include "clk-mtk.h"
static const struct mtk_gate_regs venc1_cg_regs = {
.set_ofs = 0x4,
.clr_ofs = 0x8,
.sta_ofs = 0x0,
};
#define GATE_VENC1(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &venc1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
static const struct mtk_gate venc1_clks[] = {
GATE_VENC1(CLK_VENC1_LARB, "venc1_larb", "top_venc", 0),
GATE_VENC1(CLK_VENC1_VENC, "venc1_venc", "top_venc", 4),
GATE_VENC1(CLK_VENC1_JPGENC, "venc1_jpgenc", "top_venc", 8),
GATE_VENC1(CLK_VENC1_JPGDEC, "venc1_jpgdec", "top_venc", 12),
GATE_VENC1(CLK_VENC1_JPGDEC_C1, "venc1_jpgdec_c1", "top_venc", 16),
GATE_VENC1(CLK_VENC1_GALS, "venc1_gals", "top_venc", 28),
GATE_VENC1(CLK_VENC1_GALS_SRAM, "venc1_gals_sram", "top_venc", 31),
};
static const struct mtk_clk_desc venc1_desc = {
.clks = venc1_clks,
.num_clks = ARRAY_SIZE(venc1_clks),
};
static const struct of_device_id of_match_clk_mt8188_venc1[] = {
{ .compatible = "mediatek,mt8188-vencsys", .data = &venc1_desc },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(platform, of_match_clk_mt8188_venc1);
static struct platform_driver clk_mt8188_venc1_drv = {
.probe = mtk_clk_simple_probe,
.remove = mtk_clk_simple_remove,
.driver = {
.name = "clk-mt8188-venc1",
.of_match_table = of_match_clk_mt8188_venc1,
},
};
module_platform_driver(clk_mt8188_venc1_drv);
MODULE_LICENSE("GPL");