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phy: exynos5-usbdrd: support isolating HS and SS ports independently

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Some versions of this IP have been integrated using separate PMU power
control registers for the HS and SS parts. One example is the Google
Tensor gs101 SoC.

Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their
exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value.

The existing 'usbdrdphy' alias can not be used in this case because
that is meant for determining the correct PMU offset if multiple
distinct PHYs exist in the system (as opposed to one PHY with multiple
isolators).

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-2-b66de9ae7424@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
André Draszik 2024-06-17 17:44:43 +01:00 committed by Vinod Koul
parent e340c041b7
commit bbb28a1d73
1 changed files with 13 additions and 10 deletions
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23
drivers/phy/samsung/phy-exynos5-usbdrd.c
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@ -186,6 +186,7 @@ struct exynos5_usbdrd_phy_drvdata {
const struct exynos5_usbdrd_phy_config *phy_cfg; const struct exynos5_usbdrd_phy_config *phy_cfg;
const struct phy_ops *phy_ops; const struct phy_ops *phy_ops;
u32 pmu_offset_usbdrd0_phy; u32 pmu_offset_usbdrd0_phy;
u32 pmu_offset_usbdrd0_phy_ss;
u32 pmu_offset_usbdrd1_phy; u32 pmu_offset_usbdrd1_phy;
bool has_common_clk_gate; bool has_common_clk_gate;
}; };
@ -1065,16 +1066,6 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
if (channel < 0) if (channel < 0)
dev_dbg(dev, "Not a multi-controller usbdrd phy\n"); dev_dbg(dev, "Not a multi-controller usbdrd phy\n");
switch (channel) {
case 1:
pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
break;
case 0:
default:
pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
break;
}
/* Get Vbus regulators */ /* Get Vbus regulators */
phy_drd->vbus = devm_regulator_get(dev, "vbus"); phy_drd->vbus = devm_regulator_get(dev, "vbus");
if (IS_ERR(phy_drd->vbus)) { if (IS_ERR(phy_drd->vbus)) {
@ -1109,6 +1100,18 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
phy_drd->phys[i].phy = phy; phy_drd->phys[i].phy = phy;
phy_drd->phys[i].index = i; phy_drd->phys[i].index = i;
phy_drd->phys[i].reg_pmu = reg_pmu; phy_drd->phys[i].reg_pmu = reg_pmu;
switch (channel) {
case 1:
pmu_offset = drv_data->pmu_offset_usbdrd1_phy;
break;
case 0:
default:
pmu_offset = drv_data->pmu_offset_usbdrd0_phy;
if (i == EXYNOS5_DRDPHY_PIPE3 && drv_data
->pmu_offset_usbdrd0_phy_ss)
pmu_offset = drv_data->pmu_offset_usbdrd0_phy_ss;
break;
}
phy_drd->phys[i].pmu_offset = pmu_offset; phy_drd->phys[i].pmu_offset = pmu_offset;
phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i]; phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
phy_set_drvdata(phy, &phy_drd->phys[i]); phy_set_drvdata(phy, &phy_drd->phys[i]);