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drm/amd/display: Fix possible overflow in integer multiplication

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[WHAT & HOW]
Integer multiplies integer may overflow in context that expects an
expression of unsigned/siged long long (64 bits). This can be fixed
by casting integer to unsigned/siged long long to force 64 bits results.

This fixes 26 OVERFLOW_BEFORE_WIDEN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Hung 2024-06-07 22:09:53 -06:00 committed by Alex Deucher
parent 95134e5852
commit bbd0d1c942
13 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
View File

@ -158,7 +158,7 @@ void amdgpu_dm_psr_enable(struct dc_stream_state *stream)
DRM_DEBUG_DRIVER("Enabling psr...\n");
vsync_rate_hz = div64_u64(div64_u64((
stream->timing.pix_clk_100hz * 100),
stream->timing.pix_clk_100hz * (uint64_t)100),
stream->timing.v_total),
stream->timing.h_total);

2
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
View File

@ -1853,7 +1853,7 @@ static void calculate_bandwidth(
/*compute total time to request one chunk from each active display pipe*/
for (i = 0; i <= maximum_number_of_surfaces - 1; i++) {
if (data->enable[i]) {
data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));
data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * (int64_t)data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2))))));
}
}
/*compute total time to request cursor data*/

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
View File

@ -576,7 +576,7 @@ static void dcn32_auto_dpm_test_log(
p_state_list[i] = curr_pipe_ctx->p_state_type;
refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
curr_pipe_ctx->stream->timing.v_total * curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
curr_pipe_ctx->stream->timing.v_total * (uint64_t)curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
disp_src_refresh_list[i] = refresh_rate;

8
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -888,21 +888,21 @@ static struct rect calculate_plane_rec_in_timing_active(
struct rect rec_out = {0};
struct fixed31_32 temp;
temp = dc_fixpt_from_fraction(rec_in->x * stream->dst.width,
temp = dc_fixpt_from_fraction(rec_in->x * (long long)stream->dst.width,
stream->src.width);
rec_out.x = stream->dst.x + dc_fixpt_round(temp);
temp = dc_fixpt_from_fraction(
(rec_in->x + rec_in->width) * stream->dst.width,
(rec_in->x + rec_in->width) * (long long)stream->dst.width,
stream->src.width);
rec_out.width = stream->dst.x + dc_fixpt_round(temp) - rec_out.x;
temp = dc_fixpt_from_fraction(rec_in->y * stream->dst.height,
temp = dc_fixpt_from_fraction(rec_in->y * (long long)stream->dst.height,
stream->src.height);
rec_out.y = stream->dst.y + dc_fixpt_round(temp);
temp = dc_fixpt_from_fraction(
(rec_in->y + rec_in->height) * stream->dst.height,
(rec_in->y + rec_in->height) * (long long)stream->dst.height,
stream->src.height);
rec_out.height = stream->dst.y + dc_fixpt_round(temp) - rec_out.y;

6
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View File

@ -975,7 +975,7 @@ static int dc_stream_calculate_flickerless_refresh_rate(struct dc_stream_state *
}
if (search_for_max_increase)
return (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*stream->timing.h_total);
return (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream->timing.h_total);
else
return stream->lumin_data.refresh_rate_hz[0];
}
@ -1024,7 +1024,7 @@ static unsigned int dc_stream_get_max_flickerless_instant_vtotal_delta(struct dc
if (stream->timing.v_total * stream->timing.h_total == 0)
return 0;
int current_refresh_hz = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*stream->timing.h_total);
int current_refresh_hz = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, stream->timing.v_total*(long long)stream->timing.h_total);
int safe_refresh_hz = dc_stream_calculate_flickerless_refresh_rate(stream,
dc_stream_get_brightness_millinits_from_refresh(stream, current_refresh_hz),
@ -1032,7 +1032,7 @@ static unsigned int dc_stream_get_max_flickerless_instant_vtotal_delta(struct dc
is_gaming,
increase);
int safe_refresh_v_total = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, safe_refresh_hz*stream->timing.h_total);
int safe_refresh_v_total = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, safe_refresh_hz*(long long)stream->timing.h_total);
if (increase)
return (((int) stream->timing.v_total - safe_refresh_v_total) >= 0) ? (stream->timing.v_total - safe_refresh_v_total) : 0;

2
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
View File

@ -353,7 +353,7 @@ static uint32_t calculate_required_audio_bw_in_symbols(
/* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */
struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100);
struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction(
crtc_info->requested_pixel_clock_100Hz, crtc_info->h_total * 10);
crtc_info->requested_pixel_clock_100Hz, (long long)crtc_info->h_total * 10);
struct fixed31_32 samples_per_line;
struct fixed31_32 layouts_per_line;
struct fixed31_32 symbols_per_sdp_max_layout;

8
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@ -217,7 +217,7 @@ static bool calc_fb_divider_checking_tolerance(
actual_calc_clk_100hz = (uint64_t)feedback_divider *
calc_pll_cs->fract_fb_divider_factor +
fract_feedback_divider;
actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10;
actual_calc_clk_100hz =
div_u64(actual_calc_clk_100hz,
ref_divider * post_divider *
@ -680,7 +680,7 @@ static bool calculate_ss(
* so have to divided by 100 * 100*/
ss_amount = dc_fixpt_mul(
fb_div, dc_fixpt_from_fraction(ss_data->percentage,
100 * ss_data->percentage_divider));
100 * (long long)ss_data->percentage_divider));
ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
ss_nslip_amount = dc_fixpt_sub(ss_amount,
@ -695,8 +695,8 @@ static bool calculate_ss(
/* compute SS_STEP_SIZE_DSFRAC */
modulation_time = dc_fixpt_from_fraction(
pll_settings->reference_freq * 1000,
pll_settings->reference_divider * ss_data->modulation_freq_hz);
pll_settings->reference_freq * (uint64_t)1000,
pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz);
if (ss_data->flags.CENTER_SPREAD)
modulation_time = dc_fixpt_div_int(modulation_time, 4);

2
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
View File

@ -218,7 +218,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
* contain integer component, lower 16 bits contain fractional component
* of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
*/
active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
active_duty_cycle = backlight_pwm_u16_16 * (uint64_t)masked_pwm_period;
/* 1.3 Calculate 16 bit active duty cycle from integer and fractional
* components shift by bitCount then mask 16 bits and add rounding bit

2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@ -997,7 +997,7 @@ static bool subvp_subvp_admissable(struct dc *dc,
if (pipe->plane_state && !pipe->top_pipe &&
dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_MAIN) {
refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
pipe->stream->timing.v_total * (uint64_t)pipe->stream->timing.h_total - (uint64_t)1);
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);

2
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@ -2208,7 +2208,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
grouped_pipes[i]->stream->signal)) {
embedded = i;
master = i;
phase[i] = embedded_pix_clk_100hz*100;
phase[i] = embedded_pix_clk_100hz*(uint64_t)100;
modulo[i] = dp_ref_clk_100hz*100;
} else {

2
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
View File

@ -763,7 +763,7 @@ bool edp_setup_psr(struct dc_link *link,
psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
timing.pix_clk_100hz * 100),
timing.pix_clk_100hz * (u64)100),
stream->timing.v_total),
stream->timing.h_total);

8
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
View File

@ -110,21 +110,21 @@ static struct spl_rect calculate_plane_rec_in_timing_active(
struct fixed31_32 temp;
temp = dc_fixpt_from_fraction(rec_in->x * stream_dst->width,
temp = dc_fixpt_from_fraction(rec_in->x * (long long)stream_dst->width,
stream_src->width);
rec_out.x = stream_dst->x + dc_fixpt_round(temp);
temp = dc_fixpt_from_fraction(
(rec_in->x + rec_in->width) * stream_dst->width,
(rec_in->x + rec_in->width) * (long long)stream_dst->width,
stream_src->width);
rec_out.width = stream_dst->x + dc_fixpt_round(temp) - rec_out.x;
temp = dc_fixpt_from_fraction(rec_in->y * stream_dst->height,
temp = dc_fixpt_from_fraction(rec_in->y * (long long)stream_dst->height,
stream_src->height);
rec_out.y = stream_dst->y + dc_fixpt_round(temp);
temp = dc_fixpt_from_fraction(
(rec_in->y + rec_in->height) * stream_dst->height,
(rec_in->y + rec_in->height) * (long long)stream_dst->height,
stream_src->height);
rec_out.height = stream_dst->y + dc_fixpt_round(temp) - rec_out.y;

2
drivers/gpu/drm/amd/display/modules/freesync/freesync.c
View File

@ -1002,7 +1002,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
(stream->timing.h_total * stream->ctx->dc->caps.max_v_total));
(stream->timing.h_total * (long long)stream->ctx->dc->caps.max_v_total));
}
/* Limit minimum refresh rate to what can be supported by hardware */
min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?