IIO: Add basic MXS LRADC driver
This driver is very basic. It supports userland trigger, buffer and raw access to channels. The support for delay channels is missing altogether. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Juergen Beisert <jbe@pengutronix.de> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Marek Vasut
Jonathan Cameron
parent
6cffc1f814
commit
bc2c90c974
@ -0,0 +1,15 @@
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* Freescale i.MX28 LRADC device driver
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Required properties:
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- compatible: Should be "fsl,imx28-lradc"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the LRADC interrupts
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Examples:
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lradc@80050000 {
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compatible = "fsl,imx28-lradc";
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reg = <0x80050000 0x2000>;
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interrupts = <10 14 15 16 17 18 19
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20 21 22 23 24 25>;
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};
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@ -200,6 +200,18 @@ config LPC32XX_ADC
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activate only one via device tree selection. Provides direct access
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via sysfs.
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config MXS_LRADC
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tristate "Freescale i.MX28 LRADC"
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depends on ARCH_MXS
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to build support for i.MX28 LRADC convertor
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built into these chips.
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To compile this driver as a module, choose M here: the
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module will be called mxs-lradc.
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config SPEAR_ADC
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tristate "ST SPEAr ADC"
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depends on PLAT_SPEAR
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@ -38,4 +38,5 @@ obj-$(CONFIG_ADT7310) += adt7310.o
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obj-$(CONFIG_ADT7410) += adt7410.o
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obj-$(CONFIG_AD7280) += ad7280a.o
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obj-$(CONFIG_LPC32XX_ADC) += lpc32xx_adc.o
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obj-$(CONFIG_MXS_LRADC) += mxs-lradc.o
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obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
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590
drivers/staging/iio/adc/mxs-lradc.c
Normal file
590
drivers/staging/iio/adc/mxs-lradc.c
Normal file
@ -0,0 +1,590 @@
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/*
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* Freescale i.MX28 LRADC driver
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*
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* Copyright (c) 2012 DENX Software Engineering, GmbH.
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* Marek Vasut <marex@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/sysfs.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <linux/stmp_device.h>
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#include <linux/bitops.h>
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#include <linux/completion.h>
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#include <mach/mxs.h>
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#include <mach/common.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#define DRIVER_NAME "mxs-lradc"
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#define LRADC_MAX_DELAY_CHANS 4
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#define LRADC_MAX_MAPPED_CHANS 8
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#define LRADC_MAX_TOTAL_CHANS 16
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#define LRADC_DELAY_TIMER_HZ 2000
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/*
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* Make this runtime configurable if necessary. Currently, if the buffered mode
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* is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
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* triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
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* seconds. The result is that the samples arrive every 500mS.
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*/
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#define LRADC_DELAY_TIMER_PER 200
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#define LRADC_DELAY_TIMER_LOOP 5
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static const char * const mxs_lradc_irq_name[] = {
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"mxs-lradc-touchscreen",
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"mxs-lradc-thresh0",
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"mxs-lradc-thresh1",
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"mxs-lradc-channel0",
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"mxs-lradc-channel1",
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"mxs-lradc-channel2",
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"mxs-lradc-channel3",
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"mxs-lradc-channel4",
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"mxs-lradc-channel5",
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"mxs-lradc-channel6",
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"mxs-lradc-channel7",
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"mxs-lradc-button0",
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"mxs-lradc-button1",
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};
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struct mxs_lradc_chan {
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uint8_t slot;
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uint8_t flags;
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};
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struct mxs_lradc {
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struct device *dev;
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void __iomem *base;
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int irq[13];
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uint32_t *buffer;
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struct iio_trigger *trig;
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struct mutex lock;
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uint8_t enable;
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struct completion completion;
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};
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#define LRADC_CTRL0 0x00
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#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
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#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
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#define LRADC_CTRL1 0x10
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#define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
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#define LRADC_CTRL1_LRADC_IRQ_MASK 0x1fff
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#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
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#define LRADC_CTRL1_LRADC_IRQ_EN_MASK (0x1fff << 16)
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#define LRADC_CTRL2 0x20
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#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
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#define LRADC_CH(n) (0x50 + (0x10 * (n)))
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#define LRADC_CH_ACCUMULATE (1 << 29)
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#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
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#define LRADC_CH_NUM_SAMPLES_OFFSET 24
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#define LRADC_CH_VALUE_MASK 0x3ffff
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#define LRADC_CH_VALUE_OFFSET 0
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#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
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#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
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#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
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#define LRADC_DELAY_KICK (1 << 20)
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#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
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#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
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#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
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#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
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#define LRADC_DELAY_DELAY_MASK 0x7ff
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#define LRADC_DELAY_DELAY_OFFSET 0
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#define LRADC_CTRL4 0x140
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#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
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#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
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/*
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* Raw I/O operations
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*/
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static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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int *val, int *val2, long m)
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{
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struct mxs_lradc *lradc = iio_priv(iio_dev);
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int ret;
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if (m != IIO_CHAN_INFO_RAW)
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return -EINVAL;
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/* Check for invalid channel */
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if (chan->channel > LRADC_MAX_TOTAL_CHANS)
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return -EINVAL;
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/*
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* See if there is no buffered operation in progess. If there is, simply
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* bail out. This can be improved to support both buffered and raw IO at
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* the same time, yet the code becomes horribly complicated. Therefore I
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* applied KISS principle here.
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*/
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ret = mutex_trylock(&lradc->lock);
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if (!ret)
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return -EBUSY;
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INIT_COMPLETION(lradc->completion);
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/*
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* No buffered operation in progress, map the channel and trigger it.
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* Virtual channel 0 is always used here as the others are always not
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* used if doing raw sampling.
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*/
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writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
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lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
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writel(chan->channel, lradc->base + LRADC_CTRL4);
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writel(0, lradc->base + LRADC_CH(0));
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/* Enable the IRQ and start sampling the channel. */
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writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
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lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
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writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
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/* Wait for completion on the channel, 1 second max. */
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ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
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if (!ret)
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ret = -ETIMEDOUT;
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if (ret < 0)
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goto err;
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/* Read the data. */
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*val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
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ret = IIO_VAL_INT;
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err:
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writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
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lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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mutex_unlock(&lradc->lock);
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return ret;
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}
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static const struct iio_info mxs_lradc_iio_info = {
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.driver_module = THIS_MODULE,
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.read_raw = mxs_lradc_read_raw,
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};
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/*
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* IRQ Handling
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*/
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static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
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{
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struct iio_dev *iio = data;
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struct mxs_lradc *lradc = iio_priv(iio);
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unsigned long reg = readl(lradc->base + LRADC_CTRL1);
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if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK))
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return IRQ_NONE;
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/*
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* Touchscreen IRQ handling code shall probably have priority
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* and therefore shall be placed here.
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*/
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if (iio_buffer_enabled(iio))
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iio_trigger_poll(iio->trig, iio_get_time_ns());
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else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
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complete(&lradc->completion);
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writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK,
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lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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return IRQ_HANDLED;
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}
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/*
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* Trigger handling
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*/
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static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *iio = pf->indio_dev;
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struct mxs_lradc *lradc = iio_priv(iio);
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struct iio_buffer *buffer = iio->buffer;
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const uint32_t chan_value = LRADC_CH_ACCUMULATE |
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((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
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int i, j = 0;
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for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
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lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
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writel(chan_value, lradc->base + LRADC_CH(j));
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lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
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lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
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j++;
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}
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if (iio->scan_timestamp) {
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s64 *timestamp = (s64 *)((u8 *)lradc->buffer +
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ALIGN(j, sizeof(s64)));
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*timestamp = pf->timestamp;
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}
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iio_push_to_buffer(buffer, (u8 *)lradc->buffer, pf->timestamp);
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iio_trigger_notify_done(iio->trig);
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return IRQ_HANDLED;
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}
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static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
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{
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struct iio_dev *iio = trig->private_data;
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struct mxs_lradc *lradc = iio_priv(iio);
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const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
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writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);
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return 0;
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}
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static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
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.owner = THIS_MODULE,
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.set_trigger_state = &mxs_lradc_configure_trigger,
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};
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static int mxs_lradc_trigger_init(struct iio_dev *iio)
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{
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int ret;
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struct iio_trigger *trig;
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trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
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if (trig == NULL)
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return -ENOMEM;
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trig->dev.parent = iio->dev.parent;
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trig->private_data = iio;
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trig->ops = &mxs_lradc_trigger_ops;
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ret = iio_trigger_register(trig);
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if (ret) {
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iio_trigger_free(trig);
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return ret;
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}
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iio->trig = trig;
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return 0;
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}
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static void mxs_lradc_trigger_remove(struct iio_dev *iio)
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{
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iio_trigger_unregister(iio->trig);
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iio_trigger_free(iio->trig);
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}
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static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
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{
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struct mxs_lradc *lradc = iio_priv(iio);
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struct iio_buffer *buffer = iio->buffer;
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int ret = 0, chan, ofs = 0, enable = 0;
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uint32_t ctrl4 = 0;
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uint32_t ctrl1_irq = 0;
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const uint32_t chan_value = LRADC_CH_ACCUMULATE |
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((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
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const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
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if (!len)
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return -EINVAL;
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/*
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* Lock the driver so raw access can not be done during buffered
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* operation. This simplifies the code a lot.
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*/
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ret = mutex_trylock(&lradc->lock);
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if (!ret)
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return -EBUSY;
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lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
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if (!lradc->buffer) {
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ret = -ENOMEM;
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goto err_mem;
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}
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ret = iio_sw_buffer_preenable(iio);
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if (ret < 0)
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goto err_buf;
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writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
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lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
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for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
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ctrl4 |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
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ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
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writel(chan_value, lradc->base + LRADC_CH(ofs));
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enable |= 1 << ofs;
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ofs++;
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};
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writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
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lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
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writel(ctrl4, lradc->base + LRADC_CTRL4);
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writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
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writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
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lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
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return 0;
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err_buf:
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kfree(lradc->buffer);
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err_mem:
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mutex_unlock(&lradc->lock);
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return ret;
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}
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static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
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{
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struct mxs_lradc *lradc = iio_priv(iio);
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writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
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lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
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writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
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writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
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lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
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kfree(lradc->buffer);
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mutex_unlock(&lradc->lock);
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return 0;
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}
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static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
|
||||
const unsigned long *mask)
|
||||
{
|
||||
const int mw = bitmap_weight(mask, iio->masklength);
|
||||
|
||||
return mw <= LRADC_MAX_MAPPED_CHANS;
|
||||
}
|
||||
|
||||
static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
|
||||
.preenable = &mxs_lradc_buffer_preenable,
|
||||
.postenable = &iio_triggered_buffer_postenable,
|
||||
.predisable = &iio_triggered_buffer_predisable,
|
||||
.postdisable = &mxs_lradc_buffer_postdisable,
|
||||
.validate_scan_mask = &mxs_lradc_validate_scan_mask,
|
||||
};
|
||||
|
||||
/*
|
||||
* Driver initialization
|
||||
*/
|
||||
|
||||
#define MXS_ADC_CHAN(idx, chan_type) { \
|
||||
.type = (chan_type), \
|
||||
.indexed = 1, \
|
||||
.scan_index = (idx), \
|
||||
.info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \
|
||||
.channel = (idx), \
|
||||
.scan_type = { \
|
||||
.sign = 'u', \
|
||||
.realbits = 18, \
|
||||
.storagebits = 32, \
|
||||
}, \
|
||||
}
|
||||
|
||||
static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
|
||||
MXS_ADC_CHAN(0, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(1, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(2, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(3, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(4, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(5, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(6, IIO_VOLTAGE),
|
||||
MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
|
||||
MXS_ADC_CHAN(8, IIO_TEMP), /* Temp sense 0 */
|
||||
MXS_ADC_CHAN(9, IIO_TEMP), /* Temp sense 1 */
|
||||
MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
|
||||
MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
|
||||
MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
|
||||
MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
|
||||
MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
|
||||
MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
|
||||
};
|
||||
|
||||
static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
|
||||
{
|
||||
int i;
|
||||
const uint32_t cfg =
|
||||
(LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
|
||||
|
||||
stmp_reset_block(lradc->base);
|
||||
|
||||
for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
|
||||
writel(cfg | (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + i)),
|
||||
lradc->base + LRADC_DELAY(i));
|
||||
|
||||
/* Start internal temperature sensing. */
|
||||
writel(0, lradc->base + LRADC_CTRL2);
|
||||
}
|
||||
|
||||
static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
|
||||
{
|
||||
int i;
|
||||
|
||||
writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
|
||||
lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
|
||||
|
||||
for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
|
||||
writel(0, lradc->base + LRADC_DELAY(i));
|
||||
}
|
||||
|
||||
static int __devinit mxs_lradc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct mxs_lradc *lradc;
|
||||
struct iio_dev *iio;
|
||||
struct resource *iores;
|
||||
int ret = 0;
|
||||
int i;
|
||||
|
||||
/* Allocate the IIO device. */
|
||||
iio = iio_device_alloc(sizeof(*lradc));
|
||||
if (!iio) {
|
||||
dev_err(dev, "Failed to allocate IIO device\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
lradc = iio_priv(iio);
|
||||
|
||||
/* Grab the memory area */
|
||||
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
lradc->dev = &pdev->dev;
|
||||
lradc->base = devm_request_and_ioremap(dev, iores);
|
||||
if (!lradc->base) {
|
||||
ret = -EADDRNOTAVAIL;
|
||||
goto err_addr;
|
||||
}
|
||||
|
||||
/* Grab all IRQ sources */
|
||||
for (i = 0; i < 13; i++) {
|
||||
lradc->irq[i] = platform_get_irq(pdev, i);
|
||||
if (lradc->irq[i] < 0) {
|
||||
ret = -EINVAL;
|
||||
goto err_addr;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, lradc->irq[i],
|
||||
mxs_lradc_handle_irq, 0,
|
||||
mxs_lradc_irq_name[i], iio);
|
||||
if (ret)
|
||||
goto err_addr;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, iio);
|
||||
|
||||
init_completion(&lradc->completion);
|
||||
mutex_init(&lradc->lock);
|
||||
|
||||
iio->name = pdev->name;
|
||||
iio->dev.parent = &pdev->dev;
|
||||
iio->info = &mxs_lradc_iio_info;
|
||||
iio->modes = INDIO_DIRECT_MODE;
|
||||
iio->channels = mxs_lradc_chan_spec;
|
||||
iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
|
||||
|
||||
ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
|
||||
&mxs_lradc_trigger_handler,
|
||||
&mxs_lradc_buffer_ops);
|
||||
if (ret)
|
||||
goto err_addr;
|
||||
|
||||
ret = mxs_lradc_trigger_init(iio);
|
||||
if (ret)
|
||||
goto err_trig;
|
||||
|
||||
/* Register IIO device. */
|
||||
ret = iio_device_register(iio);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register IIO device\n");
|
||||
goto err_dev;
|
||||
}
|
||||
|
||||
/* Configure the hardware. */
|
||||
mxs_lradc_hw_init(lradc);
|
||||
|
||||
return 0;
|
||||
|
||||
err_dev:
|
||||
mxs_lradc_trigger_remove(iio);
|
||||
err_trig:
|
||||
iio_triggered_buffer_cleanup(iio);
|
||||
err_addr:
|
||||
iio_device_free(iio);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devexit mxs_lradc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct iio_dev *iio = platform_get_drvdata(pdev);
|
||||
struct mxs_lradc *lradc = iio_priv(iio);
|
||||
|
||||
mxs_lradc_hw_stop(lradc);
|
||||
|
||||
iio_device_unregister(iio);
|
||||
iio_triggered_buffer_cleanup(iio);
|
||||
mxs_lradc_trigger_remove(iio);
|
||||
iio_device_free(iio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mxs_lradc_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx28-lradc", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
|
||||
|
||||
static struct platform_driver mxs_lradc_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mxs_lradc_dt_ids,
|
||||
},
|
||||
.probe = mxs_lradc_probe,
|
||||
.remove = __devexit_p(mxs_lradc_remove),
|
||||
};
|
||||
|
||||
module_platform_driver(mxs_lradc_driver);
|
||||
|
||||
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
||||
MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
x
Reference in New Issue
Block a user