drm/amdgpu: Add xcc param to SRIOV kiq write and WREG32_SOC15_IP_NO_KIQ (v4)
WREG32/RREG32_SOC15_IP_NO_KIQ and amdgpu_virt_kiq_reg_write_reg_wait are not using the correct rlcg interface or mec engine, respectively. Add xcc instance parameter to them. v4: Use GET_INST and squash commit with: "drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait" v3: xcc not needed for MMMHUB v2: rebase Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -73,9 +73,10 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask)
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uint32_t ref, uint32_t mask,
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uint32_t xcc_inst)
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{
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_inst];
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struct amdgpu_ring *ring = &kiq->ring;
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signed long r, cnt = 0;
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unsigned long flags;
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@ -334,7 +334,8 @@ bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
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void amdgpu_virt_init_setting(struct amdgpu_device *adev);
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void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
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uint32_t reg0, uint32_t rreg1,
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uint32_t ref, uint32_t mask);
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uint32_t ref, uint32_t mask,
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uint32_t xcc_inst);
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
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@ -268,7 +268,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid);
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1 << vmid, GET_INST(GC, 0));
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return;
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}
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@ -229,7 +229,7 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid);
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1 << vmid, GET_INST(GC, 0));
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return;
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}
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@ -817,7 +817,7 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t vmhub, uint32_t flush_type)
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{
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bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
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u32 j, inv_req, tmp, sem, req, ack;
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u32 j, inv_req, tmp, sem, req, ack, inst;
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const unsigned int eng = 17;
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struct amdgpu_vmhub *hub;
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@ -832,13 +832,17 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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/* This is necessary for a HW workaround under SRIOV as well
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* as GFXOFF under bare metal
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*/
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if (adev->gfx.kiq[0].ring.sched.ready &&
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if (vmhub >= AMDGPU_MMHUB0(0))
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inst = GET_INST(GC, 0);
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else
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inst = vmhub;
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if (adev->gfx.kiq[inst].ring.sched.ready &&
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(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
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uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
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uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
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amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
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1 << vmid);
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1 << vmid, inst);
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return;
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}
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@ -856,9 +860,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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for (j = 0; j < adev->usec_timeout; j++) {
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/* a read return value of 1 means semaphore acquire */
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if (vmhub >= AMDGPU_MMHUB0(0))
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tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem);
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tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst);
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else
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tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem);
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tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst);
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if (tmp & 0x1)
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break;
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udelay(1);
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@ -869,9 +873,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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}
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if (vmhub >= AMDGPU_MMHUB0(0))
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WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req);
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WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst);
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else
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WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req);
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WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst);
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/*
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* Issue a dummy read to wait for the ACK register to
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@ -884,9 +888,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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for (j = 0; j < adev->usec_timeout; j++) {
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if (vmhub >= AMDGPU_MMHUB0(0))
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tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack);
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tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst);
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else
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tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack);
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tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst);
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if (tmp & (1 << vmid))
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break;
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udelay(1);
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@ -899,9 +903,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
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* write with 0 means semaphore release
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*/
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if (vmhub >= AMDGPU_MMHUB0(0))
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WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0);
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WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst);
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else
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WREG32_SOC15_IP_NO_KIQ(GC, sem, 0);
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WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst);
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}
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spin_unlock(&adev->gmc.invalidate_lock);
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@ -69,7 +69,7 @@
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#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)
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#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
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#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
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#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
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__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
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@ -86,8 +86,8 @@
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#define WREG32_SOC15_IP(ip, reg, value) \
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__WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
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#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
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__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
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#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \
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__WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
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#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
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__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
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