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arm64: dts: foundation-v8: Enable PSCI mode

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Currently if the Foundation model is running ARM Trusted Firmware then
the kernel, which is configured to use spin tables, cannot start secondary
processors or "power off" the simulation.

After adding a couple of labels to the include file and splitting out the
spin-table configuration into a header, we add a couple of new headers
together with two new DTs (GICv2 + PSCI and GICv3 + PSCI).

The new GICv3+PSCI DT has been boot tested, the remaining three (two of
which existed prior to this patch) have been "tested" by decompiling the
blobs and comparing them against a reference.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Daniel Thompson 2017-09-19 19:32:04 +01:00 committed by Sudeep Holla
parent 2bd6bf03f4
commit bc3d3447b6
10 changed files with 129 additions and 50 deletions
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4
arch/arm64/boot/dts/arm/Makefile
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@ -1,4 +1,6 @@
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += \
foundation-v8.dtb foundation-v8-psci.dtb \
foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb

19
arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi Normal file
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@ -0,0 +1,19 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv2 configuration)
*/
/ {
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <2>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
};

9
arch/arm64/boot/dts/arm/foundation-v8-gicv3-psci.dts Normal file
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@ -0,0 +1,9 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv3+PSCI configuration)
*/
#include "foundation-v8.dtsi"
#include "foundation-v8-gicv3.dtsi"
#include "foundation-v8-psci.dtsi"

25
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dts
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@ -5,26 +5,5 @@
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x200000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <1 9 4>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
};
#include "foundation-v8-gicv3.dtsi"
#include "foundation-v8-spin-table.dtsi"

28
arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi Normal file
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@ -0,0 +1,28 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv3 configuration)
*/
/ {
gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x2f000000 0x0 0x10000>,
<0x0 0x2f100000 0x0 0x200000>,
<0x0 0x2c000000 0x0 0x2000>,
<0x0 0x2c010000 0x0 0x2000>,
<0x0 0x2c02f000 0x0 0x2000>;
interrupts = <1 9 4>;
its: its@2f020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>;
};
};
};

9
arch/arm64/boot/dts/arm/foundation-v8-psci.dts Normal file
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@ -0,0 +1,9 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (GICv2+PSCI configuration)
*/
#include "foundation-v8.dtsi"
#include "foundation-v8-gicv2.dtsi"
#include "foundation-v8-psci.dtsi"

28
arch/arm64/boot/dts/arm/foundation-v8-psci.dtsi Normal file
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@ -0,0 +1,28 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (PSCI configuration)
*/
/ {
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};

25
arch/arm64/boot/dts/arm/foundation-v8-spin-table.dtsi Normal file
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@ -0,0 +1,25 @@
/*
* ARM Ltd.
*
* ARMv8 Foundation model DTS (spin table configuration)
*/
&cpu0 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
&cpu1 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
&cpu2 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
&cpu3 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};

16
arch/arm64/boot/dts/arm/foundation-v8.dts
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@ -5,17 +5,5 @@
*/
#include "foundation-v8.dtsi"
/ {
gic: interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <2>;
interrupt-controller;
reg = <0x0 0x2c001000 0 0x1000>,
<0x0 0x2c002000 0 0x2000>,
<0x0 0x2c004000 0 0x2000>,
<0x0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
};
};
#include "foundation-v8-gicv2.dtsi"
#include "foundation-v8-spin-table.dtsi"

16
arch/arm64/boot/dts/arm/foundation-v8.dtsi
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@ -28,36 +28,28 @@
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@2 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
cpu@3 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};