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Merge branches 'omap/prcm' and 'omap/mfd' of git+ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc into next/devel-2

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This commit is contained in:
Arnd Bergmann 2011-07-17 21:48:22 +02:00
commit bc574e190d
141 changed files with 7325 additions and 7408 deletions
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4
arch/arm/mach-omap1/board-ams-delta.c
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@ -138,7 +138,7 @@ void ams_delta_latch2_write(u16 mask, u16 value)
static void __init ams_delta_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static struct map_desc ams_delta_io_desc[] __initdata = {
@ -391,7 +391,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
.reserve = omap_reserve,
.init_irq = ams_delta_init_irq,
.init_machine = ams_delta_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END
EXPORT_SYMBOL(ams_delta_latch1_write);

4
arch/arm/mach-omap1/board-fsample.c
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@ -329,7 +329,7 @@ static void __init omap_fsample_init(void)
static void __init omap_fsample_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
@ -394,5 +394,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
.reserve = omap_reserve,
.init_irq = omap_fsample_init_irq,
.init_machine = omap_fsample_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-generic.c
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@ -31,7 +31,7 @@
static void __init omap_generic_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
/* assume no Mini-AB port */
@ -99,5 +99,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
.reserve = omap_reserve,
.init_irq = omap_generic_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-h2.c
View File

@ -376,7 +376,7 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
static void __init h2_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static struct omap_usb_config h2_usb_config __initdata = {
@ -466,5 +466,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
.reserve = omap_reserve,
.init_irq = h2_init_irq,
.init_machine = h2_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-h3.c
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@ -439,7 +439,7 @@ static void __init h3_init(void)
static void __init h3_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static void __init h3_map_io(void)
@ -454,5 +454,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
.reserve = omap_reserve,
.init_irq = h3_init_irq,
.init_machine = h3_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-htcherald.c
View File

@ -605,7 +605,7 @@ static void __init htcherald_init_irq(void)
{
printk(KERN_INFO "htcherald_init_irq.\n");
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
MACHINE_START(HERALD, "HTC Herald")
@ -616,5 +616,5 @@ MACHINE_START(HERALD, "HTC Herald")
.reserve = omap_reserve,
.init_irq = htcherald_init_irq,
.init_machine = htcherald_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-innovator.c
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@ -292,7 +292,7 @@ static void __init innovator_init_smc91x(void)
static void __init innovator_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
#ifdef CONFIG_ARCH_OMAP15XX
@ -464,5 +464,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
.reserve = omap_reserve,
.init_irq = innovator_init_irq,
.init_machine = innovator_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-nokia770.c
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@ -51,7 +51,7 @@ static void __init omap_nokia770_init_irq(void)
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static const unsigned int nokia770_keymap[] = {
@ -269,5 +269,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
.reserve = omap_reserve,
.init_irq = omap_nokia770_init_irq,
.init_machine = omap_nokia770_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-osk.c
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@ -282,7 +282,7 @@ static void __init osk_init_cf(void)
static void __init osk_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static struct omap_usb_config osk_usb_config __initdata = {
@ -588,5 +588,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
.reserve = omap_reserve,
.init_irq = osk_init_irq,
.init_machine = osk_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-palmte.c
View File

@ -62,7 +62,7 @@
static void __init omap_palmte_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static const unsigned int palmte_keymap[] = {
@ -280,5 +280,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.reserve = omap_reserve,
.init_irq = omap_palmte_init_irq,
.init_machine = omap_palmte_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-palmtt.c
View File

@ -266,7 +266,7 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
static void __init omap_palmtt_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static struct omap_usb_config palmtt_usb_config __initdata = {
@ -326,5 +326,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
.reserve = omap_reserve,
.init_irq = omap_palmtt_init_irq,
.init_machine = omap_palmtt_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-palmz71.c
View File

@ -61,7 +61,7 @@ static void __init
omap_palmz71_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static const unsigned int palmz71_keymap[] = {
@ -346,5 +346,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
.reserve = omap_reserve,
.init_irq = omap_palmz71_init_irq,
.init_machine = omap_palmz71_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-perseus2.c
View File

@ -297,7 +297,7 @@ static void __init omap_perseus2_init(void)
static void __init omap_perseus2_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_perseus2_io_desc[] __initdata = {
@ -355,5 +355,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
.reserve = omap_reserve,
.init_irq = omap_perseus2_init_irq,
.init_machine = omap_perseus2_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-sx1.c
View File

@ -411,7 +411,7 @@ static void __init omap_sx1_init(void)
static void __init omap_sx1_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
/*----------------------------------------*/
@ -426,5 +426,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
.reserve = omap_reserve,
.init_irq = omap_sx1_init_irq,
.init_machine = omap_sx1_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

4
arch/arm/mach-omap1/board-voiceblue.c
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@ -162,7 +162,7 @@ static struct omap_board_config_kernel voiceblue_config[] = {
static void __init voiceblue_init_irq(void)
{
omap1_init_common_hw();
omap_init_irq();
omap1_init_irq();
}
static void __init voiceblue_map_io(void)
@ -306,5 +306,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
.reserve = omap_reserve,
.init_irq = voiceblue_init_irq,
.init_machine = voiceblue_init,
.timer = &omap_timer,
.timer = &omap1_timer,
MACHINE_END

2
arch/arm/mach-omap1/irq.c
View File

@ -175,7 +175,7 @@ static struct irq_chip omap_irq_chip = {
.irq_set_wake = omap_wake_irq,
};
void __init omap_init_irq(void)
void __init omap1_init_irq(void)
{
int i, j;

4
arch/arm/mach-omap1/mcbsp.c
View File

@ -38,7 +38,7 @@ static void omap1_mcbsp_request(unsigned int id)
* On 1510, 1610 and 1710, McBSP1 and McBSP3
* are DSP public peripherals.
*/
if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
if (id == 0 || id == 2) {
if (dsp_use++ == 0) {
api_clk = clk_get(NULL, "api_ck");
dsp_clk = clk_get(NULL, "dsp_ck");
@ -59,7 +59,7 @@ static void omap1_mcbsp_request(unsigned int id)
static void omap1_mcbsp_free(unsigned int id)
{
if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
if (id == 0 || id == 2) {
if (--dsp_use == 0) {
if (!IS_ERR(api_clk)) {
clk_disable(api_clk);

6
arch/arm/mach-omap1/time.c
View File

@ -297,7 +297,7 @@ static inline int omap_32k_timer_usable(void)
* Timer initialization
* ---------------------------------------------------------------------------
*/
static void __init omap_timer_init(void)
static void __init omap1_timer_init(void)
{
if (omap_32k_timer_usable()) {
preferred_sched_clock_init(1);
@ -307,6 +307,6 @@ static void __init omap_timer_init(void)
}
}
struct sys_timer omap_timer = {
.init = omap_timer_init,
struct sys_timer omap1_timer = {
.init = omap1_timer_init,
};

4
arch/arm/mach-omap1/timer32k.c
View File

@ -183,10 +183,6 @@ static __init void omap_init_32k_timer(void)
bool __init omap_32k_timer_init(void)
{
omap_init_clocksource_32k();
#ifdef CONFIG_OMAP_DM_TIMER
omap_dm_timer_init();
#endif
omap_init_32k_timer();
return true;

20
arch/arm/mach-omap2/Makefile
View File

@ -3,7 +3,7 @@
#
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o
omap-2-3-common = irq.o sdrc.o
@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
omap_hwmod_2xxx_3xxx_ipblock_data.o \
omap_hwmod_2xxx_interconnect_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
omap_hwmod_2xxx_3xxx_ipblock_data.o \
omap_hwmod_2xxx_interconnect_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
omap_hwmod_2xxx_3xxx_interconnect_data.o \
omap_hwmod_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
@ -269,4 +279,4 @@ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
disp-$(CONFIG_OMAP2_DSS) := display.o
obj-y += $(disp-m) $(disp-y)
obj-y += common-board-devices.o
obj-y += common-board-devices.o twl-common.o

4
arch/arm/mach-omap2/board-2430sdp.c
View File

@ -260,7 +260,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
.reserve = omap_reserve,
.map_io = omap_2430sdp_map_io,
.init_early = omap_2430sdp_init_early,
.init_irq = omap_init_irq,
.init_irq = omap2_init_irq,
.init_machine = omap_2430sdp_init,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END

93
arch/arm/mach-omap2/board-3430sdp.c
View File

@ -231,22 +231,6 @@ static void __init omap_3430sdp_init_early(void)
omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
}
static int sdp3430_batt_table[] = {
/* 0 C*/
30800, 29500, 28300, 27100,
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
4040, 3910, 3790, 3670, 3550
};
static struct twl4030_bci_platform_data sdp3430_bci_data = {
.battery_tmp_tbl = sdp3430_batt_table,
.tblsize = ARRAY_SIZE(sdp3430_batt_table),
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
@ -292,14 +276,6 @@ static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
.setup = sdp3430_twl_gpio_setup,
};
static struct twl4030_usb_data sdp3430_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_madc_platform_data sdp3430_madc_data = {
.irq_line = 1,
};
/* regulator consumer mappings */
/* ads7846 on SPI */
@ -307,16 +283,6 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
@ -433,54 +399,10 @@ static struct regulator_init_data sdp3430_vsim = {
.consumer_supplies = sdp3430_vsim_supplies,
};
/* VDAC for DSS driving S-Video */
static struct regulator_init_data sdp3430_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
.consumer_supplies = sdp3430_vdda_dac_supplies,
};
static struct regulator_init_data sdp3430_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
.consumer_supplies = sdp3430_vpll2_supplies,
};
static struct twl4030_codec_audio_data sdp3430_audio;
static struct twl4030_codec_data sdp3430_codec = {
.audio_mclk = 26000000,
.audio = &sdp3430_audio,
};
static struct twl4030_platform_data sdp3430_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.bci = &sdp3430_bci_data,
.gpio = &sdp3430_gpio_data,
.madc = &sdp3430_madc_data,
.keypad = &sdp3430_kp_data,
.usb = &sdp3430_usb_data,
.codec = &sdp3430_codec,
.vaux1 = &sdp3430_vaux1,
.vaux2 = &sdp3430_vaux2,
@ -489,14 +411,21 @@ static struct twl4030_platform_data sdp3430_twldata = {
.vmmc1 = &sdp3430_vmmc1,
.vmmc2 = &sdp3430_vmmc2,
.vsim = &sdp3430_vsim,
.vdac = &sdp3430_vdac,
.vpll2 = &sdp3430_vpll2,
};
static int __init omap3430_i2c_init(void)
{
/* i2c1 for PMIC only */
omap3_pmic_get_config(&sdp3430_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
sdp3430_twldata.vdac->constraints.apply_uV = true;
sdp3430_twldata.vpll2->constraints.apply_uV = true;
sdp3430_twldata.vpll2->constraints.name = "VDVI";
omap3_pmic_init("twl4030", &sdp3430_twldata);
/* i2c2 on camera connector (for sensor control) and optional isp1301 */
omap_register_i2c_bus(2, 400, NULL, 0);
/* i2c3 on display connector (for DVI, tfp410) */
@ -804,7 +733,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_3430sdp_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap_3430sdp_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

4
arch/arm/mach-omap2/board-3630sdp.c
View File

@ -219,7 +219,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_sdp_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap_sdp_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

200
arch/arm/mach-omap2/board-4430sdp.c
View File

@ -22,6 +22,7 @@
#include <linux/i2c/twl.h>
#include <linux/gpio_keys.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/leds.h>
#include <linux/leds_pwm.h>
@ -40,7 +41,6 @@
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "control.h"
#include "common-board-devices.h"
@ -276,11 +276,40 @@ static struct platform_device sdp4430_lcd_device = {
.id = -1,
};
static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
};
static struct regulator_init_data sdp4430_vbat_data = {
.constraints = {
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply),
.consumer_supplies = sdp4430_vbat_supply,
};
static struct fixed_voltage_config sdp4430_vbat_pdata = {
.supply_name = "VBAT",
.microvolts = 3750000,
.init_data = &sdp4430_vbat_data,
.gpio = -EINVAL,
};
static struct platform_device sdp4430_vbat = {
.name = "reg-fixed-voltage",
.id = -1,
.dev = {
.platform_data = &sdp4430_vbat_pdata,
},
};
static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_lcd_device,
&sdp4430_gpio_keys_device,
&sdp4430_leds_gpio,
&sdp4430_leds_pwm,
&sdp4430_vbat,
};
static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@ -295,9 +324,6 @@ static void __init omap_4430sdp_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1);
#endif
}
static struct omap_musb_board_data musb_board_data = {
@ -306,14 +332,6 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
static struct twl4030_usb_data omap4_usbphy_data = {
.phy_init = omap4430_phy_init,
.phy_exit = omap4430_phy_exit,
.phy_power = omap4430_phy_power,
.phy_set_clock = omap4430_phy_set_clk,
.phy_suspend = omap4430_phy_suspend,
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 2,
@ -333,16 +351,7 @@ static struct omap2_hsmmc_info mmc[] = {
};
static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
{
.supply = "vmmc",
.dev_name = "omap_hsmmc.1",
},
};
static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
{
.supply = "vmmc",
.dev_name = "omap_hsmmc.0",
},
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
@ -399,65 +408,10 @@ static struct regulator_init_data sdp4430_vaux1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
.consumer_supplies = sdp4430_vaux_supply,
};
static struct regulator_init_data sdp4430_vaux2 = {
.constraints = {
.min_uV = 1200000,
.max_uV = 2800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data sdp4430_vaux3 = {
.constraints = {
.min_uV = 1000000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
/* VMMC1 for MMC1 card */
static struct regulator_init_data sdp4430_vmmc = {
.constraints = {
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = sdp4430_vmmc_supply,
};
static struct regulator_init_data sdp4430_vpp = {
.constraints = {
.min_uV = 1800000,
.max_uV = 2500000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data sdp4430_vusim = {
.constraints = {
.min_uV = 1200000,
@ -471,74 +425,36 @@ static struct regulator_init_data sdp4430_vusim = {
},
};
static struct regulator_init_data sdp4430_vana = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
static struct twl4030_codec_data twl6040_codec = {
/* single-step ramp for headset and handsfree */
.hs_left_step = 0x0f,
.hs_right_step = 0x0f,
.hf_left_step = 0x1d,
.hf_right_step = 0x1d,
};
static struct regulator_init_data sdp4430_vcxio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
static struct twl4030_vibra_data twl6040_vibra = {
.vibldrv_res = 8,
.vibrdrv_res = 3,
.viblmotor_res = 10,
.vibrmotor_res = 10,
.vddvibl_uV = 0, /* fixed volt supply - VBAT */
.vddvibr_uV = 0, /* fixed volt supply - VBAT */
};
static struct regulator_init_data sdp4430_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data sdp4430_vusb = {
.constraints = {
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data sdp4430_clk32kg = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
static struct twl4030_audio_data twl6040_audio = {
.codec = &twl6040_codec,
.vibra = &twl6040_vibra,
.audpwron_gpio = 127,
.naudint_irq = OMAP44XX_IRQ_SYS_2N,
.irq_base = TWL6040_CODEC_IRQ_BASE,
};
static struct twl4030_platform_data sdp4430_twldata = {
.irq_base = TWL6030_IRQ_BASE,
.irq_end = TWL6030_IRQ_END,
.audio = &twl6040_audio,
/* Regulators */
.vmmc = &sdp4430_vmmc,
.vpp = &sdp4430_vpp,
.vusim = &sdp4430_vusim,
.vana = &sdp4430_vana,
.vcxio = &sdp4430_vcxio,
.vdac = &sdp4430_vdac,
.vusb = &sdp4430_vusb,
.vaux1 = &sdp4430_vaux1,
.vaux2 = &sdp4430_vaux2,
.vaux3 = &sdp4430_vaux3,
.clk32kg = &sdp4430_clk32kg,
.usb = &omap4_usbphy_data
};
static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
@ -556,6 +472,16 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
};
static int __init omap4_i2c_init(void)
{
omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC |
TWL_COMMON_REGULATOR_VAUX2 |
TWL_COMMON_REGULATOR_VAUX3 |
TWL_COMMON_REGULATOR_VMMC |
TWL_COMMON_REGULATOR_VPP |
TWL_COMMON_REGULATOR_VANA |
TWL_COMMON_REGULATOR_VCXIO |
TWL_COMMON_REGULATOR_VUSB |
TWL_COMMON_REGULATOR_CLK32KG);
omap4_pmic_init("twl6030", &sdp4430_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
@ -773,5 +699,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
.init_early = omap_4430sdp_init_early,
.init_irq = gic_init_irq,
.init_machine = omap_4430sdp_init,
.timer = &omap_timer,
.timer = &omap4_timer,
MACHINE_END

4
arch/arm/mach-omap2/board-am3517crane.c
View File

@ -104,7 +104,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = am3517_crane_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = am3517_crane_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

4
arch/arm/mach-omap2/board-am3517evm.c
View File

@ -494,7 +494,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = am3517_evm_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = am3517_evm_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

4
arch/arm/mach-omap2/board-apollon.c
View File

@ -354,7 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
.reserve = omap_reserve,
.map_io = omap_apollon_map_io,
.init_early = omap_apollon_init_early,
.init_irq = omap_init_irq,
.init_irq = omap2_init_irq,
.init_machine = omap_apollon_init,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END

81
arch/arm/mach-omap2/board-cm-t35.c
View File

@ -162,9 +162,7 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
static struct omap_nand_platform_data cm_t35_nand_data = {
.parts = cm_t35_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.cs = 0,
};
static void __init cm_t35_init_nand(void)
@ -337,19 +335,17 @@ static void __init cm_t35_init_display(void)
}
}
static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply cm_t35_vsim_supply = {
.supply = "vmmc_aux",
static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply cm_t35_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
static struct regulator_consumer_supply cm_t35_vdvi_supply =
REGULATOR_SUPPLY("vdvi", "omapdss");
static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
REGULATOR_SUPPLY("vdvi", "omapdss"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {
@ -362,8 +358,8 @@ static struct regulator_init_data cm_t35_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &cm_t35_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
.consumer_supplies = cm_t35_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@ -377,41 +373,8 @@ static struct regulator_init_data cm_t35_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &cm_t35_vsim_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data cm_t35_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &cm_t35_vdac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data cm_t35_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &cm_t35_vdvi_supply,
};
static struct twl4030_usb_data cm_t35_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
.num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
.consumer_supplies = cm_t35_vsim_supply,
};
static uint32_t cm_t35_keymap[] = {
@ -481,10 +444,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
cm_t35_vmmc1_supply.dev = mmc[0].dev;
cm_t35_vsim_supply.dev = mmc[0].dev;
return 0;
}
@ -496,21 +455,23 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
};
static struct twl4030_platform_data cm_t35_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.keypad = &cm_t35_kp_data,
.usb = &cm_t35_usb_data,
.gpio = &cm_t35_gpio_data,
.vmmc1 = &cm_t35_vmmc1,
.vsim = &cm_t35_vsim,
.vdac = &cm_t35_vdac,
.vpll2 = &cm_t35_vpll2,
};
static void __init cm_t35_init_i2c(void)
{
omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
cm_t35_twldata.vpll2->constraints.name = "VDVI";
cm_t35_twldata.vpll2->num_consumer_supplies =
ARRAY_SIZE(cm_t35_vdvi_supply);
cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
omap3_pmic_init("tps65930", &cm_t35_twldata);
}
@ -646,7 +607,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = cm_t35_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = cm_t35_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

5
arch/arm/mach-omap2/board-cm-t3517.c
View File

@ -236,7 +236,6 @@ static struct mtd_partition cm_t3517_nand_partitions[] = {
static struct omap_nand_platform_data cm_t3517_nand_data = {
.parts = cm_t3517_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.cs = 0,
};
@ -304,7 +303,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = cm_t3517_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = cm_t3517_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

64
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -58,7 +58,6 @@
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "common-board-devices.h"
#define OMAP_DM9000_GPIO_IRQ 25
@ -130,13 +129,14 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
gpio_set_value_cansleep(dssdev->reset_gpio, 0);
}
static struct regulator_consumer_supply devkit8000_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* ads7846 on SPI */
static struct regulator_consumer_supply devkit8000_vio_supply =
REGULATOR_SUPPLY("vcc", "spi2.0");
static struct regulator_consumer_supply devkit8000_vio_supply[] = {
REGULATOR_SUPPLY("vcc", "spi2.0"),
};
static struct panel_generic_dpi_data lcd_panel = {
.name = "generic",
@ -186,9 +186,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
.default_device = &devkit8000_lcd_device,
};
static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_1),
KEY(1, 0, KEY_2),
@ -284,22 +281,8 @@ static struct regulator_init_data devkit8000_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &devkit8000_vmmc1_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data devkit8000_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &devkit8000_vdda_dac_supply,
.num_consumer_supplies = ARRAY_SIZE(devkit8000_vmmc1_supply),
.consumer_supplies = devkit8000_vmmc1_supply,
};
/* VPLL1 for digital video outputs */
@ -327,31 +310,14 @@ static struct regulator_init_data devkit8000_vio = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &devkit8000_vio_supply,
};
static struct twl4030_usb_data devkit8000_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data devkit8000_audio_data;
static struct twl4030_codec_data devkit8000_codec_data = {
.audio_mclk = 26000000,
.audio = &devkit8000_audio_data,
.num_consumer_supplies = ARRAY_SIZE(devkit8000_vio_supply),
.consumer_supplies = devkit8000_vio_supply,
};
static struct twl4030_platform_data devkit8000_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &devkit8000_usb_data,
.gpio = &devkit8000_gpio_data,
.codec = &devkit8000_codec_data,
.vmmc1 = &devkit8000_vmmc1,
.vdac = &devkit8000_vdac,
.vpll1 = &devkit8000_vpll1,
.vio = &devkit8000_vio,
.keypad = &devkit8000_kp_data,
@ -359,6 +325,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
static int __init devkit8000_i2c_init(void)
{
omap3_pmic_get_config(&devkit8000_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC);
omap3_pmic_init("tps65930", &devkit8000_twldata);
/* Bus 3 is attached to the DVI port where devices like the pico DLP
* projector don't work reliably with 400kHz */
@ -438,10 +407,7 @@ static void __init devkit8000_init_early(void)
static void __init devkit8000_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap3_init_irq();
}
#define OMAP_DM9000_BASE 0x2c000000
@ -707,5 +673,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
.init_early = devkit8000_init_early,
.init_irq = devkit8000_init_irq,
.init_machine = devkit8000_init,
.timer = &omap_timer,
.timer = &omap3_secure_timer,
MACHINE_END

4
arch/arm/mach-omap2/board-flash.c
View File

@ -132,11 +132,7 @@ static struct gpmc_timings nand_timings = {
};
static struct omap_nand_platform_data board_nand_data = {
.nand_setup = NULL,
.gpmc_t = &nand_timings,
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.dev_ready = NULL,
.devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
};
void

4
arch/arm/mach-omap2/board-generic.c
View File

@ -70,7 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
.reserve = omap_reserve,
.map_io = omap_generic_map_io,
.init_early = omap_generic_init_early,
.init_irq = omap_init_irq,
.init_irq = omap2_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END

4
arch/arm/mach-omap2/board-h4.c
View File

@ -298,7 +298,7 @@ static void __init omap_h4_init_early(void)
static void __init omap_h4_init_irq(void)
{
omap_init_irq();
omap2_init_irq();
}
static struct at24_platform_data m24c01 = {
@ -388,5 +388,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
.init_early = omap_h4_init_early,
.init_irq = omap_h4_init_irq,
.init_machine = omap_h4_init,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END

79
arch/arm/mach-omap2/board-igep0020.c
View File

@ -222,8 +222,9 @@ static inline void __init igep2_init_smsc911x(void)
static inline void __init igep2_init_smsc911x(void) { }
#endif
static struct regulator_consumer_supply igep_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
static struct regulator_consumer_supply igep_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data igep_vmmc1 = {
@ -236,12 +237,13 @@ static struct regulator_init_data igep_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &igep_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
.consumer_supplies = igep_vmmc1_supply,
};
static struct regulator_consumer_supply igep_vio_supply =
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
static struct regulator_consumer_supply igep_vio_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
};
static struct regulator_init_data igep_vio = {
.constraints = {
@ -254,20 +256,21 @@ static struct regulator_init_data igep_vio = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &igep_vio_supply,
.num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
.consumer_supplies = igep_vio_supply,
};
static struct regulator_consumer_supply igep_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_consumer_supply igep_vmmc2_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
static struct regulator_init_data igep_vmmc2 = {
.constraints = {
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
},
.num_consumer_supplies = 1,
.consumer_supplies = &igep_vmmc2_supply,
.num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
.consumer_supplies = igep_vmmc2_supply,
};
static struct fixed_voltage_config igep_vwlan = {
@ -440,10 +443,6 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
.setup = igep_twl_gpio_setup,
};
static struct twl4030_usb_data igep_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static int igep2_enable_dvi(struct omap_dss_device *dssdev)
{
gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
@ -480,26 +479,6 @@ static struct omap_dss_board_info igep2_dss_data = {
.default_device = &igep2_dvi_device,
};
static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct regulator_init_data igep2_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies),
.consumer_supplies = igep2_vpll2_supplies,
};
static void __init igep2_display_init(void)
{
int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
@ -519,13 +498,6 @@ static void __init igep_init_early(void)
m65kxxxxam_sdrc_params);
}
static struct twl4030_codec_audio_data igep2_audio_data;
static struct twl4030_codec_data igep2_codec_data = {
.audio_mclk = 26000000,
.audio = &igep2_audio_data,
};
static int igep2_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
@ -558,11 +530,7 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
};
static struct twl4030_platform_data igep_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &igep_usb_data,
.gpio = &igep_twl4030_gpio_pdata,
.vmmc1 = &igep_vmmc1,
.vio = &igep_vio,
@ -578,6 +546,8 @@ static void __init igep_i2c_init(void)
{
int ret;
omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
if (machine_is_igep0020()) {
/*
* Bus 3 is attached to the DVI port where devices like the
@ -588,9 +558,12 @@ static void __init igep_i2c_init(void)
if (ret)
pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
igep_twldata.codec = &igep2_codec_data;
igep_twldata.keypad = &igep2_keypad_pdata;
igep_twldata.vpll2 = &igep2_vpll2;
/* Get common pmic data */
omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VPLL2);
igep_twldata.vpll2->constraints.apply_uV = true;
igep_twldata.vpll2->constraints.name = "VDVI";
}
omap3_pmic_init("twl4030", &igep_twldata);
@ -703,9 +676,9 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = igep_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = igep_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END
MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@ -713,7 +686,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = igep_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = igep_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

29
arch/arm/mach-omap2/board-ldp.c
View File

@ -199,22 +199,14 @@ static void __init omap_ldp_init_early(void)
omap2_init_common_devices(NULL, NULL);
}
static struct twl4030_usb_data ldp_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_gpio_platform_data ldp_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
.irq_end = TWL4030_GPIO_IRQ_END,
};
static struct twl4030_madc_platform_data ldp_madc_data = {
.irq_line = 1,
};
static struct regulator_consumer_supply ldp_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@ -228,8 +220,8 @@ static struct regulator_init_data ldp_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &ldp_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
.consumer_supplies = ldp_vmmc1_supply,
};
/* ads7846 on SPI */
@ -253,12 +245,7 @@ static struct regulator_init_data ldp_vaux1 = {
};
static struct twl4030_platform_data ldp_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.madc = &ldp_madc_data,
.usb = &ldp_usb_data,
.vmmc1 = &ldp_vmmc1,
.vaux1 = &ldp_vaux1,
.gpio = &ldp_gpio_data,
@ -267,6 +254,8 @@ static struct twl4030_platform_data ldp_twldata = {
static int __init omap_i2c_init(void)
{
omap3_pmic_get_config(&ldp_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
omap3_pmic_init("twl4030", &ldp_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);
@ -341,8 +330,6 @@ static void __init omap_ldp_init(void)
ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
ldp_vmmc1_supply.dev = mmc[0].dev;
}
MACHINE_START(OMAP_LDP, "OMAP LDP board")
@ -350,7 +337,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_ldp_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap_ldp_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

12
arch/arm/mach-omap2/board-n8x0.c
View File

@ -699,9 +699,9 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
.reserve = omap_reserve,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
.init_irq = omap_init_irq,
.init_irq = omap2_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END
MACHINE_START(NOKIA_N810, "Nokia N810")
@ -709,9 +709,9 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
.reserve = omap_reserve,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
.init_irq = omap_init_irq,
.init_irq = omap2_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@ -719,7 +719,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.reserve = omap_reserve,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
.init_irq = omap_init_irq,
.init_irq = omap2_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
.timer = &omap2_timer,
MACHINE_END

89
arch/arm/mach-omap2/board-omap3beagle.c
View File

@ -50,7 +50,6 @@
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "pm.h"
#include "common-board-devices.h"
@ -210,14 +209,6 @@ static struct omap_dss_board_info beagle_dss_data = {
.default_device = &beagle_dvi_device,
};
static struct regulator_consumer_supply beagle_vdac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static void __init beagle_display_init(void)
{
int r;
@ -239,12 +230,12 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
static struct regulator_consumer_supply beagle_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply beagle_vsim_supply = {
.supply = "vmmc_aux",
static struct regulator_consumer_supply beagle_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct gpio_led gpio_leds[];
@ -267,10 +258,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
beagle_vmmc1_supply.dev = mmc[0].dev;
beagle_vsim_supply.dev = mmc[0].dev;
/*
* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
* high / others active low)
@ -336,8 +323,8 @@ static struct regulator_init_data beagle_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &beagle_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
.consumer_supplies = beagle_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@ -351,62 +338,15 @@ static struct regulator_init_data beagle_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &beagle_vsim_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data beagle_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &beagle_vdac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data beagle_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies),
.consumer_supplies = beagle_vdvi_supplies,
};
static struct twl4030_usb_data beagle_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data beagle_audio_data;
static struct twl4030_codec_data beagle_codec_data = {
.audio_mclk = 26000000,
.audio = &beagle_audio_data,
.num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
.consumer_supplies = beagle_vsim_supply,
};
static struct twl4030_platform_data beagle_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &beagle_usb_data,
.gpio = &beagle_gpio_data,
.codec = &beagle_codec_data,
.vmmc1 = &beagle_vmmc1,
.vsim = &beagle_vsim,
.vdac = &beagle_vdac,
.vpll2 = &beagle_vpll2,
};
static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
@ -417,6 +357,12 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
static int __init omap3_beagle_i2c_init(void)
{
omap3_pmic_get_config(&beagle_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
beagle_twldata.vpll2->constraints.name = "VDVI";
omap3_pmic_init("twl4030", &beagle_twldata);
/* Bus 3 is attached to the DVI port where devices like the pico DLP
* projector don't work reliably with 400kHz */
@ -486,10 +432,7 @@ static void __init omap3_beagle_init_early(void)
static void __init omap3_beagle_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap3_init_irq();
}
static struct platform_device *omap3_beagle_devices[] __initdata = {
@ -599,5 +542,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
.init_early = omap3_beagle_init_early,
.init_irq = omap3_beagle_init_irq,
.init_machine = omap3_beagle_init,
.timer = &omap_timer,
.timer = &omap3_secure_timer,
MACHINE_END

111
arch/arm/mach-omap2/board-omap3evm.c
View File

@ -273,12 +273,12 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
.default_device = &omap3_evm_lcd_device,
};
static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply omap3evm_vsim_supply = {
.supply = "vmmc_aux",
static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@ -292,8 +292,8 @@ static struct regulator_init_data omap3evm_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3evm_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
.consumer_supplies = omap3evm_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@ -307,8 +307,8 @@ static struct regulator_init_data omap3evm_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3evm_vsim_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
.consumer_supplies = omap3evm_vsim_supply,
};
static struct omap2_hsmmc_info mmc[] = {
@ -365,10 +365,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
omap3evm_vmmc1_supply.dev = mmc[0].dev;
omap3evm_vsim_supply.dev = mmc[0].dev;
/*
* Most GPIOs are for USB OTG. Some are mostly sent to
* the P2 connector; notably LEDA for the LCD backlight.
@ -400,10 +396,6 @@ static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
.setup = omap3evm_twl_gpio_setup,
};
static struct twl4030_usb_data omap3evm_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_DOWN),
@ -438,58 +430,10 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
.rep = 1,
};
static struct twl4030_madc_platform_data omap3evm_madc_data = {
.irq_line = 1,
};
static struct twl4030_codec_audio_data omap3evm_audio_data;
static struct twl4030_codec_data omap3evm_codec_data = {
.audio_mclk = 26000000,
.audio = &omap3evm_audio_data,
};
static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_evm_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3_evm_vdda_dac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct regulator_init_data omap3_evm_vpll2 = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies),
.consumer_supplies = omap3_evm_vpll2_supplies,
};
/* ads7846 on SPI */
static struct regulator_consumer_supply omap3evm_vio_supply =
REGULATOR_SUPPLY("vcc", "spi1.0");
static struct regulator_consumer_supply omap3evm_vio_supply[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
/* VIO for ads7846 */
static struct regulator_init_data omap3evm_vio = {
@ -502,8 +446,8 @@ static struct regulator_init_data omap3evm_vio = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3evm_vio_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
.consumer_supplies = omap3evm_vio_supply,
};
#ifdef CONFIG_WL12XX_PLATFORM_DATA
@ -511,16 +455,17 @@ static struct regulator_init_data omap3evm_vio = {
#define OMAP3EVM_WLAN_PMENA_GPIO (150)
#define OMAP3EVM_WLAN_IRQ_GPIO (149)
static struct regulator_consumer_supply omap3evm_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
/* VMMC2 for driving the WL12xx module */
static struct regulator_init_data omap3evm_vmmc2 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3evm_vmmc2_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
.consumer_supplies = omap3evm_vmmc2_supply,
};
static struct fixed_voltage_config omap3evm_vwlan = {
@ -548,17 +493,9 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
#endif
static struct twl4030_platform_data omap3evm_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.keypad = &omap3evm_kp_data,
.madc = &omap3evm_madc_data,
.usb = &omap3evm_usb_data,
.gpio = &omap3evm_gpio_data,
.codec = &omap3evm_codec_data,
.vdac = &omap3_evm_vdac,
.vpll2 = &omap3_evm_vpll2,
.vio = &omap3evm_vio,
.vmmc1 = &omap3evm_vmmc1,
.vsim = &omap3evm_vsim,
@ -566,6 +503,14 @@ static struct twl4030_platform_data omap3evm_twldata = {
static int __init omap3_evm_i2c_init(void)
{
omap3_pmic_get_config(&omap3evm_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
omap3evm_twldata.vdac->constraints.apply_uV = true;
omap3evm_twldata.vpll2->constraints.apply_uV = true;
omap3_pmic_init("twl4030", &omap3evm_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);
@ -740,7 +685,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3_evm_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap3_evm_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

19
arch/arm/mach-omap2/board-omap3logic.c
View File

@ -35,7 +35,6 @@
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "control.h"
#include "common-board-devices.h"
@ -55,8 +54,8 @@
#define OMAP3_TORPEDO_MMC_GPIO_CD 127
#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129
static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@ -71,8 +70,8 @@ static struct regulator_init_data omap3logic_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3logic_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply),
.consumer_supplies = omap3logic_vmmc1_supply,
};
static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
@ -130,8 +129,6 @@ static void __init board_mmc_init(void)
}
omap2_hsmmc_init(board_mmc_info);
/* link regulators to MMC adapters */
omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
}
static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@ -215,16 +212,16 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_early = omap3logic_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap3logic_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END
MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_early = omap3logic_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap3logic_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

119
arch/arm/mach-omap2/board-omap3pandora.c
View File

@ -320,17 +320,17 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
.setup = omap3pandora_twl_gpio_setup,
};
static struct regulator_consumer_supply pandora_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
static struct regulator_consumer_supply pandora_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply pandora_vmmc2_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_consumer_supply pandora_vmmc2_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1")
};
static struct regulator_consumer_supply pandora_vmmc3_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
static struct regulator_consumer_supply pandora_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
};
static struct regulator_consumer_supply pandora_vdds_supplies[] = {
REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
@ -338,11 +338,13 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct regulator_consumer_supply pandora_vcc_lcd_supply =
REGULATOR_SUPPLY("vcc", "display0");
static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
REGULATOR_SUPPLY("vcc", "display0"),
};
static struct regulator_consumer_supply pandora_usb_phy_supply =
REGULATOR_SUPPLY("hsusb0", "ehci-omap.0");
static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
};
/* ads7846 on SPI and 2 nub controllers on I2C */
static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
@ -351,8 +353,9 @@ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
REGULATOR_SUPPLY("vcc", "3-0067"),
};
static struct regulator_consumer_supply pandora_adac_supply =
REGULATOR_SUPPLY("vcc", "soc-audio");
static struct regulator_consumer_supply pandora_adac_supply[] = {
REGULATOR_SUPPLY("vcc", "soc-audio"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data pandora_vmmc1 = {
@ -365,8 +368,8 @@ static struct regulator_init_data pandora_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(pandora_vmmc1_supply),
.consumer_supplies = pandora_vmmc1_supply,
};
/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
@ -380,38 +383,8 @@ static struct regulator_init_data pandora_vmmc2 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_vmmc2_supply,
};
/* VDAC for DSS driving S-Video */
static struct regulator_init_data pandora_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_vdda_dac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data pandora_vpll2 = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies),
.consumer_supplies = pandora_vdds_supplies,
.num_consumer_supplies = ARRAY_SIZE(pandora_vmmc2_supply),
.consumer_supplies = pandora_vmmc2_supply,
};
/* VAUX1 for LCD */
@ -425,8 +398,8 @@ static struct regulator_init_data pandora_vaux1 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_vcc_lcd_supply,
.num_consumer_supplies = ARRAY_SIZE(pandora_vcc_lcd_supply),
.consumer_supplies = pandora_vcc_lcd_supply,
};
/* VAUX2 for USB host PHY */
@ -440,8 +413,8 @@ static struct regulator_init_data pandora_vaux2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_usb_phy_supply,
.num_consumer_supplies = ARRAY_SIZE(pandora_usb_phy_supply),
.consumer_supplies = pandora_usb_phy_supply,
};
/* VAUX4 for ads7846 and nubs */
@ -470,8 +443,8 @@ static struct regulator_init_data pandora_vsim = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_adac_supply,
.num_consumer_supplies = ARRAY_SIZE(pandora_adac_supply),
.consumer_supplies = pandora_adac_supply,
};
/* Fixed regulator internal to Wifi module */
@ -479,8 +452,8 @@ static struct regulator_init_data pandora_vmmc3 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &pandora_vmmc3_supply,
.num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
.consumer_supplies = pandora_vmmc3_supply,
};
static struct fixed_voltage_config pandora_vwlan = {
@ -501,29 +474,12 @@ static struct platform_device pandora_vwlan_device = {
},
};
static struct twl4030_usb_data omap3pandora_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data omap3pandora_audio_data;
static struct twl4030_codec_data omap3pandora_codec_data = {
.audio_mclk = 26000000,
.audio = &omap3pandora_audio_data,
};
static struct twl4030_bci_platform_data pandora_bci_data;
static struct twl4030_platform_data omap3pandora_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
.gpio = &omap3pandora_gpio_data,
.usb = &omap3pandora_usb_data,
.codec = &omap3pandora_codec_data,
.vmmc1 = &pandora_vmmc1,
.vmmc2 = &pandora_vmmc2,
.vdac = &pandora_vdac,
.vpll2 = &pandora_vpll2,
.vaux1 = &pandora_vaux1,
.vaux2 = &pandora_vaux2,
.vaux4 = &pandora_vaux4,
@ -541,6 +497,17 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
static int __init omap3pandora_i2c_init(void)
{
omap3_pmic_get_config(&omap3pandora_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
omap3pandora_twldata.vdac->constraints.apply_uV = true;
omap3pandora_twldata.vpll2->constraints.apply_uV = true;
omap3pandora_twldata.vpll2->num_consumer_supplies =
ARRAY_SIZE(pandora_vdds_supplies);
omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies;
omap3_pmic_init("tps65950", &omap3pandora_twldata);
/* i2c2 pins are not connected */
omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
@ -643,7 +610,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3pandora_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap3pandora_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

99
arch/arm/mach-omap2/board-omap3stalker.c
View File

@ -52,7 +52,6 @@
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "common-board-devices.h"
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@ -206,12 +205,12 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
.default_device = &omap3_stalker_dvi_device,
};
static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply omap3stalker_vsim_supply = {
.supply = "vmmc_aux",
static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@ -224,8 +223,8 @@ static struct regulator_init_data omap3stalker_vmmc1 = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3stalker_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3stalker_vmmc1_supply),
.consumer_supplies = omap3stalker_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@ -238,8 +237,8 @@ static struct regulator_init_data omap3stalker_vsim = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3stalker_vsim_supply,
.num_consumer_supplies = ARRAY_SIZE(omap3stalker_vsim_supply),
.consumer_supplies = omap3stalker_vsim_supply,
};
static struct omap2_hsmmc_info mmc[] = {
@ -321,10 +320,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
omap3stalker_vmmc1_supply.dev = mmc[0].dev;
omap3stalker_vsim_supply.dev = mmc[0].dev;
/*
* Most GPIOs are for USB OTG. Some are mostly sent to
* the P2 connector; notably LEDA for the LCD backlight.
@ -354,10 +349,6 @@ static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
.setup = omap3stalker_twl_gpio_setup,
};
static struct twl4030_usb_data omap3stalker_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_DOWN),
@ -392,68 +383,10 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
.rep = 1,
};
static struct twl4030_madc_platform_data omap3stalker_madc_data = {
.irq_line = 1,
};
static struct twl4030_codec_audio_data omap3stalker_audio_data;
static struct twl4030_codec_data omap3stalker_codec_data = {
.audio_mclk = 26000000,
.audio = &omap3stalker_audio_data,
};
static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
/* VDAC for DSS driving S-Video */
static struct regulator_init_data omap3_stalker_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap3_stalker_vdda_dac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct regulator_init_data omap3_stalker_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
.consumer_supplies = omap3_stalker_vpll2_supplies,
};
static struct twl4030_platform_data omap3stalker_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.keypad = &omap3stalker_kp_data,
.madc = &omap3stalker_madc_data,
.usb = &omap3stalker_usb_data,
.gpio = &omap3stalker_gpio_data,
.codec = &omap3stalker_codec_data,
.vdac = &omap3_stalker_vdac,
.vpll2 = &omap3_stalker_vpll2,
.vmmc1 = &omap3stalker_vmmc1,
.vsim = &omap3stalker_vsim,
};
@ -474,6 +407,15 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
static int __init omap3_stalker_i2c_init(void)
{
omap3_pmic_get_config(&omap3stalker_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
omap3stalker_twldata.vdac->constraints.apply_uV = true;
omap3stalker_twldata.vpll2->constraints.apply_uV = true;
omap3stalker_twldata.vpll2->constraints.name = "VDVI";
omap3_pmic_init("twl4030", &omap3stalker_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
@ -494,10 +436,7 @@ static void __init omap3_stalker_init_early(void)
static void __init omap3_stalker_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap3_init_irq();
}
static struct platform_device *omap3_stalker_devices[] __initdata = {
@ -560,5 +499,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
.init_early = omap3_stalker_init_early,
.init_irq = omap3_stalker_init_irq,
.init_machine = omap3_stalker_init,
.timer = &omap_timer,
.timer = &omap3_secure_timer,
MACHINE_END

97
arch/arm/mach-omap2/board-omap3touchbook.c
View File

@ -51,7 +51,6 @@
#include "mux.h"
#include "hsmmc.h"
#include "timer-gp.h"
#include "common-board-devices.h"
#include <asm/setup.h>
@ -114,12 +113,12 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct regulator_consumer_supply touchbook_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply touchbook_vsim_supply = {
.supply = "vmmc_aux",
static struct regulator_consumer_supply touchbook_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct gpio_led gpio_leds[];
@ -137,10 +136,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
touchbook_vmmc1_supply.dev = mmc[0].dev;
touchbook_vsim_supply.dev = mmc[0].dev;
/* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
*/
@ -167,14 +162,18 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = {
.setup = touchbook_twl_gpio_setup,
};
static struct regulator_consumer_supply touchbook_vdac_supply = {
static struct regulator_consumer_supply touchbook_vdac_supply[] = {
{
.supply = "vdac",
.dev = &omap3_touchbook_lcd_device.dev,
},
};
static struct regulator_consumer_supply touchbook_vdvi_supply = {
static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
{
.supply = "vdvi",
.dev = &omap3_touchbook_lcd_device.dev,
},
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@ -188,8 +187,8 @@ static struct regulator_init_data touchbook_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(touchbook_vmmc1_supply),
.consumer_supplies = touchbook_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@ -203,62 +202,15 @@ static struct regulator_init_data touchbook_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vsim_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data touchbook_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vdac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data touchbook_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vdvi_supply,
};
static struct twl4030_usb_data touchbook_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data touchbook_audio_data;
static struct twl4030_codec_data touchbook_codec_data = {
.audio_mclk = 26000000,
.audio = &touchbook_audio_data,
.num_consumer_supplies = ARRAY_SIZE(touchbook_vsim_supply),
.consumer_supplies = touchbook_vsim_supply,
};
static struct twl4030_platform_data touchbook_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &touchbook_usb_data,
.gpio = &touchbook_gpio_data,
.codec = &touchbook_codec_data,
.vmmc1 = &touchbook_vmmc1,
.vsim = &touchbook_vsim,
.vdac = &touchbook_vdac,
.vpll2 = &touchbook_vpll2,
};
static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
@ -270,8 +222,20 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
static int __init omap3_touchbook_i2c_init(void)
{
/* Standard TouchBook bus */
omap3_pmic_init("twl4030", &touchbook_twldata);
omap3_pmic_get_config(&touchbook_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
touchbook_twldata.vdac->num_consumer_supplies =
ARRAY_SIZE(touchbook_vdac_supply);
touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
touchbook_twldata.vpll2->constraints.name = "VDVI";
touchbook_twldata.vpll2->num_consumer_supplies =
ARRAY_SIZE(touchbook_vdvi_supply);
touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
omap3_pmic_init("twl4030", &touchbook_twldata);
/* Additional TouchBook bus */
omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
ARRAY_SIZE(touchBook_i2c_boardinfo));
@ -371,10 +335,7 @@ static void __init omap3_touchbook_init_early(void)
static void __init omap3_touchbook_init_irq(void)
{
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap3_init_irq();
}
static struct platform_device *omap3_touchbook_devices[] __initdata = {
@ -449,5 +410,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
.init_early = omap3_touchbook_init_early,
.init_irq = omap3_touchbook_init_irq,
.init_machine = omap3_touchbook_init,
.timer = &omap_timer,
.timer = &omap3_secure_timer,
MACHINE_END

161
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -41,7 +41,6 @@
#include <plat/usb.h>
#include <plat/mmc.h>
#include <video/omap-panel-generic-dpi.h>
#include "timer-gp.h"
#include "hsmmc.h"
#include "control.h"
@ -155,14 +154,6 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
static struct twl4030_usb_data omap4_usbphy_data = {
.phy_init = omap4430_phy_init,
.phy_exit = omap4430_phy_exit,
.phy_power = omap4430_phy_power,
.phy_set_clock = omap4430_phy_set_clk,
.phy_suspend = omap4430_phy_suspend,
};
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
@ -182,24 +173,16 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
{
.supply = "vmmc",
.dev_name = "omap_hsmmc.0",
},
};
static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
.supply = "vmmc",
.dev_name = "omap_hsmmc.4",
static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
};
static struct regulator_init_data panda_vmmc5 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &omap4_panda_vmmc5_supply,
.num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
.consumer_supplies = omap4_panda_vmmc5_supply,
};
static struct fixed_voltage_config panda_vwlan = {
@ -274,128 +257,8 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
return 0;
}
static struct regulator_init_data omap4_panda_vaux2 = {
.constraints = {
.min_uV = 1200000,
.max_uV = 2800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_panda_vaux3 = {
.constraints = {
.min_uV = 1000000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
/* VMMC1 for MMC1 card */
static struct regulator_init_data omap4_panda_vmmc = {
.constraints = {
.min_uV = 1200000,
.max_uV = 3000000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = omap4_panda_vmmc_supply,
};
static struct regulator_init_data omap4_panda_vpp = {
.constraints = {
.min_uV = 1800000,
.max_uV = 2500000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_panda_vana = {
.constraints = {
.min_uV = 2100000,
.max_uV = 2100000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_panda_vcxio = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_panda_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_panda_vusb = {
.constraints = {
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
};
static struct regulator_init_data omap4_panda_clk32kg = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
};
static struct twl4030_platform_data omap4_panda_twldata = {
.irq_base = TWL6030_IRQ_BASE,
.irq_end = TWL6030_IRQ_END,
/* Regulators */
.vmmc = &omap4_panda_vmmc,
.vpp = &omap4_panda_vpp,
.vana = &omap4_panda_vana,
.vcxio = &omap4_panda_vcxio,
.vdac = &omap4_panda_vdac,
.vusb = &omap4_panda_vusb,
.vaux2 = &omap4_panda_vaux2,
.vaux3 = &omap4_panda_vaux3,
.clk32kg = &omap4_panda_clk32kg,
.usb = &omap4_usbphy_data,
};
/* Panda board uses the common PMIC configuration */
static struct twl4030_platform_data omap4_panda_twldata;
/*
* Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@ -409,6 +272,16 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
static int __init omap4_panda_i2c_init(void)
{
omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
TWL_COMMON_REGULATOR_VDAC |
TWL_COMMON_REGULATOR_VAUX2 |
TWL_COMMON_REGULATOR_VAUX3 |
TWL_COMMON_REGULATOR_VMMC |
TWL_COMMON_REGULATOR_VPP |
TWL_COMMON_REGULATOR_VANA |
TWL_COMMON_REGULATOR_VCXIO |
TWL_COMMON_REGULATOR_VUSB |
TWL_COMMON_REGULATOR_CLK32KG);
omap4_pmic_init("twl6030", &omap4_panda_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
/*
@ -716,5 +589,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
.init_early = omap4_panda_init_early,
.init_irq = gic_init_irq,
.init_machine = omap4_panda_init,
.timer = &omap_timer,
.timer = &omap4_timer,
MACHINE_END

83
arch/arm/mach-omap2/board-overo.c
View File

@ -74,15 +74,16 @@
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/* fixed regulator for ads7846 */
static struct regulator_consumer_supply ads7846_supply =
REGULATOR_SUPPLY("vcc", "spi1.0");
static struct regulator_consumer_supply ads7846_supply[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
static struct regulator_init_data vads7846_regulator = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &ads7846_supply,
.num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
.consumer_supplies = ads7846_supply,
};
static struct fixed_voltage_config vads7846 = {
@ -264,14 +265,6 @@ static struct omap_dss_board_info overo_dss_data = {
.default_device = &overo_dvi_device,
};
static struct regulator_consumer_supply overo_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct mtd_partition overo_nand_partitions[] = {
{
.name = "xloader",
@ -319,8 +312,8 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
static struct regulator_consumer_supply overo_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply overo_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
@ -415,8 +408,6 @@ static int overo_twl_gpio_setup(struct device *dev,
{
omap2_hsmmc_init(mmc);
overo_vmmc1_supply.dev = mmc[0].dev;
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@ -433,10 +424,6 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
.setup = overo_twl_gpio_setup,
};
static struct twl4030_usb_data overo_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct regulator_init_data overo_vmmc1 = {
.constraints = {
.min_uV = 1850000,
@ -447,59 +434,23 @@ static struct regulator_init_data overo_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &overo_vmmc1_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data overo_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &overo_vdda_dac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data overo_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply),
.consumer_supplies = overo_vdds_dsi_supply,
};
static struct twl4030_codec_audio_data overo_audio_data;
static struct twl4030_codec_data overo_codec_data = {
.audio_mclk = 26000000,
.audio = &overo_audio_data,
.num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
.consumer_supplies = overo_vmmc1_supply,
};
static struct twl4030_platform_data overo_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
.gpio = &overo_gpio_data,
.usb = &overo_usb_data,
.codec = &overo_codec_data,
.vmmc1 = &overo_vmmc1,
.vdac = &overo_vdac,
.vpll2 = &overo_vpll2,
};
static int __init overo_i2c_init(void)
{
omap3_pmic_get_config(&overo_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
overo_twldata.vpll2->constraints.name = "VDVI";
omap3_pmic_init("tps65950", &overo_twldata);
/* i2c2 pins are used for gpio */
omap_register_i2c_bus(3, 400, NULL, 0);
@ -615,7 +566,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = overo_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = overo_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

12
arch/arm/mach-omap2/board-rm680.c
View File

@ -79,20 +79,14 @@ static struct twl4030_gpio_platform_data rm680_gpio_data = {
.pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
};
static struct twl4030_usb_data rm680_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_platform_data rm680_twl_data = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
.gpio = &rm680_gpio_data,
.usb = &rm680_usb_data,
/* add rest of the children here */
};
static void __init rm680_i2c_init(void)
{
omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);
@ -163,7 +157,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
.reserve = omap_reserve,
.map_io = rm680_map_io,
.init_early = rm680_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = rm680_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

73
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -288,10 +288,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
.rep = 1,
};
static struct twl4030_madc_platform_data rx51_madc_data = {
.irq_line = 1,
};
/* Enable input logic and pull all lines up when eMMC is on. */
static struct omap_board_mux rx51_mmc2_on_mux[] = {
OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
@ -358,14 +354,17 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
{} /* Terminator */
};
static struct regulator_consumer_supply rx51_vmmc1_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply rx51_vaux3_supply =
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
static struct regulator_consumer_supply rx51_vaux3_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
static struct regulator_consumer_supply rx51_vsim_supply =
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
static struct regulator_consumer_supply rx51_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
};
static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
/* tlv320aic3x analog supplies */
@ -395,10 +394,6 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
REGULATOR_SUPPLY("vdd", "2-0063"),
};
static struct regulator_consumer_supply rx51_vdac_supply[] = {
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
};
static struct regulator_init_data rx51_vaux1 = {
.constraints = {
.name = "V28",
@ -452,8 +447,8 @@ static struct regulator_init_data rx51_vaux3_mmc = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &rx51_vaux3_supply,
.num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
.consumer_supplies = rx51_vaux3_supply,
};
static struct regulator_init_data rx51_vaux4 = {
@ -479,8 +474,8 @@ static struct regulator_init_data rx51_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &rx51_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
.consumer_supplies = rx51_vmmc1_supply,
};
static struct regulator_init_data rx51_vmmc2 = {
@ -511,23 +506,8 @@ static struct regulator_init_data rx51_vsim = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &rx51_vsim_supply,
};
static struct regulator_init_data rx51_vdac = {
.constraints = {
.name = "VDAC",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = rx51_vdac_supply,
.num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
.consumer_supplies = rx51_vsim_supply,
};
static struct regulator_init_data rx51_vio = {
@ -600,10 +580,6 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
.setup = rx51_twlgpio_setup,
};
static struct twl4030_usb_data rx51_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_ins sleep_on_seq[] __initdata = {
/*
* Turn off everything
@ -765,33 +741,27 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
.resource_config = twl4030_rconfig,
};
struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
struct twl4030_vibra_data rx51_vibra_data __initdata = {
.coexist = 0,
};
struct twl4030_codec_data rx51_codec_data __initdata = {
struct twl4030_audio_data rx51_audio_data __initdata = {
.audio_mclk = 26000000,
.vibra = &rx51_vibra_data,
};
static struct twl4030_platform_data rx51_twldata __initdata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.gpio = &rx51_gpio_data,
.keypad = &rx51_kp_data,
.madc = &rx51_madc_data,
.usb = &rx51_usb_data,
.power = &rx51_t2scripts_data,
.codec = &rx51_codec_data,
.audio = &rx51_audio_data,
.vaux1 = &rx51_vaux1,
.vaux2 = &rx51_vaux2,
.vaux4 = &rx51_vaux4,
.vmmc1 = &rx51_vmmc1,
.vsim = &rx51_vsim,
.vdac = &rx51_vdac,
.vio = &rx51_vio,
};
@ -847,6 +817,13 @@ static int __init rx51_i2c_init(void)
rx51_twldata.vaux3 = &rx51_vaux3_cam;
}
rx51_twldata.vmmc2 = &rx51_vmmc2;
omap3_pmic_get_config(&rx51_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
TWL_COMMON_REGULATOR_VDAC);
rx51_twldata.vdac->constraints.apply_uV = true;
rx51_twldata.vdac->constraints.name = "VDAC";
omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));

4
arch/arm/mach-omap2/board-rx51.c
View File

@ -160,7 +160,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
.reserve = rx51_reserve,
.map_io = rx51_map_io,
.init_early = rx51_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = rx51_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

9
arch/arm/mach-omap2/board-ti8168evm.c
View File

@ -33,11 +33,6 @@ static void __init ti8168_init_early(void)
omap2_init_common_devices(NULL, NULL);
}
static void __init ti8168_evm_init_irq(void)
{
omap_init_irq();
}
static void __init ti8168_evm_init(void)
{
omap_serial_init();
@ -56,7 +51,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
.boot_params = 0x80000100,
.map_io = ti8168_evm_map_io,
.init_early = ti8168_init_early,
.init_irq = ti8168_evm_init_irq,
.timer = &omap_timer,
.init_irq = ti816x_init_irq,
.timer = &omap3_timer,
.init_machine = ti8168_evm_init,
MACHINE_END

128
arch/arm/mach-omap2/board-zoom-peripherals.c
View File

@ -105,21 +105,20 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = {
.rep = 1,
};
static struct regulator_consumer_supply zoom_vmmc1_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply zoom_vsim_supply = {
.supply = "vmmc_aux",
static struct regulator_consumer_supply zoom_vsim_supply[] = {
REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct regulator_consumer_supply zoom_vmmc2_supply = {
.supply = "vmmc",
static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
static struct regulator_consumer_supply zoom_vmmc3_supply = {
.supply = "vmmc",
.dev_name = "omap_hsmmc.2",
static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@ -133,8 +132,8 @@ static struct regulator_init_data zoom_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom_vmmc1_supply,
.num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply),
.consumer_supplies = zoom_vmmc1_supply,
};
/* VMMC2 for MMC2 card */
@ -148,8 +147,8 @@ static struct regulator_init_data zoom_vmmc2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom_vmmc2_supply,
.num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply),
.consumer_supplies = zoom_vmmc2_supply,
};
/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@ -163,16 +162,16 @@ static struct regulator_init_data zoom_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom_vsim_supply,
.num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply),
.consumer_supplies = zoom_vsim_supply,
};
static struct regulator_init_data zoom_vmmc3 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom_vmmc3_supply,
.num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply),
.consumer_supplies = zoom_vmmc3_supply,
};
static struct fixed_voltage_config zoom_vwlan = {
@ -227,40 +226,6 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
static struct regulator_consumer_supply zoom_vdda_dac_supply =
REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
static struct regulator_init_data zoom_vpll2 = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies),
.consumer_supplies = zoom_vpll2_supplies,
};
static struct regulator_init_data zoom_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom_vdda_dac_supply,
};
static int zoom_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
@ -270,13 +235,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
* regulators will be set up only *after* we return.
*/
zoom_vmmc1_supply.dev = mmc[0].dev;
zoom_vsim_supply.dev = mmc[0].dev;
zoom_vmmc2_supply.dev = mmc[1].dev;
ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
"lcd enable");
if (ret)
@ -292,26 +250,6 @@ static void zoom2_set_hs_extmute(int mute)
gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
}
static int zoom_batt_table[] = {
/* 0 C*/
30800, 29500, 28300, 27100,
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
4040, 3910, 3790, 3670, 3550
};
static struct twl4030_bci_platform_data zoom_bci_data = {
.battery_tmp_tbl = zoom_batt_table,
.tblsize = ARRAY_SIZE(zoom_batt_table),
};
static struct twl4030_usb_data zoom_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_gpio_platform_data zoom_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
@ -319,41 +257,29 @@ static struct twl4030_gpio_platform_data zoom_gpio_data = {
.setup = zoom_twl_gpio_setup,
};
static struct twl4030_madc_platform_data zoom_madc_data = {
.irq_line = 1,
};
static struct twl4030_codec_audio_data zoom_audio_data;
static struct twl4030_codec_data zoom_codec_data = {
.audio_mclk = 26000000,
.audio = &zoom_audio_data,
};
static struct twl4030_platform_data zoom_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.bci = &zoom_bci_data,
.madc = &zoom_madc_data,
.usb = &zoom_usb_data,
.gpio = &zoom_gpio_data,
.keypad = &zoom_kp_twl4030_data,
.codec = &zoom_codec_data,
.vmmc1 = &zoom_vmmc1,
.vmmc2 = &zoom_vmmc2,
.vsim = &zoom_vsim,
.vpll2 = &zoom_vpll2,
.vdac = &zoom_vdac,
};
static int __init omap_i2c_init(void)
{
omap3_pmic_get_config(&zoom_twldata,
TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
if (machine_is_omap_zoom2()) {
zoom_audio_data.ramp_delay_value = 3; /* 161 ms */
zoom_audio_data.hs_extmute = 1;
zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
struct twl4030_codec_data *codec_data;
codec_data = zoom_twldata.audio->codec;
codec_data->ramp_delay_value = 3; /* 161 ms */
codec_data->hs_extmute = 1;
codec_data->set_hs_extmute = zoom2_set_hs_extmute;
}
omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);

8
arch/arm/mach-omap2/board-zoom.c
View File

@ -137,9 +137,9 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_zoom_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap_zoom_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END
MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@ -147,7 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_zoom_init_early,
.init_irq = omap_init_irq,
.init_irq = omap3_init_irq,
.init_machine = omap_zoom_init,
.timer = &omap_timer,
.timer = &omap3_timer,
MACHINE_END

27
arch/arm/mach-omap2/clock.c
View File

@ -37,6 +37,14 @@
u8 cpu_mask;
/*
* clkdm_control: if true, then when a clock is enabled in the
* hardware, its clockdomain will first be enabled; and when a clock
* is disabled in the hardware, its clockdomain will be disabled
* afterwards.
*/
static bool clkdm_control = true;
/*
* OMAP2+ specific clock functions
*/
@ -99,6 +107,19 @@ void omap2_init_clk_clkdm(struct clk *clk)
}
}
/**
* omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
*
* Prevent the OMAP clock code from calling into the clockdomain code
* when a hardware clock in that clockdomain is enabled or disabled.
* Intended to be called at init time from omap*_clk_init(). No
* return value.
*/
void __init omap2_clk_disable_clkdm_control(void)
{
clkdm_control = false;
}
/**
* omap2_clk_dflt_find_companion - find companion clock to @clk
* @clk: struct clk * to find the companion clock of
@ -268,7 +289,7 @@ void omap2_clk_disable(struct clk *clk)
clk->ops->disable(clk);
}
if (clk->clkdm)
if (clkdm_control && clk->clkdm)
clkdm_clk_disable(clk->clkdm, clk);
if (clk->parent)
@ -308,7 +329,7 @@ int omap2_clk_enable(struct clk *clk)
}
}
if (clk->clkdm) {
if (clkdm_control && clk->clkdm) {
ret = clkdm_clk_enable(clk->clkdm, clk);
if (ret) {
WARN(1, "clock: %s: could not enable clockdomain %s: "
@ -330,7 +351,7 @@ int omap2_clk_enable(struct clk *clk)
return 0;
oce_err3:
if (clk->clkdm)
if (clkdm_control && clk->clkdm)
clkdm_clk_disable(clk->clkdm, clk);
oce_err2:
if (clk->parent)

3
arch/arm/mach-omap2/clock.h
View File

@ -16,6 +16,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
#include <linux/kernel.h>
#include <plat/clock.h>
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
@ -72,6 +74,7 @@ void omap2_clk_disable_unused(struct clk *clk);
#endif
void omap2_init_clk_clkdm(struct clk *clk);
void __init omap2_clk_disable_clkdm_control(void);
/* clkt_clksel.c public functions */
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,

22
arch/arm/mach-omap2/clock2420_data.c
View File

@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
CLK("omapdss_dss", "fck", &dss1_fck, CK_242X),
CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X),
CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),

32
arch/arm/mach-omap2/clock2430_data.c
View File

@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
CLK("omapdss_dss", "fck", &dss1_fck, CK_243X),
CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X),
CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = {
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X),
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X),
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),

44
arch/arm/mach-omap2/clock3xxx_data.c
View File

@ -3289,25 +3289,25 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX),
CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX),
CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),

7
arch/arm/mach-omap2/clock44xx.h
View File

@ -8,13 +8,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
/*
* XXX Missing values for the OMAP4 DPLL_USB
* XXX Missing min_multiplier values for all OMAP4 DPLLs
*/
#define OMAP4430_MAX_DPLL_MULT 2047
#define OMAP4430_MAX_DPLL_DIV 128
int omap4xxx_clk_init(void);
#endif

451
arch/arm/mach-omap2/clock44xx_data.c
View File

@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
static struct clk pad_clks_ck = {
.name = "pad_clks_ck",
.rate = 12000000,
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
.enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
.enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
};
static struct clk pad_slimbus_core_clks_ck = {
@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
static struct clk slimbus_clk = {
.name = "slimbus_clk",
.rate = 12000000,
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
.enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_CLKSEL_ABE,
.enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
};
static struct clk sys_32k_ck = {
@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
};
@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
static struct clk dpll_abe_x2_ck = {
.name = "dpll_abe_x2_ck",
.parent = &dpll_abe_ck,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
};
static const struct clksel_rate div31_1to31_rates[] = {
@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
};
@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
};
static struct clk dpll_core_m7x2_ck = {
@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
};
@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
};
@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.max_multiplier = 2047,
.max_divider = 128,
.min_divider = 1,
};
@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
static struct clk dpll_per_x2_ck = {
.name = "dpll_per_x2_ck",
.parent = &dpll_per_ck,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
};
static const struct clksel dpll_per_m2x2_div[] = {
@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
.enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
};
static struct clk dpll_per_m4x2_ck = {
@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
/* DPLL_UNIPRO */
static struct dpll_data dpll_unipro_dd = {
.mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
.clk_bypass = &sys_clkin_ck,
.clk_ref = &sys_clkin_ck,
.control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
.autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
.idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
.mult_mask = OMAP4430_DPLL_MULT_MASK,
.div1_mask = OMAP4430_DPLL_DIV_MASK,
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.min_divider = 1,
};
static struct clk dpll_unipro_ck = {
.name = "dpll_unipro_ck",
.parent = &sys_clkin_ck,
.dpll_data = &dpll_unipro_dd,
.init = &omap2_init_dpll_parent,
.ops = &clkops_omap3_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
};
static struct clk dpll_unipro_x2_ck = {
.name = "dpll_unipro_x2_ck",
.parent = &dpll_unipro_ck,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_null,
.recalc = &omap3_clkoutx2_recalc,
};
static const struct clksel dpll_unipro_m2x2_div[] = {
{ .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
{ .parent = NULL },
};
static struct clk dpll_unipro_m2x2_ck = {
.name = "dpll_unipro_m2x2_ck",
.parent = &dpll_unipro_x2_ck,
.clksel = dpll_unipro_m2x2_div,
.clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
.clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk usb_hs_clk_div_ck = {
.name = "usb_hs_clk_div_ck",
.parent = &dpll_abe_m3x2_ck,
@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
.max_multiplier = OMAP4430_MAX_DPLL_MULT,
.max_divider = OMAP4430_MAX_DPLL_DIV,
.sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
.max_multiplier = 4095,
.max_divider = 256,
.min_divider = 1,
};
@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
static struct clk dpll_usb_clkdcoldo_ck = {
.name = "dpll_usb_clkdcoldo_ck",
.parent = &dpll_usb_ck,
.ops = &clkops_omap4_dpllmx_ops,
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &followparent_recalc,
};
@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel hsmmc6_fclk_sel[] = {
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk hsmmc6_fclk = {
.name = "hsmmc6_fclk",
.parent = &func_64m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static const struct clksel_rate div2_1to8_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
.recalc = &omap2_clksel_recalc,
};
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk per_abe_24m_fclk = {
.name = "per_abe_24m_fclk",
.parent = &dpll_abe_m2_ck,
.ops = &clkops_null,
.fixed_div = 4,
.recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel per_abe_nc_fclk_div[] = {
{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
{ .parent = NULL },
@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel mcasp2_fclk_sel[] = {
{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk mcasp2_fclk = {
.name = "mcasp2_fclk",
.parent = &func_96m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk mcasp3_fclk = {
.name = "mcasp3_fclk",
.parent = &func_96m_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk ocp_abe_iclk = {
.name = "ocp_abe_iclk",
.parent = &aess_fclk,
.ops = &clkops_null,
.recalc = &followparent_recalc,
};
static struct clk per_abe_24m_fclk = {
.name = "per_abe_24m_fclk",
.parent = &dpll_abe_m2_ck,
.ops = &clkops_null,
.fixed_div = 4,
.recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel pmd_stm_clock_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@ -1694,6 +1605,7 @@ static struct clk gpmc_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.flags = ENABLE_ON_INIT,
.clkdm_name = "l3_2_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
@ -1846,8 +1758,8 @@ static struct clk l3_instr_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
@ -1857,8 +1769,8 @@ static struct clk l3_main_3_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
@ -1995,10 +1907,16 @@ static struct clk mcbsp3_fck = {
.clkdm_name = "abe_clkdm",
};
static const struct clksel mcbsp4_sync_mux_sel[] = {
{ .parent = &func_96m_fclk, .rates = div_1_0_rates },
{ .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
static struct clk mcbsp4_sync_mux_ck = {
.name = "mcbsp4_sync_mux_ck",
.parent = &func_96m_fclk,
.clksel = mcasp2_fclk_sel,
.clksel = mcbsp4_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@ -2077,11 +1995,17 @@ static struct clk mcspi4_fck = {
.recalc = &followparent_recalc,
};
static const struct clksel hsmmc1_fclk_sel[] = {
{ .parent = &func_64m_fclk, .rates = div_1_0_rates },
{ .parent = &func_96m_fclk, .rates = div_1_1_rates },
{ .parent = NULL },
};
/* Merged hsmmc1_fclk into mmc1 */
static struct clk mmc1_fck = {
.name = "mmc1_fck",
.parent = &func_64m_fclk,
.clksel = hsmmc6_fclk_sel,
.clksel = hsmmc1_fclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
@ -2096,7 +2020,7 @@ static struct clk mmc1_fck = {
static struct clk mmc2_fck = {
.name = "mmc2_fck",
.parent = &func_64m_fclk,
.clksel = hsmmc6_fclk_sel,
.clksel = hsmmc1_fclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
@ -2162,8 +2086,8 @@ static struct clk ocp_wp_noc_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
.clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
.clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
@ -2850,19 +2774,39 @@ static struct clk trace_clk_div_ck = {
/* SCRM aux clk nodes */
static const struct clksel auxclk_sel[] = {
static const struct clksel auxclk_src_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
{ .parent = NULL },
};
static struct clk auxclk0_ck = {
.name = "auxclk0_ck",
static const struct clksel_rate div16_1to16_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 3, .val = 2, .flags = RATE_IN_4430 },
{ .div = 4, .val = 3, .flags = RATE_IN_4430 },
{ .div = 5, .val = 4, .flags = RATE_IN_4430 },
{ .div = 6, .val = 5, .flags = RATE_IN_4430 },
{ .div = 7, .val = 6, .flags = RATE_IN_4430 },
{ .div = 8, .val = 7, .flags = RATE_IN_4430 },
{ .div = 9, .val = 8, .flags = RATE_IN_4430 },
{ .div = 10, .val = 9, .flags = RATE_IN_4430 },
{ .div = 11, .val = 10, .flags = RATE_IN_4430 },
{ .div = 12, .val = 11, .flags = RATE_IN_4430 },
{ .div = 13, .val = 12, .flags = RATE_IN_4430 },
{ .div = 14, .val = 13, .flags = RATE_IN_4430 },
{ .div = 15, .val = 14, .flags = RATE_IN_4430 },
{ .div = 16, .val = 15, .flags = RATE_IN_4430 },
{ .div = 0 },
};
static struct clk auxclk0_src_ck = {
.name = "auxclk0_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
.clksel = auxclk_sel,
.clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK0,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@ -2870,12 +2814,29 @@ static struct clk auxclk0_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
static struct clk auxclk1_ck = {
.name = "auxclk1_ck",
static const struct clksel auxclk0_sel[] = {
{ .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
{ .parent = NULL },
};
static struct clk auxclk0_ck = {
.name = "auxclk0_ck",
.parent = &auxclk0_src_ck,
.clksel = auxclk0_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK0,
.clksel_mask = OMAP4_CLKDIV_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk auxclk1_src_ck = {
.name = "auxclk1_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
.clksel = auxclk_sel,
.clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK1,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@ -2883,24 +2844,59 @@ static struct clk auxclk1_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
static struct clk auxclk2_ck = {
.name = "auxclk2_ck",
static const struct clksel auxclk1_sel[] = {
{ .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
{ .parent = NULL },
};
static struct clk auxclk1_ck = {
.name = "auxclk1_ck",
.parent = &auxclk1_src_ck,
.clksel = auxclk1_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK1,
.clksel_mask = OMAP4_CLKDIV_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk auxclk2_src_ck = {
.name = "auxclk2_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
.clksel = auxclk_sel,
.clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK2,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4_SCRM_AUXCLK2,
.enable_bit = OMAP4_ENABLE_SHIFT,
};
static struct clk auxclk3_ck = {
.name = "auxclk3_ck",
static const struct clksel auxclk2_sel[] = {
{ .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
{ .parent = NULL },
};
static struct clk auxclk2_ck = {
.name = "auxclk2_ck",
.parent = &auxclk2_src_ck,
.clksel = auxclk2_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK2,
.clksel_mask = OMAP4_CLKDIV_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk auxclk3_src_ck = {
.name = "auxclk3_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
.clksel = auxclk_sel,
.clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK3,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@ -2908,12 +2904,29 @@ static struct clk auxclk3_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
static struct clk auxclk4_ck = {
.name = "auxclk4_ck",
static const struct clksel auxclk3_sel[] = {
{ .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
{ .parent = NULL },
};
static struct clk auxclk3_ck = {
.name = "auxclk3_ck",
.parent = &auxclk3_src_ck,
.clksel = auxclk3_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK3,
.clksel_mask = OMAP4_CLKDIV_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk auxclk4_src_ck = {
.name = "auxclk4_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
.clksel = auxclk_sel,
.clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK4,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@ -2921,12 +2934,29 @@ static struct clk auxclk4_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
static struct clk auxclk5_ck = {
.name = "auxclk5_ck",
static const struct clksel auxclk4_sel[] = {
{ .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
{ .parent = NULL },
};
static struct clk auxclk4_ck = {
.name = "auxclk4_ck",
.parent = &auxclk4_src_ck,
.clksel = auxclk4_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK4,
.clksel_mask = OMAP4_CLKDIV_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static struct clk auxclk5_src_ck = {
.name = "auxclk5_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
.clksel = auxclk_sel,
.clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK5,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@ -2934,6 +2964,23 @@ static struct clk auxclk5_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
static const struct clksel auxclk5_sel[] = {
{ .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
{ .parent = NULL },
};
static struct clk auxclk5_ck = {
.name = "auxclk5_ck",
.parent = &auxclk5_src_ck,
.clksel = auxclk5_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK5,
.clksel_mask = OMAP4_CLKDIV_MASK,
.ops = &clkops_null,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
};
static const struct clksel auxclkreq_sel[] = {
{ .parent = &auxclk0_ck, .rates = div_1_0_rates },
{ .parent = &auxclk1_ck, .rates = div_1_1_rates },
@ -3077,9 +3124,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
@ -3092,17 +3136,14 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
@ -3114,10 +3155,10 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@ -3138,12 +3179,12 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X),
CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X),
CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X),
CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
CLK(NULL, "iss_fck", &iss_fck, CK_443X),
@ -3154,23 +3195,23 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@ -3204,7 +3245,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
@ -3216,9 +3256,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
@ -3226,17 +3264,32 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@ -3253,6 +3306,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
@ -3270,19 +3324,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)
@ -3296,6 +3340,7 @@ int __init omap4xxx_clk_init(void)
}
clk_init(&omap2_clk_functions);
omap2_clk_disable_clkdm_control();
for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
c++)

224
arch/arm/mach-omap2/clockdomain.c
View File

@ -1,8 +1,8 @@
/*
* OMAP2/3/4 clockdomain framework functions
*
* Copyright (C) 2008-2010 Texas Instruments, Inc.
* Copyright (C) 2008-2010 Nokia Corporation
* Copyright (C) 2008-2011 Texas Instruments, Inc.
* Copyright (C) 2008-2011 Nokia Corporation
*
* Written by Paul Walmsley and Jouni Högander
* Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@ -92,6 +92,8 @@ static int _clkdm_register(struct clockdomain *clkdm)
pwrdm_add_clkdm(pwrdm, clkdm);
spin_lock_init(&clkdm->lock);
pr_debug("clockdomain: registered %s\n", clkdm->name);
return 0;
@ -690,6 +692,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
*/
int clkdm_sleep(struct clockdomain *clkdm)
{
int ret;
unsigned long flags;
if (!clkdm)
return -EINVAL;
@ -704,7 +709,11 @@ int clkdm_sleep(struct clockdomain *clkdm)
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
return arch_clkdm->clkdm_sleep(clkdm);
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
ret = arch_clkdm->clkdm_sleep(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags);
return ret;
}
/**
@ -718,6 +727,9 @@ int clkdm_sleep(struct clockdomain *clkdm)
*/
int clkdm_wakeup(struct clockdomain *clkdm)
{
int ret;
unsigned long flags;
if (!clkdm)
return -EINVAL;
@ -732,7 +744,11 @@ int clkdm_wakeup(struct clockdomain *clkdm)
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
return arch_clkdm->clkdm_wakeup(clkdm);
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
ret = arch_clkdm->clkdm_wakeup(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags);
return ret;
}
/**
@ -747,6 +763,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
*/
void clkdm_allow_idle(struct clockdomain *clkdm)
{
unsigned long flags;
if (!clkdm)
return;
@ -762,8 +780,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
clkdm->name);
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_allow_idle(clkdm);
pwrdm_clkdm_state_switch(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags);
}
/**
@ -777,6 +798,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
*/
void clkdm_deny_idle(struct clockdomain *clkdm)
{
unsigned long flags;
if (!clkdm)
return;
@ -792,11 +815,90 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
spin_lock_irqsave(&clkdm->lock, flags);
clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_deny_idle(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags);
}
/**
* clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
* @clkdm: struct clockdomain *
*
* Returns true if clockdomain @clkdm currently has
* hardware-supervised idle enabled, or false if it does not or if
* @clkdm is NULL. It is only valid to call this function after
* clkdm_init() has been called. This function does not actually read
* bits from the hardware; it instead tests an in-memory flag that is
* changed whenever the clockdomain code changes the auto-idle mode.
*/
bool clkdm_in_hwsup(struct clockdomain *clkdm)
{
bool ret;
unsigned long flags;
/* Clockdomain-to-clock framework interface code */
if (!clkdm)
return false;
spin_lock_irqsave(&clkdm->lock, flags);
ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
spin_unlock_irqrestore(&clkdm->lock, flags);
return ret;
}
/* Clockdomain-to-clock/hwmod framework interface code */
static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
{
unsigned long flags;
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
/*
* For arch's with no autodeps, clkcm_clk_enable
* should be called for every clock instance or hwmod that is
* enabled, so the clkdm can be force woken up.
*/
if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
return 0;
spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags);
pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
return 0;
}
static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
{
unsigned long flags;
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
if (atomic_read(&clkdm->usecount) == 0) {
WARN_ON(1); /* underflow */
return -ERANGE;
}
if (atomic_dec_return(&clkdm->usecount) > 0)
return 0;
spin_lock_irqsave(&clkdm->lock, flags);
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_clkdm_state_switch(clkdm);
spin_unlock_irqrestore(&clkdm->lock, flags);
pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
return 0;
}
/**
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
@ -819,25 +921,10 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
* downstream clocks for debugging purposes?
*/
if (!clkdm || !clk)
if (!clk)
return -EINVAL;
if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
if (atomic_inc_return(&clkdm->usecount) > 1)
return 0;
/* Clockdomain now has one enabled downstream clock */
pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
clk->name);
arch_clkdm->clkdm_clk_enable(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
return 0;
return _clkdm_clk_hwmod_enable(clkdm);
}
/**
@ -850,9 +937,8 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
* clockdomain usecount goes to 0, put the clockdomain to sleep
* (software-supervised mode) or remove the clkdm autodependencies
* (hardware-supervised mode). Returns -EINVAL if passed null
* pointers; -ERANGE if the @clkdm usecount underflows and debugging
* is enabled; or returns 0 upon success or if the clockdomain is in
* hwsup idle mode.
* pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
* upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
@ -861,30 +947,72 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
* downstream clocks for debugging purposes?
*/
if (!clkdm || !clk)
if (!clk)
return -EINVAL;
if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
#ifdef DEBUG
if (atomic_read(&clkdm->usecount) == 0) {
WARN_ON(1); /* underflow */
return -ERANGE;
}
#endif
if (atomic_dec_return(&clkdm->usecount) > 0)
return 0;
/* All downstream clocks of this clockdomain are now disabled */
pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
clk->name);
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_clkdm_state_switch(clkdm);
return 0;
return _clkdm_clk_hwmod_disable(clkdm);
}
/**
* clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
* @clkdm: struct clockdomain *
* @oh: struct omap_hwmod * of the enabled downstream hwmod
*
* Increment the usecount of the clockdomain @clkdm and ensure that it
* is awake before @oh is enabled. Intended to be called by
* module_enable() code.
* If the clockdomain is in software-supervised idle mode, force the
* clockdomain to wake. If the clockdomain is in hardware-supervised idle
* mode, add clkdm-pwrdm autodependencies, to ensure that devices in the
* clockdomain can be read from/written to by on-chip processors.
* Returns -EINVAL if passed null pointers;
* returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream hwmods for debugging purposes?
*/
if (!oh)
return -EINVAL;
return _clkdm_clk_hwmod_enable(clkdm);
}
/**
* clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
* @clkdm: struct clockdomain *
* @oh: struct omap_hwmod * of the disabled downstream hwmod
*
* Decrement the usecount of this clockdomain @clkdm when @oh is
* disabled. Intended to be called by module_disable() code.
* If the clockdomain usecount goes to 0, put the clockdomain to sleep
* (software-supervised mode) or remove the clkdm autodependencies
* (hardware-supervised mode).
* Returns -EINVAL if passed null pointers; -ERANGE if the @clkdm usecount
* underflows; or returns 0 upon success or if the clockdomain is in hwsup
* idle mode.
*/
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
{
/* The clkdm attribute does not exist yet prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream hwmods for debugging purposes?
*/
if (!oh)
return -EINVAL;
return _clkdm_clk_hwmod_disable(clkdm);
}

11
arch/arm/mach-omap2/clockdomain.h
View File

@ -17,9 +17,11 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
#include <linux/init.h>
#include <linux/spinlock.h>
#include "powerdomain.h"
#include <plat/clock.h>
#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
/*
@ -82,6 +84,9 @@ struct clkdm_dep {
const struct omap_chip_id omap_chip;
};
/* Possible flags for struct clockdomain._flags */
#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0)
/**
* struct clockdomain - OMAP clockdomain
* @name: clockdomain name
@ -89,6 +94,7 @@ struct clkdm_dep {
* @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
* @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
* @flags: Clockdomain capability flags
* @_flags: Flags for use only by internal clockdomain code
* @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
* @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
* @cm_inst: (OMAP4 only) CM instance register offset
@ -113,6 +119,7 @@ struct clockdomain {
} pwrdm;
const u16 clktrctrl_mask;
const u8 flags;
u8 _flags;
const u8 dep_bit;
const u8 prcm_partition;
const s16 cm_inst;
@ -122,6 +129,7 @@ struct clockdomain {
const struct omap_chip_id omap_chip;
atomic_t usecount;
struct list_head node;
spinlock_t lock;
};
/**
@ -177,12 +185,15 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
void clkdm_allow_idle(struct clockdomain *clkdm);
void clkdm_deny_idle(struct clockdomain *clkdm);
bool clkdm_in_hwsup(struct clockdomain *clkdm);
int clkdm_wakeup(struct clockdomain *clkdm);
int clkdm_sleep(struct clockdomain *clkdm);
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
extern void __init omap2xxx_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);

6
arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
View File

@ -183,7 +183,8 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
_clkdm_add_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
clkdm_wakeup(clkdm);
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
omap2_clkdm_wakeup(clkdm);
}
return 0;
@ -205,7 +206,8 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
_clkdm_del_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
clkdm_sleep(clkdm);
if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
omap2_clkdm_sleep(clkdm);
}
return 0;

13
arch/arm/mach-omap2/clockdomain44xx.c
View File

@ -95,13 +95,8 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
{
bool hwsup = false;
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
if (!hwsup)
clkdm_wakeup(clkdm);
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
return omap4_clkdm_wakeup(clkdm);
return 0;
}
@ -113,8 +108,8 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
if (!hwsup)
clkdm_sleep(clkdm);
if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
omap4_clkdm_sleep(clkdm);
return 0;
}

126
arch/arm/mach-omap2/clockdomains44xx_data.c
View File

@ -1,11 +1,12 @@
/*
* OMAP4 Clock domains framework
*
* Copyright (C) 2009 Texas Instruments, Inc.
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
@ -32,6 +33,42 @@
/* Static Dependencies for OMAP4 Clock Domains */
static struct clkdm_dep d2d_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep ducati_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
@ -116,42 +153,6 @@ static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{ NULL },
};
static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
.clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
};
static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
{ NULL },
};
static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain mpuss_44xx_clkdm = {
.name = "mpuss_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.prcm_partition = OMAP4430_CM1_PARTITION,
.cm_inst = OMAP4430_CM1_MPU_INST,
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
.wkdep_srcs = mpuss_wkup_sleep_deps,
.sleepdep_srcs = mpuss_wkup_sleep_deps,
static struct clockdomain d2d_44xx_clkdm = {
.name = "d2d_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
.wkdep_srcs = d2d_wkup_sleep_deps,
.sleepdep_srcs = d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain mpu_44xx_clkdm = {
.name = "mpuss_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.prcm_partition = OMAP4430_CM1_PARTITION,
.cm_inst = OMAP4430_CM1_MPU_INST,
.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
.wkdep_srcs = mpu_wkup_sleep_deps,
.sleepdep_srcs = mpu_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_2_44xx_clkdm = {
.name = "l3_2_clkdm",
.pwrdm = { .name = "core_pwrdm" },
@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain l3_d2d_44xx_clkdm = {
.name = "l3_d2d_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = OMAP4430_CM2_PARTITION,
.cm_inst = OMAP4430_CM2_CORE_INST,
.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
.wkdep_srcs = l3_d2d_wkup_sleep_deps,
.sleepdep_srcs = l3_d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static struct clockdomain iss_44xx_clkdm = {
.name = "iss_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap44xx[] __initdata = {
&l4_cefuse_44xx_clkdm,
&l4_cfg_44xx_clkdm,
@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
&abe_44xx_clkdm,
&l3_instr_44xx_clkdm,
&l3_init_44xx_clkdm,
&mpuss_44xx_clkdm,
&d2d_44xx_clkdm,
&mpu0_44xx_clkdm,
&mpu1_44xx_clkdm,
&l3_emif_44xx_clkdm,
&l4_ao_44xx_clkdm,
&ducati_44xx_clkdm,
&mpu_44xx_clkdm,
&l3_2_44xx_clkdm,
&l3_1_44xx_clkdm,
&l3_d2d_44xx_clkdm,
&iss_44xx_clkdm,
&l3_dss_44xx_clkdm,
&l4_wkup_44xx_clkdm,
&emu_sys_44xx_clkdm,
&l3_dma_44xx_clkdm,
NULL,
NULL
};
void __init omap44xx_clockdomains_init(void)

623
arch/arm/mach-omap2/cm-regbits-44xx.h
View File

File diff suppressed because it is too large Load Diff

64
arch/arm/mach-omap2/cm1_44xx.h
View File

@ -1,7 +1,7 @@
/*
* OMAP44xx CM1 instance offset macros
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
@ -41,9 +41,9 @@
#define OMAP4430_CM1_INSTR_INST 0x0f00
/* CM1 clockdomain register offsets (from instance start) */
#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
/* CM1 */
@ -82,8 +82,8 @@
#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
@ -98,8 +98,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
@ -116,8 +116,8 @@
#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
@ -134,8 +134,8 @@
#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
@ -154,8 +154,8 @@
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
@ -217,42 +217,6 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
/* CM1.RESTORE_CM1 register offsets */
#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
/* Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);

73
arch/arm/mach-omap2/cm2_44xx.h
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@ -1,7 +1,7 @@
/*
* OMAP44xx CM2 instance offset macros
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
@ -40,9 +40,9 @@
#define OMAP4430_CM2_CAM_INST 0x1000
#define OMAP4430_CM2_DSS_INST 0x1100
#define OMAP4430_CM2_GFX_INST 0x1200
#define OMAP4430_CM2_L3INIT_INST 0x1300
#define OMAP4430_CM2_L3INIT_INST 0x1300
#define OMAP4430_CM2_L4PER_INST 0x1400
#define OMAP4430_CM2_CEFUSE_INST 0x1600
#define OMAP4430_CM2_CEFUSE_INST 0x1600
#define OMAP4430_CM2_RESTORE_INST 0x1e00
#define OMAP4430_CM2_INSTR_INST 0x1f00
@ -65,7 +65,6 @@
#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
/* CM2 */
/* CM2.OCP_SOCKET_CM2 register offsets */
@ -121,8 +120,8 @@
#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
@ -135,8 +134,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
@ -151,8 +150,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
/* CM2.ALWAYS_ON_CM2 register offsets */
#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
@ -227,8 +226,8 @@
#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528
#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
@ -450,56 +449,6 @@
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
/* CM2.RESTORE_CM2 register offsets */
#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
/* Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);

8
arch/arm/mach-omap2/cm44xx.h
View File

@ -1,7 +1,7 @@
/*
* OMAP4 Clock Management (CM) definitions
*
* Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2011 Texas Instruments, Inc.
* Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
@ -23,10 +23,4 @@
#define OMAP4_CM_CLKSTCTRL 0x0000
#define OMAP4_CM_STATICDEP 0x0004
/* Function prototypes */
# ifndef __ASSEMBLER__
extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
# endif
#endif

152
arch/arm/mach-omap2/cminst44xx.c
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@ -2,6 +2,7 @@
* OMAP4 CM instance functions
*
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@ -32,6 +33,22 @@
#include "prm44xx.h"
#include "prcm_mpu44xx.h"
/*
* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
*
* 0x0 func: Module is fully functional, including OCP
* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
* abortion
* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
* using separate functional clock
* 0x3 disabled: Module is disabled and cannot be accessed
*
*/
#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
#define CLKCTRL_IDLEST_INTRANSITION 0x1
#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
#define CLKCTRL_IDLEST_DISABLED 0x3
static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
[OMAP4430_INVALID_PRCM_PARTITION] = 0,
[OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
@ -41,6 +58,48 @@ static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
[OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
};
/* Private functions */
/**
* _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
* bit 0.
*/
static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
v &= OMAP4430_IDLEST_MASK;
v >>= OMAP4430_IDLEST_SHIFT;
return v;
}
/**
* _is_module_ready - can module registers be accessed without causing an abort?
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
*/
static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
u32 v;
v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
}
/* Public functions */
/* Read a register in a CM instance */
u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{
@ -200,36 +259,93 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
*/
/**
* omap4_cm_wait_module_ready - wait for a module to be in 'func' state
* @clkctrl_reg: CLKCTRL module address
* omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Wait for the module IDLEST to be functional. If the idle state is in any
* the non functional state (trans, idle or disabled), module and thus the
* sysconfig cannot be accessed and will probably lead to an "imprecise
* external abort"
*
* Module idle state:
* 0x0 func: Module is fully functional, including OCP
* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
* abortion
* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
* using separate functional clock
* 0x3 disabled: Module is disabled and cannot be accessed
*
*/
int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
int i = 0;
if (!clkctrl_reg)
if (!clkctrl_offs)
return 0;
omap_test_timeout((
((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
(((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
OMAP4430_IDLEST_SHIFT) == 0x2)),
MAX_MODULE_READY_TIME, i);
omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
MAX_MODULE_READY_TIME, i);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}
/**
* omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
* state
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Wait for the module IDLEST to be disabled. Some PRCM transition,
* like reset assertion or parent clock de-activation must wait the
* module to be fully disabled.
*/
int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
if (!clkctrl_offs)
return 0;
omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
CLKCTRL_IDLEST_DISABLED),
MAX_MODULE_READY_TIME, i);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}
/**
* omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
* @mode: Module mode (SW or HW)
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* No return value.
*/
void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
u32 v;
v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
v &= ~OMAP4430_MODULEMODE_MASK;
v |= mode << OMAP4430_MODULEMODE_SHIFT;
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
}
/**
* omap4_cminst_module_disable - Disable the module inside CLKCTRL
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* No return value.
*/
void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs)
{
u32 v;
v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
v &= ~OMAP4430_MODULEMODE_MASK;
omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
}

10
arch/arm/mach-omap2/cminst44xx.h
View File

@ -17,6 +17,14 @@ extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs);
extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
u16 clkctrl_offs);
/*
* In an ideal world, we would not export these low-level functions,
* but this will probably take some time to fix properly
@ -32,6 +40,4 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
u32 mask);
extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
#endif

27
arch/arm/mach-omap2/common-board-devices.c
View File

@ -20,36 +20,15 @@
*
*/
#include <linux/i2c.h>
#include <linux/i2c/twl.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <plat/i2c.h>
#include <plat/mcspi.h>
#include <plat/nand.h>
#include "common-board-devices.h"
static struct i2c_board_info __initdata pmic_i2c_board_info = {
.addr = 0x48,
.flags = I2C_CLIENT_WAKE,
};
void __init omap_pmic_init(int bus, u32 clkrate,
const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data)
{
strncpy(pmic_i2c_board_info.type, pmic_type,
sizeof(pmic_i2c_board_info.type));
pmic_i2c_board_info.irq = pmic_irq;
pmic_i2c_board_info.platform_data = pmic_data;
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
}
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
@ -115,9 +94,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
#endif
#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
static struct omap_nand_platform_data nand_data = {
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
};
static struct omap_nand_platform_data nand_data;
void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
int nr_parts)
@ -148,7 +125,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
nand_data.cs = nandcs;
nand_data.parts = parts;
nand_data.nr_parts = nr_parts;
nand_data.options = options;
nand_data.devsize = options;
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
if (gpmc_nand_init(&nand_data) < 0)

26
arch/arm/mach-omap2/common-board-devices.h
View File

@ -1,33 +1,11 @@
#ifndef __OMAP_COMMON_BOARD_DEVICES__
#define __OMAP_COMMON_BOARD_DEVICES__
#include "twl-common.h"
#define NAND_BLOCK_SIZE SZ_128K
struct twl4030_platform_data;
struct mtd_partition;
void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
struct twl4030_platform_data *pmic_data);
static inline void omap2_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
}
static inline void omap3_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
}
static inline void omap4_pmic_init(const char *pmic_type,
struct twl4030_platform_data *pmic_data)
{
/* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
}
struct ads7846_platform_data;
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,

10
arch/arm/mach-omap2/gpmc-nand.c
View File

@ -20,8 +20,6 @@
#include <plat/board.h>
#include <plat/gpmc.h>
static struct omap_nand_platform_data *gpmc_nand_data;
static struct resource gpmc_nand_resource = {
.flags = IORESOURCE_MEM,
};
@ -33,7 +31,7 @@ static struct platform_device gpmc_nand_device = {
.resource = &gpmc_nand_resource,
};
static int omap2_nand_gpmc_retime(void)
static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
{
struct gpmc_timings t;
int err;
@ -83,13 +81,11 @@ static int omap2_nand_gpmc_retime(void)
return 0;
}
int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
{
int err = 0;
struct device *dev = &gpmc_nand_device.dev;
gpmc_nand_data = _nand_data;
gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
@ -100,7 +96,7 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
}
/* Set timings in GPMC */
err = omap2_nand_gpmc_retime();
err = omap2_nand_gpmc_retime(gpmc_nand_data);
if (err < 0) {
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
return err;

68
arch/arm/mach-omap2/i2c.c
View File

@ -21,9 +21,19 @@
#include <plat/cpu.h>
#include <plat/i2c.h>
#include <plat/common.h>
#include <plat/omap_hwmod.h>
#include "mux.h"
/* In register I2C_CON, Bit 15 is the I2C enable bit */
#define I2C_EN BIT(15)
#define OMAP2_I2C_CON_OFFSET 0x24
#define OMAP4_I2C_CON_OFFSET 0xA4
/* Maximum microseconds to wait for OMAP module to softreset */
#define MAX_MODULE_SOFTRESET_WAIT 10000
void __init omap2_i2c_mux_pins(int bus_id)
{
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
/**
* omap_i2c_reset - reset the omap i2c module.
* @oh: struct omap_hwmod *
*
* The i2c moudle in omap2, omap3 had a special sequence to reset. The
* sequence is:
* - Disable the I2C.
* - Write to SOFTRESET bit.
* - Enable the I2C.
* - Poll on the RESETDONE bit.
* The sequence is implemented in below function. This is called for 2420,
* 2430 and omap3.
*/
int omap_i2c_reset(struct omap_hwmod *oh)
{
u32 v;
u16 i2c_con;
int c = 0;
if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
i2c_con = OMAP4_I2C_CON_OFFSET;
} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
i2c_con = OMAP2_I2C_CON_OFFSET;
} else {
WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
oh->name);
return -EINVAL;
}
/* Disable I2C */
v = omap_hwmod_read(oh, i2c_con);
v &= ~I2C_EN;
omap_hwmod_write(v, oh, i2c_con);
/* Write to the SOFTRESET bit */
omap_hwmod_softreset(oh);
/* Enable I2C */
v = omap_hwmod_read(oh, i2c_con);
v |= I2C_EN;
omap_hwmod_write(v, oh, i2c_con);
/* Poll on RESETDONE bit */
omap_test_timeout((omap_hwmod_read(oh,
oh->class->sysc->syss_offs)
& SYSS_RESETDONE_MASK),
MAX_MODULE_SOFTRESET_WAIT, c);
if (c == MAX_MODULE_SOFTRESET_WAIT)
pr_warning("%s: %s: softreset failed (waited %d usec)\n",
__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
else
pr_debug("%s: %s: softreset in %d usec\n", __func__,
oh->name, c);
return 0;
}

17
arch/arm/mach-omap2/io.c
View File

@ -333,23 +333,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
/* See irq.c, omap4-common.c and entry-macro.S */
void __iomem *omap_irq_base;
/*
* Initialize asm_irq_base for entry-macro.S
*/
static inline void omap_irq_base_init(void)
{
if (cpu_is_omap24xx())
omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
else if (cpu_is_omap34xx())
omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
else if (cpu_is_omap44xx())
omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
else
pr_err("Could not initialize omap_irq_base\n");
}
void __init omap2_init_common_infrastructure(void)
{
u8 postsetup_state;
@ -422,7 +408,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
_omap2_init_reprogram_sdrc();
}
omap_irq_base_init();
}
/*

32
arch/arm/mach-omap2/irq.c
View File

@ -141,25 +141,20 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
void __init omap_init_irq(void)
static void __init omap_init_irq(u32 base, int nr_irqs)
{
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
int i, j;
omap_irq_base = ioremap(base, SZ_4K);
if (WARN_ON(!omap_irq_base))
return;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
unsigned long base = 0;
struct omap_irq_bank *bank = irq_banks + i;
if (cpu_is_omap24xx())
base = OMAP24XX_IC_BASE;
else if (cpu_is_omap34xx())
base = OMAP34XX_IC_BASE;
BUG_ON(!base);
if (cpu_is_ti816x())
bank->nr_irqs = 128;
bank->nr_irqs = nr_irqs;
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
@ -181,6 +176,21 @@ void __init omap_init_irq(void)
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}
void __init omap2_init_irq(void)
{
omap_init_irq(OMAP24XX_IC_BASE, 96);
}
void __init omap3_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 96);
}
void __init ti816x_init_irq(void)
{
omap_init_irq(OMAP34XX_IC_BASE, 128);
}
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

10
arch/arm/mach-omap2/omap4-common.c
View File

@ -19,6 +19,8 @@
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/irqs.h>
#include <mach/hardware.h>
#include <mach/omap4-common.h>
@ -31,17 +33,15 @@ void __iomem *gic_dist_base_addr;
void __init gic_init_irq(void)
{
void __iomem *gic_cpu_base;
/* Static mapping, never released */
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
BUG_ON(!gic_dist_base_addr);
/* Static mapping, never released */
gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
BUG_ON(!gic_cpu_base);
omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
BUG_ON(!omap_irq_base);
gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}
#ifdef CONFIG_CACHE_L2X0

404
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2,6 +2,7 @@
* omap_hwmod implementation for OMAP2/3/4
*
* Copyright (C) 2009-2011 Nokia Corporation
* Copyright (C) 2011 Texas Instruments, Inc.
*
* Paul Walmsley, Benoît Cousson, Kevin Hilman
*
@ -145,9 +146,10 @@
#include <plat/prcm.h>
#include "cm2xxx_3xxx.h"
#include "cm44xx.h"
#include "cminst44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
#include "prminst44xx.h"
#include "mux.h"
/* Maximum microseconds to wait for OMAP module to softreset */
@ -387,11 +389,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
*/
static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
{
u32 wakeup_mask;
if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL;
if (!oh->class->sysc->sysc_fields) {
@ -399,12 +400,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
return -EINVAL;
}
wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
*v |= wakeup_mask;
if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
*v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
@ -422,11 +424,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
*/
static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
{
u32 wakeup_mask;
if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL;
if (!oh->class->sysc->sysc_fields) {
@ -434,12 +435,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
return -EINVAL;
}
wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
*v &= ~wakeup_mask;
if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
*v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
@ -677,6 +679,125 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
}
}
/**
* _enable_module - enable CLKCTRL modulemode on OMAP4
* @oh: struct omap_hwmod *
*
* Enables the PRCM module mode related to the hwmod @oh.
* No return value.
*/
static void _enable_module(struct omap_hwmod *oh)
{
/* The module mode does not exist prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return;
if (!oh->clkdm || !oh->prcm.omap4.modulemode)
return;
pr_debug("omap_hwmod: %s: _enable_module: %d\n",
oh->name, oh->prcm.omap4.modulemode);
omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
oh->clkdm->prcm_partition,
oh->clkdm->cm_inst,
oh->clkdm->clkdm_offs,
oh->prcm.omap4.clkctrl_offs);
}
/**
* _disable_module - enable CLKCTRL modulemode on OMAP4
* @oh: struct omap_hwmod *
*
* Disable the PRCM module mode related to the hwmod @oh.
* No return value.
*/
static void _disable_module(struct omap_hwmod *oh)
{
/* The module mode does not exist prior OMAP4 */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return;
if (!oh->clkdm || !oh->prcm.omap4.modulemode)
return;
pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
omap4_cminst_module_disable(oh->clkdm->prcm_partition,
oh->clkdm->cm_inst,
oh->clkdm->clkdm_offs,
oh->prcm.omap4.clkctrl_offs);
}
/**
* _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
* @oh: struct omap_hwmod *oh
*
* Count and return the number of MPU IRQs associated with the hwmod
* @oh. Used to allocate struct resource data. Returns 0 if @oh is
* NULL.
*/
static int _count_mpu_irqs(struct omap_hwmod *oh)
{
struct omap_hwmod_irq_info *ohii;
int i = 0;
if (!oh || !oh->mpu_irqs)
return 0;
do {
ohii = &oh->mpu_irqs[i++];
} while (ohii->irq != -1);
return i;
}
/**
* _count_sdma_reqs - count the number of SDMA request lines associated with @oh
* @oh: struct omap_hwmod *oh
*
* Count and return the number of SDMA request lines associated with
* the hwmod @oh. Used to allocate struct resource data. Returns 0
* if @oh is NULL.
*/
static int _count_sdma_reqs(struct omap_hwmod *oh)
{
struct omap_hwmod_dma_info *ohdi;
int i = 0;
if (!oh || !oh->sdma_reqs)
return 0;
do {
ohdi = &oh->sdma_reqs[i++];
} while (ohdi->dma_req != -1);
return i;
}
/**
* _count_ocp_if_addr_spaces - count the number of address space entries for @oh
* @oh: struct omap_hwmod *oh
*
* Count and return the number of address space ranges associated with
* the hwmod @oh. Used to allocate struct resource data. Returns 0
* if @oh is NULL.
*/
static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
{
struct omap_hwmod_addr_space *mem;
int i = 0;
if (!os || !os->addr)
return 0;
do {
mem = &os->addr[i++];
} while (mem->pa_start != mem->pa_end);
return i;
}
/**
* _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
* @oh: struct omap_hwmod *
@ -722,8 +843,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
{
struct omap_hwmod_ocp_if *os;
struct omap_hwmod_addr_space *mem;
int i;
int found = 0;
int i = 0, found = 0;
void __iomem *va_start;
if (!oh || oh->slaves_cnt == 0)
@ -731,12 +851,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
os = oh->slaves[index];
for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
if (mem->flags & ADDR_TYPE_RT) {
if (!os->addr)
return NULL;
do {
mem = &os->addr[i++];
if (mem->flags & ADDR_TYPE_RT)
found = 1;
break;
}
}
} while (!found && mem->pa_start != mem->pa_end);
if (found) {
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
@ -781,8 +903,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
}
if (sf & SYSC_HAS_MIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
idlemode = HWMOD_IDLEMODE_NO;
} else {
if (sf & SYSC_HAS_ENAWAKEUP)
_enable_wakeup(oh, &v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
else
idlemode = HWMOD_IDLEMODE_SMART;
}
_set_master_standbymode(oh, idlemode, &v);
}
@ -840,8 +970,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
}
if (sf & SYSC_HAS_MIDLEMODE) {
idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
idlemode = HWMOD_IDLEMODE_FORCE;
} else {
if (sf & SYSC_HAS_ENAWAKEUP)
_enable_wakeup(oh, &v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
idlemode = HWMOD_IDLEMODE_SMART_WKUP;
else
idlemode = HWMOD_IDLEMODE_SMART;
}
_set_master_standbymode(oh, idlemode, &v);
}
@ -903,9 +1041,40 @@ static struct omap_hwmod *_lookup(const char *name)
return oh;
}
/**
* _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
* @oh: struct omap_hwmod *
*
* Convert a clockdomain name stored in a struct omap_hwmod into a
* clockdomain pointer, and save it into the struct omap_hwmod.
* return -EINVAL if clkdm_name does not exist or if the lookup failed.
*/
static int _init_clkdm(struct omap_hwmod *oh)
{
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
if (!oh->clkdm_name) {
pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
return -EINVAL;
}
oh->clkdm = clkdm_lookup(oh->clkdm_name);
if (!oh->clkdm) {
pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
oh->name, oh->clkdm_name);
return -EINVAL;
}
pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
oh->name, oh->clkdm_name);
return 0;
}
/**
* _init_clocks - clk_get() all clocks associated with this hwmod
* _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
* well the clockdomain.
* @oh: struct omap_hwmod *
* @data: not used; pass NULL
*
@ -925,9 +1094,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
ret |= _init_main_clk(oh);
ret |= _init_interface_clks(oh);
ret |= _init_opt_clks(oh);
ret |= _init_clkdm(oh);
if (!ret)
oh->_state = _HWMOD_STATE_CLKS_INITED;
else
pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
return ret;
}
@ -939,7 +1111,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
* Wait for a module @oh to leave slave idle. Returns 0 if the module
* does not have an IDLEST bit or if the module successfully leaves
* slave idle; otherwise, pass along the return value of the
* appropriate *_cm_wait_module_ready() function.
* appropriate *_cm*_wait_module_ready() function.
*/
static int _wait_target_ready(struct omap_hwmod *oh)
{
@ -966,7 +1138,13 @@ static int _wait_target_ready(struct omap_hwmod *oh)
oh->prcm.omap2.idlest_reg_id,
oh->prcm.omap2.idlest_idle_bit);
} else if (cpu_is_omap44xx()) {
ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
if (!oh->clkdm)
return -EINVAL;
ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
oh->clkdm->cm_inst,
oh->clkdm->clkdm_offs,
oh->prcm.omap4.clkctrl_offs);
} else {
BUG();
};
@ -974,6 +1152,36 @@ static int _wait_target_ready(struct omap_hwmod *oh)
return ret;
}
/**
* _wait_target_disable - wait for a module to be disabled
* @oh: struct omap_hwmod *
*
* Wait for a module @oh to enter slave idle. Returns 0 if the module
* does not have an IDLEST bit or if the module successfully enters
* slave idle; otherwise, pass along the return value of the
* appropriate *_cm*_wait_module_idle() function.
*/
static int _wait_target_disable(struct omap_hwmod *oh)
{
/* TODO: For now just handle OMAP4+ */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
if (!oh)
return -EINVAL;
if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
return 0;
if (oh->flags & HWMOD_NO_IDLEST)
return 0;
return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
oh->clkdm->cm_inst,
oh->clkdm->clkdm_offs,
oh->prcm.omap4.clkctrl_offs);
}
/**
* _lookup_hardreset - fill register bit info for this hwmod/reset line
* @oh: struct omap_hwmod *
@ -1030,8 +1238,10 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
ohri.rst_shift);
else if (cpu_is_omap44xx())
return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
ohri.rst_shift);
return omap4_prminst_assert_hardreset(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs);
else
return -EINVAL;
}
@ -1066,8 +1276,10 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
if (ohri.st_shift)
pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
oh->name, name);
ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
ohri.rst_shift);
ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs);
} else {
return -EINVAL;
}
@ -1102,8 +1314,10 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
ohri.st_shift);
} else if (cpu_is_omap44xx()) {
return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
ohri.rst_shift);
return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.rstctrl_offs);
} else {
return -EINVAL;
}
@ -1223,6 +1437,9 @@ static int _reset(struct omap_hwmod *oh)
static int _enable(struct omap_hwmod *oh)
{
int r;
int hwsup = 0;
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
if (oh->_state != _HWMOD_STATE_INITIALIZED &&
oh->_state != _HWMOD_STATE_IDLE &&
@ -1232,11 +1449,10 @@ static int _enable(struct omap_hwmod *oh)
return -EINVAL;
}
pr_debug("omap_hwmod: %s: enabling\n", oh->name);
/*
* If an IP contains only one HW reset line, then de-assert it in order
* to allow to enable the clocks. Otherwise the PRCM will return
* to allow the module state transition. Otherwise the PRCM will return
* Intransition status, and the init will failed.
*/
if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
@ -1250,10 +1466,34 @@ static int _enable(struct omap_hwmod *oh)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
_add_initiator_dep(oh, mpu_oh);
if (oh->clkdm) {
/*
* A clockdomain must be in SW_SUP before enabling
* completely the module. The clockdomain can be set
* in HW_AUTO only when the module become ready.
*/
hwsup = clkdm_in_hwsup(oh->clkdm);
r = clkdm_hwmod_enable(oh->clkdm, oh);
if (r) {
WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
oh->name, oh->clkdm->name, r);
return r;
}
}
_enable_clocks(oh);
_enable_module(oh);
r = _wait_target_ready(oh);
if (!r) {
/*
* Set the clockdomain to HW_AUTO only if the target is ready,
* assuming that the previous state was HW_AUTO
*/
if (oh->clkdm && hwsup)
clkdm_allow_idle(oh->clkdm);
oh->_state = _HWMOD_STATE_ENABLED;
/* Access the sysconfig only if the target is ready */
@ -1266,6 +1506,9 @@ static int _enable(struct omap_hwmod *oh)
_disable_clocks(oh);
pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
oh->name, r);
if (oh->clkdm)
clkdm_hwmod_disable(oh->clkdm, oh);
}
return r;
@ -1281,18 +1524,33 @@ static int _enable(struct omap_hwmod *oh)
*/
static int _idle(struct omap_hwmod *oh)
{
int ret;
pr_debug("omap_hwmod: %s: idling\n", oh->name);
if (oh->_state != _HWMOD_STATE_ENABLED) {
WARN(1, "omap_hwmod: %s: idle state can only be entered from "
"enabled state\n", oh->name);
return -EINVAL;
}
pr_debug("omap_hwmod: %s: idling\n", oh->name);
if (oh->class->sysc)
_idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh);
_disable_module(oh);
ret = _wait_target_disable(oh);
if (ret)
pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
oh->name);
/*
* The module must be in idle mode before disabling any parents
* clocks. Otherwise, the parent clock might be disabled before
* the module transition is done, and thus will prevent the
* transition to complete properly.
*/
_disable_clocks(oh);
if (oh->clkdm)
clkdm_hwmod_disable(oh->clkdm, oh);
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic)
@ -1374,24 +1632,34 @@ static int _shutdown(struct omap_hwmod *oh)
}
}
if (oh->class->sysc)
if (oh->class->sysc) {
if (oh->_state == _HWMOD_STATE_IDLE)
_enable(oh);
_shutdown_sysc(oh);
/*
* If an IP contains only one HW reset line, then assert it
* before disabling the clocks and shutting down the IP.
*/
if (oh->rst_lines_cnt == 1)
_assert_hardreset(oh, oh->rst_lines[0].name);
}
/* clocks and deps are already disabled in idle */
if (oh->_state == _HWMOD_STATE_ENABLED) {
_del_initiator_dep(oh, mpu_oh);
/* XXX what about the other system initiators here? dma, dsp */
_disable_module(oh);
ret = _wait_target_disable(oh);
if (ret)
pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
oh->name);
_disable_clocks(oh);
if (oh->clkdm)
clkdm_hwmod_disable(oh->clkdm, oh);
}
/* XXX Should this code also force-disable the optional clocks? */
/*
* If an IP contains only one HW reset line, then assert it
* after disabling the clocks and before shutting down the IP.
*/
if (oh->rst_lines_cnt == 1)
_assert_hardreset(oh, oh->rst_lines[0].name);
/* Mux pins to safe mode or use populated off mode values */
if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
@ -1561,6 +1829,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
__raw_writel(v, oh->_mpu_rt_va + reg_offs);
}
/**
* omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
* @oh: struct omap_hwmod *
*
* This is a public function exposed to drivers. Some drivers may need to do
* some settings before and after resetting the device. Those drivers after
* doing the necessary settings could use this function to start a reset by
* setting the SYSCONFIG.SOFTRESET bit.
*/
int omap_hwmod_softreset(struct omap_hwmod *oh)
{
u32 v;
int ret;
if (!oh || !(oh->_sysc_cache))
return -EINVAL;
v = oh->_sysc_cache;
ret = _set_softreset(oh, &v);
if (ret)
goto error;
_write_sysconfig(v, oh);
error:
return ret;
}
/**
* omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
* @oh: struct omap_hwmod *
@ -1685,9 +1980,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
return 0;
oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
if (!oh->_mpu_rt_va)
pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
__func__, oh->name);
return 0;
}
@ -1939,10 +2231,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
{
int ret, i;
ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
for (i = 0; i < oh->slaves_cnt; i++)
ret += oh->slaves[i]->addr_cnt;
ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
return ret;
}
@ -1959,12 +2251,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
*/
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
{
int i, j;
int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
int r = 0;
/* For each IRQ, DMA, memory area, fill in array.*/
for (i = 0; i < oh->mpu_irqs_cnt; i++) {
mpu_irqs_cnt = _count_mpu_irqs(oh);
for (i = 0; i < mpu_irqs_cnt; i++) {
(res + r)->name = (oh->mpu_irqs + i)->name;
(res + r)->start = (oh->mpu_irqs + i)->irq;
(res + r)->end = (oh->mpu_irqs + i)->irq;
@ -1972,7 +2265,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
r++;
}
for (i = 0; i < oh->sdma_reqs_cnt; i++) {
sdma_reqs_cnt = _count_sdma_reqs(oh);
for (i = 0; i < sdma_reqs_cnt; i++) {
(res + r)->name = (oh->sdma_reqs + i)->name;
(res + r)->start = (oh->sdma_reqs + i)->dma_req;
(res + r)->end = (oh->sdma_reqs + i)->dma_req;
@ -1982,10 +2276,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
for (i = 0; i < oh->slaves_cnt; i++) {
struct omap_hwmod_ocp_if *os;
int addr_cnt;
os = oh->slaves[i];
addr_cnt = _count_ocp_if_addr_spaces(os);
for (j = 0; j < os->addr_cnt; j++) {
for (j = 0; j < addr_cnt; j++) {
(res + r)->name = (os->addr + j)->name;
(res + r)->start = (os->addr + j)->pa_start;
(res + r)->end = (os->addr + j)->pa_end;

841
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

File diff suppressed because it is too large Load Diff

917
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

File diff suppressed because it is too large Load Diff

173
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c Normal file
View File

@ -0,0 +1,173 @@
/*
* omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
*
* Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
* XXX these should be marked initdata for multi-OMAP kernels
*/
#include <asm/sizes.h>
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include "omap_hwmod_common_data.h"
struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
{
.pa_start = 0x4809c000,
.pa_end = 0x4809c1ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
{
.pa_start = 0x480b4000,
.pa_end = 0x480b41ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
{
.pa_start = 0x48070000,
.pa_end = 0x48070000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
{
.pa_start = 0x48072000,
.pa_end = 0x48072000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_addrs[] = {
{
.pa_start = 0x48050000,
.pa_end = 0x48050000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
{
.pa_start = 0x48050400,
.pa_end = 0x48050400 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
{
.pa_start = 0x48050800,
.pa_end = 0x48050800 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
{
.pa_start = 0x48050C00,
.pa_end = 0x48050C00 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
{
.pa_start = 0x48086000,
.pa_end = 0x48086000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
{
.pa_start = 0x48088000,
.pa_end = 0x48088000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
{
.pa_start = 0x4808a000,
.pa_end = 0x4808a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
{
.pa_start = 0x48098000,
.pa_end = 0x48098000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
{
.pa_start = 0x4809a000,
.pa_end = 0x4809a000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
{
.pa_start = 0x480b8000,
.pa_end = 0x480b8000 + SZ_256 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x48056000 + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x48094000 + SZ_512 - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48074000,
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
{ }
};

322
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/*
* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>
#include <mach/irqs.h>
#include "omap_hwmod_common_data.h"
/* UART */
static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
.rev_offs = 0x50,
.sysc_offs = 0x54,
.syss_offs = 0x58,
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_uart_class = {
.name = "uart",
.sysc = &omap2_uart_sysc,
};
/*
* 'dss' class
* display sub-system
*/
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dss_hwmod_class = {
.name = "dss",
.sysc = &omap2_dss_sysc,
};
/*
* 'dispc' class
* display controller
*/
static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_dispc_hwmod_class = {
.name = "dispc",
.sysc = &omap2_dispc_sysc,
};
/*
* 'rfbi' class
* remote frame buffer interface
*/
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
.name = "rfbi",
.sysc = &omap2_rfbi_sysc,
};
/*
* 'venc' class
* video encoder
*/
struct omap_hwmod_class omap2_venc_hwmod_class = {
.name = "venc",
};
/* Common DMA request line data */
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
{ .name = "rx", .dma_req = 32 },
{ .name = "tx", .dma_req = 31 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
{ .name = "rx", .dma_req = 34 },
{ .name = "tx", .dma_req = 33 },
{ .dma_req = -1 }
};
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
{ .name = "rx", .dma_req = 18 },
{ .name = "tx", .dma_req = 17 },
{ .dma_req = -1 }
};
/* Other IP block data */
/*
* omap_hwmod class data
*/
struct omap_hwmod_class l3_hwmod_class = {
.name = "l3"
};
struct omap_hwmod_class l4_hwmod_class = {
.name = "l4"
};
struct omap_hwmod_class mpu_hwmod_class = {
.name = "mpu"
};
struct omap_hwmod_class iva_hwmod_class = {
.name = "iva"
};
/* Common MPU IRQ line data */
struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
{ .irq = 37, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
{ .irq = 38, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
{ .irq = 39, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
{ .irq = 40, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
{ .irq = 41, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
{ .irq = 42, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
{ .irq = 43, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
{ .irq = 44, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
{ .irq = 45, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
{ .irq = 46, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
{ .irq = 47, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
{ .irq = INT_24XX_UART1_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
{ .irq = INT_24XX_UART2_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
{ .irq = INT_24XX_UART3_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
{ .irq = 25 },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
{ .irq = INT_24XX_I2C1_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
{ .irq = INT_24XX_I2C2_IRQ, },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
{ .irq = 65 },
{ .irq = -1 }
};
struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
{ .irq = 66 },
{ .irq = -1 }
};

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arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c Normal file
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/*
* omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
*
* Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
* XXX these should be marked initdata for multi-OMAP kernels
*/
#include <asm/sizes.h>
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include "omap_hwmod_common_data.h"
struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
{
.pa_start = OMAP2_UART1_BASE,
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
{
.pa_start = OMAP2_UART2_BASE,
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
{
.pa_start = OMAP2_UART3_BASE,
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
{
.pa_start = 0x4802a000,
.pa_end = 0x4802a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
{
.pa_start = 0x4807a000,
.pa_end = 0x4807a000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
{
.pa_start = 0x4807c000,
.pa_end = 0x4807c000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
{
.pa_start = 0x4807e000,
.pa_end = 0x4807e000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
{
.pa_start = 0x48082000,
.pa_end = 0x48082000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
{
.pa_start = 0x48084000,
.pa_end = 0x48084000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
{
.name = "mpu",
.pa_start = 0x48076000,
.pa_end = 0x480760ff,
.flags = ADDR_TYPE_RT
},
{ }
};

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arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c Normal file
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@ -0,0 +1,150 @@
/*
* omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
*
* Copyright (C) 2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <plat/omap_hwmod.h>
#include <plat/serial.h>
#include <plat/dma.h>
#include <plat/dmtimer.h>
#include <plat/mcspi.h>
#include <mach/irqs.h>
#include "omap_hwmod_common_data.h"
#include "wd_timer.h"
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
{ .irq = 48, },
{ .irq = -1 }
};
struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .dma_req = -1 }
};
/* OMAP2xxx Timer Common */
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
.name = "timer",
.sysc = &omap2xxx_timer_sysc,
.rev = OMAP_TIMER_IP_VERSION_1,
};
/*
* 'wd_timer' class
* 32-bit watchdog upward counter that generates a pulse on the reset pin on
* overflow condition
*/
static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
.name = "wd_timer",
.sysc = &omap2xxx_wd_timer_sysc,
.pre_shutdown = &omap2_wd_timer_disable
};
/*
* 'gpio' class
* general purpose io module
*/
static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
.name = "gpio",
.sysc = &omap2xxx_gpio_sysc,
.rev = 0,
};
/* system dma */
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2xxx_dma_sysc,
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
* using a queued mailbox-interrupt mechanism.
*/
static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
.rev_offs = 0x000,
.sysc_offs = 0x010,
.syss_offs = 0x014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
.name = "mailbox",
.sysc = &omap2xxx_mailbox_sysc,
};
/*
* 'mcspi' class
* multichannel serial port interface (mcspi) / master/slave synchronous serial
* bus
*/
static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_mcspi_class = {
.name = "mcspi",
.sysc = &omap2xxx_mcspi_sysc,
.rev = OMAP2_MCSPI_REV,
};

672
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
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959
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
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20
arch/arm/mach-omap2/omap_hwmod_common_data.c
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@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
};
/*
* omap_hwmod class data
*/
struct omap_hwmod_class l3_hwmod_class = {
.name = "l3"
};
struct omap_hwmod_class l4_hwmod_class = {
.name = "l4"
};
struct omap_hwmod_class mpu_hwmod_class = {
.name = "mpu"
};
struct omap_hwmod_class iva_hwmod_class = {
.name = "iva"
};

93
arch/arm/mach-omap2/omap_hwmod_common_data.h
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@ -1,10 +1,10 @@
/*
* omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2010-2011 Nokia Corporation
* Paul Walmsley
*
* Copyright (C) 2010 Texas Instruments, Inc.
* Copyright (C) 2010-2011 Texas Instruments, Inc.
* Benoît Cousson
*
* This program is free software; you can redistribute it and/or modify
@ -16,10 +16,99 @@
#include <plat/omap_hwmod.h>
/* Common address space across OMAP2xxx */
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
/* Common address space across OMAP2xxx/3xxx */
extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
extern struct omap_hwmod_addr_space omap2_dss_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
/* Common IP block data across OMAP2xxx */
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
/* Common IP block data */
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
/* Common IP block data on OMAP2430/OMAP3 */
extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
/* Common IP block data across OMAP2/3 */
extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
/* OMAP hwmod classes - forward declarations */
extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class l4_hwmod_class;
extern struct omap_hwmod_class mpu_hwmod_class;
extern struct omap_hwmod_class iva_hwmod_class;
extern struct omap_hwmod_class omap2_uart_class;
extern struct omap_hwmod_class omap2_dss_hwmod_class;
extern struct omap_hwmod_class omap2_dispc_hwmod_class;
extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
extern struct omap_hwmod_class omap2_venc_hwmod_class;
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
#endif

372
arch/arm/mach-omap2/pm-debug.c
View File

@ -38,155 +38,12 @@
#include "prm2xxx_3xxx.h"
#include "pm.h"
int omap2_pm_debug;
u32 enable_off_mode;
u32 sleep_while_idle;
u32 wakeup_timer_seconds;
u32 wakeup_timer_milliseconds;
#define DUMP_PRM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
#define DUMP_CM_MOD_REG(mod, reg) \
regs[reg_count].name = #mod "." #reg; \
regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
#define DUMP_PRM_REG(reg) \
regs[reg_count].name = #reg; \
regs[reg_count++].val = __raw_readl(reg)
#define DUMP_CM_REG(reg) \
regs[reg_count].name = #reg; \
regs[reg_count++].val = __raw_readl(reg)
#define DUMP_INTC_REG(reg, off) \
regs[reg_count].name = #reg; \
regs[reg_count++].val = \
__raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
void omap2_pm_dump(int mode, int resume, unsigned int us)
{
struct reg {
const char *name;
u32 val;
} regs[32];
int reg_count = 0, i;
const char *s1 = NULL, *s2 = NULL;
if (!resume) {
#if 0
/* MPU */
DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
#endif
#if 0
/* INTC */
DUMP_INTC_REG(INTC_MIR0, 0x0084);
DUMP_INTC_REG(INTC_MIR1, 0x00a4);
DUMP_INTC_REG(INTC_MIR2, 0x00c4);
#endif
#if 0
DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
if (cpu_is_omap24xx()) {
DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
}
DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
#endif
#if 0
/* DSP */
if (cpu_is_omap24xx()) {
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
}
#endif
} else {
DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
if (cpu_is_omap24xx())
DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
#if 1
DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
#endif
}
switch (mode) {
case 0:
s1 = "full";
s2 = "retention";
break;
case 1:
s1 = "MPU";
s2 = "retention";
break;
case 2:
s1 = "MPU";
s2 = "idle";
break;
}
if (!resume)
#ifdef CONFIG_NO_HZ
printk(KERN_INFO
"--- Going to %s %s (next timer after %u ms)\n", s1, s2,
jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
jiffies));
#else
printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
#endif
else
printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
us / 1000, us % 1000);
for (i = 0; i < reg_count; i++)
printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
}
void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
{
u32 tick_rate, cycles;
if (!seconds && !milliseconds)
return;
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
omap_dm_timer_stop(gptimer_wakeup);
omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
pr_info("PM: Resume timer in %u.%03u secs"
" (%d ticks at %d ticks/sec.)\n",
seconds, milliseconds, cycles, tick_rate);
}
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
static void pm_dbg_regset_store(u32 *ptr);
static struct dentry *pm_dbg_dir;
static int pm_dbg_init_done;
static int pm_dbg_init(void);
@ -196,160 +53,6 @@ enum {
DEBUG_FILE_TIMERS,
};
struct pm_module_def {
char name[8]; /* Name of the module */
short type; /* CM or PRM */
unsigned short offset;
int low; /* First register address on this module */
int high; /* Last register address on this module */
};
#define MOD_CM 0
#define MOD_PRM 1
static const struct pm_module_def *pm_dbg_reg_modules;
static const struct pm_module_def omap3_pm_reg_modules[] = {
{ "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
{ "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
{ "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
{ "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
{ "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
{ "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
{ "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
{ "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
{ "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
{ "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
{ "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
{ "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
{ "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
{ "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
{ "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
{ "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
{ "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
{ "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
{ "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
{ "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
{ "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
{ "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
{ "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
{ "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
{ "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
{ "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
{ "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
{ "", 0, 0, 0, 0 },
};
#define PM_DBG_MAX_REG_SETS 4
static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
static int pm_dbg_get_regset_size(void)
{
static int regset_size;
if (regset_size == 0) {
int i = 0;
while (pm_dbg_reg_modules[i].name[0] != 0) {
regset_size += pm_dbg_reg_modules[i].high +
4 - pm_dbg_reg_modules[i].low;
i++;
}
}
return regset_size;
}
static int pm_dbg_show_regs(struct seq_file *s, void *unused)
{
int i, j;
unsigned long val;
int reg_set = (int)s->private;
u32 *ptr;
void *store = NULL;
int regs;
int linefeed;
if (reg_set == 0) {
store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
ptr = store;
pm_dbg_regset_store(ptr);
} else {
ptr = pm_dbg_reg_set[reg_set - 1];
}
i = 0;
while (pm_dbg_reg_modules[i].name[0] != 0) {
regs = 0;
linefeed = 0;
if (pm_dbg_reg_modules[i].type == MOD_CM)
seq_printf(s, "MOD: CM_%s (%08x)\n",
pm_dbg_reg_modules[i].name,
(u32)(OMAP3430_CM_BASE +
pm_dbg_reg_modules[i].offset));
else
seq_printf(s, "MOD: PRM_%s (%08x)\n",
pm_dbg_reg_modules[i].name,
(u32)(OMAP3430_PRM_BASE +
pm_dbg_reg_modules[i].offset));
for (j = pm_dbg_reg_modules[i].low;
j <= pm_dbg_reg_modules[i].high; j += 4) {
val = *(ptr++);
if (val != 0) {
regs++;
if (linefeed) {
seq_printf(s, "\n");
linefeed = 0;
}
seq_printf(s, " %02x => %08lx", j, val);
if (regs % 4 == 0)
linefeed = 1;
}
}
seq_printf(s, "\n");
i++;
}
if (store != NULL)
kfree(store);
return 0;
}
static void pm_dbg_regset_store(u32 *ptr)
{
int i, j;
u32 val;
i = 0;
while (pm_dbg_reg_modules[i].name[0] != 0) {
for (j = pm_dbg_reg_modules[i].low;
j <= pm_dbg_reg_modules[i].high; j += 4) {
if (pm_dbg_reg_modules[i].type == MOD_CM)
val = omap2_cm_read_mod_reg(
pm_dbg_reg_modules[i].offset, j);
else
val = omap2_prm_read_mod_reg(
pm_dbg_reg_modules[i].offset, j);
*(ptr++) = val;
}
i++;
}
}
int pm_dbg_regset_save(int reg_set)
{
if (pm_dbg_reg_set[reg_set-1] == NULL)
return -EINVAL;
pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
return 0;
}
static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
"OFF",
"RET",
@ -469,11 +172,6 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
};
}
static int pm_dbg_reg_open(struct inode *inode, struct file *file)
{
return single_open(file, pm_dbg_show_regs, inode->i_private);
}
static const struct file_operations debug_fops = {
.open = pm_dbg_open,
.read = seq_read,
@ -481,40 +179,6 @@ static const struct file_operations debug_fops = {
.release = single_release,
};
static const struct file_operations debug_reg_fops = {
.open = pm_dbg_reg_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
int pm_dbg_regset_init(int reg_set)
{
char name[2];
if (!pm_dbg_init_done)
pm_dbg_init();
if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
pm_dbg_reg_set[reg_set-1] != NULL)
return -EINVAL;
pm_dbg_reg_set[reg_set-1] =
kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
if (pm_dbg_reg_set[reg_set-1] == NULL)
return -ENOMEM;
if (pm_dbg_dir != NULL) {
sprintf(name, "%d", reg_set);
(void) debugfs_create_file(name, S_IRUGO,
pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
}
return 0;
}
static int pwrdm_suspend_get(void *data, u64 *val)
{
int ret = -EINVAL;
@ -576,9 +240,6 @@ static int option_set(void *data, u64 val)
{
u32 *option = data;
if (option == &wakeup_timer_milliseconds && val >= 1000)
return -EINVAL;
*option = val;
if (option == &enable_off_mode) {
@ -595,22 +256,13 @@ static int option_set(void *data, u64 val)
DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
static int pm_dbg_init(void)
static int __init pm_dbg_init(void)
{
int i;
struct dentry *d;
char name[2];
if (pm_dbg_init_done)
return 0;
if (cpu_is_omap34xx())
pm_dbg_reg_modules = omap3_pm_reg_modules;
else {
printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
return -ENODEV;
}
d = debugfs_create_dir("pm_debug", NULL);
if (IS_ERR(d))
return PTR_ERR(d);
@ -622,30 +274,8 @@ static int pm_dbg_init(void)
pwrdm_for_each(pwrdms_setup, (void *)d);
pm_dbg_dir = debugfs_create_dir("registers", d);
if (IS_ERR(pm_dbg_dir))
return PTR_ERR(pm_dbg_dir);
(void) debugfs_create_file("current", S_IRUGO,
pm_dbg_dir, (void *)0, &debug_reg_fops);
for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
if (pm_dbg_reg_set[i] != NULL) {
sprintf(name, "%d", i+1);
(void) debugfs_create_file(name, S_IRUGO,
pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
}
(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
&enable_off_mode, &pm_dbg_option_fops);
(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
&sleep_while_idle, &pm_dbg_option_fops);
(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
&wakeup_timer_seconds, &pm_dbg_option_fops);
(void) debugfs_create_file("wakeup_timer_milliseconds",
S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
&pm_dbg_option_fops);
pm_dbg_init_done = 1;
return 0;

6
arch/arm/mach-omap2/pm.c
View File

@ -106,8 +106,9 @@ static void omap2_init_processor_devices(void)
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
{
u32 cur_state;
int sleep_switch = 0;
int sleep_switch = -1;
int ret = 0;
int hwsup = 0;
if (pwrdm == NULL || IS_ERR(pwrdm))
return -EINVAL;
@ -127,6 +128,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
sleep_switch = LOWPOWERSTATE_SWITCH;
} else {
hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
sleep_switch = FORCEWAKEUP_SWITCH;
@ -142,7 +144,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
switch (sleep_switch) {
case FORCEWAKEUP_SWITCH:
if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
if (hwsup)
clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
else
clkdm_sleep(pwrdm->pwrdm_clkdms[0]);

16
arch/arm/mach-omap2/pm.h
View File

@ -60,32 +60,16 @@ inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
extern u32 wakeup_timer_seconds;
extern u32 wakeup_timer_milliseconds;
extern struct omap_dm_timer *gptimer_wakeup;
#ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
extern int omap2_pm_debug;
extern u32 enable_off_mode;
extern u32 sleep_while_idle;
#else
#define omap2_pm_dump(mode, resume, us) do {} while (0);
#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
#define omap2_pm_debug 0
#define enable_off_mode 0
#define sleep_while_idle 0
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
extern int pm_dbg_regset_save(int reg_set);
extern int pm_dbg_regset_init(int reg_set);
#else
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#define pm_dbg_regset_save(reg_set) do {} while (0);
#define pm_dbg_regset_init(reg_set) do {} while (0);
#endif /* CONFIG_PM_DEBUG */
extern void omap24xx_idle_loop_suspend(void);

6
arch/arm/mach-omap2/pm24xx.c
View File

@ -53,6 +53,8 @@
#include "powerdomain.h"
#include "clockdomain.h"
static int omap2_pm_debug;
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
@ -123,7 +125,6 @@ static void omap2_enter_full_retention(void)
omap2_gpio_prepare_for_idle(0);
if (omap2_pm_debug) {
omap2_pm_dump(0, 0, 0);
getnstimeofday(&ts_preidle);
}
@ -160,7 +161,6 @@ no_sleep:
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
omap2_pm_dump(0, 1, tmp);
}
omap2_gpio_resume_after_idle();
@ -247,7 +247,6 @@ static void omap2_enter_mpu_retention(void)
}
if (omap2_pm_debug) {
omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
getnstimeofday(&ts_preidle);
}
@ -259,7 +258,6 @@ static void omap2_enter_mpu_retention(void)
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
}
}

6
arch/arm/mach-omap2/pm34xx.c
View File

@ -497,8 +497,6 @@ console_still_active:
int omap3_can_sleep(void)
{
if (!sleep_while_idle)
return 0;
if (!omap_uart_can_sleep())
return 0;
return 1;
@ -534,10 +532,6 @@ static int omap3_pm_suspend(void)
struct power_state *pwrst;
int state, ret = 0;
if (wakeup_timer_seconds || wakeup_timer_milliseconds)
omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
wakeup_timer_milliseconds);
/* Read current next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node)
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);

27
arch/arm/mach-omap2/powerdomains44xx_data.c
View File

@ -1,7 +1,7 @@
/*
* OMAP4 Power domains framework
*
* Copyright (C) 2009-2010 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Abhijit Pagare (abhijitpagare@ti.com)
@ -41,19 +41,19 @@ static struct powerdomain core_44xx_pwrdm = {
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[1] = PWRSTS_RET, /* core_ocmram */
[2] = PWRSTS_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ducati_l2ram */
[4] = PWRSTS_OFF_RET, /* ducati_unicache */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[1] = PWRSTS_ON, /* core_ocmram */
[2] = PWRSTS_ON, /* core_other_bank */
[3] = PWRSTS_ON, /* ducati_l2ram */
[4] = PWRSTS_ON, /* ducati_unicache */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gfx_44xx_pwrdm: 3D accelerator power domain */
@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* gfx_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* abe_44xx_pwrdm: Audio back end power domain */
@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
[0] = PWRSTS_ON, /* aessmem */
[1] = PWRSTS_ON, /* periphmem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dss_44xx_pwrdm: Display subsystem power domain */
@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* dss_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* tesla_44xx_pwrdm: Tesla processor power domain */
@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
[1] = PWRSTS_ON, /* tesla_l1 */
[2] = PWRSTS_ON, /* tesla_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkup_44xx_pwrdm: Wake-up power domain */
@ -205,7 +205,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
.prcm_offs = OMAP4430_PRM_MPU_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
.pwrsts_mem_ret = {
@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
[2] = PWRSTS_ON, /* tcm1_mem */
[3] = PWRSTS_ON, /* tcm2_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_44xx_pwrdm: Camera subsystem power domain */
@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cam_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* l3init_bank1 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l4per_44xx_pwrdm: Target peripherals power domain */
@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
[0] = PWRSTS_ON, /* nonretained_bank */
[1] = PWRSTS_ON, /* retained_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*

2
arch/arm/mach-omap2/prcm.c
View File

@ -70,7 +70,7 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
prcm_offs = OMAP3430_GR_MOD;
omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
} else if (cpu_is_omap44xx()) {
omap4_prm_global_warm_sw_reset(); /* never returns */
omap4_prminst_global_warm_sw_reset(); /* never returns */
} else {
WARN_ON(1);
}

69
arch/arm/mach-omap2/prcm_mpu44xx.h
View File

@ -31,7 +31,6 @@
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
/* PRCM_MPU instances */
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
@ -52,46 +51,46 @@
*/
/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
#define OMAP4_REVISION_PRCM_OFFSET 0x0000
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
#define OMAP4_REVISION_PRCM_OFFSET 0x0000
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
/* PRCM_MPU.DEVICE_PRM register offsets */
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
/* PRCM_MPU.CPU0 register offsets */
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
/* PRCM_MPU.CPU1 register offsets */
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
/* Function prototypes */
# ifndef __ASSEMBLER__

145
arch/arm/mach-omap2/prm44xx.c
View File

@ -1,7 +1,7 @@
/*
* OMAP4 PRM module functions
*
* Copyright (C) 2010 Texas Instruments, Inc.
* Copyright (C) 2011 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
* Benoît Cousson
* Paul Walmsley
@ -24,12 +24,6 @@
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
/*
* Address offset (in bytes) between the reset control and the reset
* status registers: 4 bytes on OMAP4
*/
#define OMAP4_RST_CTRL_ST_OFFSET 4
/* PRM low-level functions */
/* Read a register in a CM/PRM instance in the PRM module */
@ -56,140 +50,3 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
return v;
}
/* Read a PRM register, AND it, and shift the result down to bit 0 */
/* XXX deprecated */
u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
{
u32 v;
v = __raw_readl(reg);
v &= mask;
v >>= __ffs(mask);
return v;
}
/* Read-modify-write a register in a PRM module. Caller must lock */
/* XXX deprecated */
u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
{
u32 v;
v = __raw_readl(reg);
v &= ~mask;
v |= bits;
__raw_writel(v, reg);
return v;
}
u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
{
return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
}
u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
{
return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
}
/**
* omap4_prm_is_hardreset_asserted - read the HW reset line state of
* submodules contained in the hwmod module
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @shift: register bit shift corresponding to the reset line to check
*
* Returns 1 if the (sub)module hardreset line is currently asserted,
* 0 if the (sub)module hardreset line is not currently asserted, or
* -EINVAL upon parameter error.
*/
int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
{
if (!cpu_is_omap44xx() || !rstctrl_reg)
return -EINVAL;
return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
}
/**
* omap4_prm_assert_hardreset - assert the HW reset line of a submodule
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @shift: register bit shift corresponding to the reset line to assert
*
* Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* place the submodule into reset. Returns 0 upon success or -EINVAL
* upon an argument error.
*/
int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
{
u32 mask;
if (!cpu_is_omap44xx() || !rstctrl_reg)
return -EINVAL;
mask = 1 << shift;
omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
return 0;
}
/**
* omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @shift: register bit shift corresponding to the reset line to deassert
*
* Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* take the submodule out of reset and wait until the PRCM indicates
* that the reset has completed before returning. Returns 0 upon success or
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly.
*/
int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
{
u32 mask;
void __iomem *rstst_reg;
int c;
if (!cpu_is_omap44xx() || !rstctrl_reg)
return -EINVAL;
rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
mask = 1 << shift;
/* Check the current status to avoid de-asserting the line twice */
if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
return -EEXIST;
/* Clear the reset status by writing 1 to the status bit */
omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
/* de-assert the reset control line */
omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
/* wait the status to be set */
omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
MAX_MODULE_HARDRESET_WAIT, c);
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}
void omap4_prm_global_warm_sw_reset(void)
{
u32 v;
v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
OMAP4_RM_RSTCTRL);
v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
OMAP4_RM_RSTCTRL);
/* OCP barrier */
v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
OMAP4_RM_RSTCTRL);
}

44
arch/arm/mach-omap2/prm44xx.h
View File

@ -31,7 +31,7 @@
#define OMAP4430_PRM_BASE 0x4a306000
#define OMAP44XX_PRM_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
/* PRM instances */
@ -46,30 +46,18 @@
#define OMAP4430_PRM_CAM_INST 0x1000
#define OMAP4430_PRM_DSS_INST 0x1100
#define OMAP4430_PRM_GFX_INST 0x1200
#define OMAP4430_PRM_L3INIT_INST 0x1300
#define OMAP4430_PRM_L3INIT_INST 0x1300
#define OMAP4430_PRM_L4PER_INST 0x1400
#define OMAP4430_PRM_CEFUSE_INST 0x1600
#define OMAP4430_PRM_CEFUSE_INST 0x1600
#define OMAP4430_PRM_WKUP_INST 0x1700
#define OMAP4430_PRM_WKUP_CM_INST 0x1800
#define OMAP4430_PRM_EMU_INST 0x1900
#define OMAP4430_PRM_EMU_CM_INST 0x1a00
#define OMAP4430_PRM_DEVICE_INST 0x1b00
#define OMAP4430_PRM_EMU_CM_INST 0x1a00
#define OMAP4430_PRM_DEVICE_INST 0x1b00
#define OMAP4430_PRM_INSTR_INST 0x1f00
/* PRM clockdomain register offsets (from instance start) */
#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
/* OMAP4 specific register offsets */
@ -247,8 +235,8 @@
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c
#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
@ -713,8 +701,8 @@
#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8
#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
@ -751,8 +739,8 @@
#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4
#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
@ -762,16 +750,6 @@
extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
extern void omap4_prm_global_warm_sw_reset(void);
# endif

112
arch/arm/mach-omap2/prminst44xx.c
View File

@ -2,6 +2,7 @@
* OMAP4 PRM instance functions
*
* Copyright (C) 2009 Nokia Corporation
* Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@ -53,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
/* Read-modify-write a register in PRM. Caller must lock */
u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
s16 idx)
u16 idx)
{
u32 v;
@ -64,3 +65,112 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
return v;
}
/*
* Address offset (in bytes) between the reset control and the reset
* status registers: 4 bytes on OMAP4
*/
#define OMAP4_RST_CTRL_ST_OFFSET 4
/**
* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
* submodules contained in the hwmod module
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @shift: register bit shift corresponding to the reset line to check
*
* Returns 1 if the (sub)module hardreset line is currently asserted,
* 0 if the (sub)module hardreset line is not currently asserted, or
* -EINVAL upon parameter error.
*/
int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
u16 rstctrl_offs)
{
u32 v;
v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
v &= 1 << shift;
v >>= shift;
return v;
}
/**
* omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @shift: register bit shift corresponding to the reset line to assert
*
* Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* place the submodule into reset. Returns 0 upon success or -EINVAL
* upon an argument error.
*/
int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
u16 rstctrl_offs)
{
u32 mask = 1 << shift;
omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
return 0;
}
/**
* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
* wait
* @rstctrl_reg: RM_RSTCTRL register address for this module
* @shift: register bit shift corresponding to the reset line to deassert
*
* Some IPs like dsp, ipu or iva contain processors that require an HW
* reset line to be asserted / deasserted in order to fully enable the
* IP. These modules may have multiple hard-reset lines that reset
* different 'submodules' inside the IP block. This function will
* take the submodule out of reset and wait until the PRCM indicates
* that the reset has completed before returning. Returns 0 upon success or
* -EINVAL upon an argument error, -EEXIST if the submodule was already out
* of reset, or -EBUSY if the submodule did not exit reset promptly.
*/
int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
u16 rstctrl_offs)
{
int c;
u32 mask = 1 << shift;
u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
/* Check the current status to avoid de-asserting the line twice */
if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
rstctrl_offs) == 0)
return -EEXIST;
/* Clear the reset status by writing 1 to the status bit */
omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
rstst_offs);
/* de-assert the reset control line */
omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
/* wait the status to be set */
omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
rstst_offs),
MAX_MODULE_HARDRESET_WAIT, c);
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}
void omap4_prminst_global_warm_sw_reset(void)
{
u32 v;
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
OMAP4430_PRM_DEVICE_INST,
OMAP4_PRM_RSTCTRL_OFFSET);
v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
OMAP4430_PRM_DEVICE_INST,
OMAP4_PRM_RSTCTRL_OFFSET);
/* OCP barrier */
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
OMAP4430_PRM_DEVICE_INST,
OMAP4_PRM_RSTCTRL_OFFSET);
}

12
arch/arm/mach-omap2/prminst44xx.h
View File

@ -2,6 +2,7 @@
* OMAP4 Power/Reset Management (PRM) function prototypes
*
* Copyright (C) 2010 Nokia Corporation
* Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@ -18,8 +19,15 @@
extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
s16 inst, s16 idx);
s16 inst, u16 idx);
extern void omap4_prm_global_warm_sw_reset(void);
extern void omap4_prminst_global_warm_sw_reset(void);
extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
u16 rstctrl_offs);
extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
u16 rstctrl_offs);
extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
u16 rstctrl_offs);
#endif

38
arch/arm/mach-omap2/smartreflex.c
View File

@ -143,7 +143,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
sr_write_reg(sr_info, IRQSTATUS, status);
}
if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
if (sr_class->notify)
sr_class->notify(sr_info->voltdm, status);
return IRQ_HANDLED;
@ -258,9 +258,7 @@ static int sr_late_init(struct omap_sr *sr_info)
struct resource *mem;
int ret = 0;
if (sr_class->class_type == SR_CLASS2 &&
sr_class->notify_flags && sr_info->irq) {
if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
if (name == NULL) {
ret = -ENOMEM;
@ -270,6 +268,7 @@ static int sr_late_init(struct omap_sr *sr_info)
0, name, (void *)sr_info);
if (ret)
goto error;
disable_irq(sr_info->irq);
}
if (pdata && pdata->enable_on_init)
@ -278,16 +277,16 @@ static int sr_late_init(struct omap_sr *sr_info)
return ret;
error:
iounmap(sr_info->base);
mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
release_mem_region(mem->start, resource_size(mem));
list_del(&sr_info->node);
dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
"interrupt handler. Smartreflex will"
"not function as desired\n", __func__);
kfree(name);
kfree(sr_info);
return ret;
iounmap(sr_info->base);
mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
release_mem_region(mem->start, resource_size(mem));
list_del(&sr_info->node);
dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
"interrupt handler. Smartreflex will"
"not function as desired\n", __func__);
kfree(name);
kfree(sr_info);
return ret;
}
static void sr_v1_disable(struct omap_sr *sr)
@ -808,10 +807,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
return -EINVAL;
}
if (!val)
sr_stop_vddautocomp(sr_info);
else
sr_start_vddautocomp(sr_info);
/* control enable/disable only if there is a delta in value */
if (sr_info->autocomp_active != val) {
if (!val)
sr_stop_vddautocomp(sr_info);
else
sr_start_vddautocomp(sr_info);
}
return 0;
}

266
arch/arm/mach-omap2/timer-gp.c
View File

@ -1,266 +0,0 @@
/*
* linux/arch/arm/mach-omap2/timer-gp.c
*
* OMAP2 GP timer support.
*
* Copyright (C) 2009 Nokia Corporation
*
* Update to use new clocksource/clockevent layers
* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
* Copyright (C) 2007 MontaVista Software, Inc.
*
* Original driver:
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
* Juha Yrjölä <juha.yrjola@nokia.com>
* OMAP Dual-mode timer framework support by Timo Teras
*
* Some parts based off of TI's 24xx code:
*
* Copyright (C) 2004-2009 Texas Instruments, Inc.
*
* Roughly modelled after the OMAP1 MPU timer code.
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <plat/dmtimer.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>
#include <plat/common.h>
#include <plat/omap_hwmod.h>
#include "timer-gp.h"
/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
#define MAX_GPTIMER_ID 12
static struct omap_dm_timer *gptimer;
static struct clock_event_device clockevent_gpt;
static u8 __initdata gptimer_id = 1;
static u8 __initdata inited;
struct omap_dm_timer *gptimer_wakeup;
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
struct clock_event_device *evt = &clockevent_gpt;
omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction omap2_gp_timer_irq = {
.name = "gp timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = omap2_gp_timer_interrupt,
};
static int omap2_gp_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
return 0;
}
static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
u32 period;
omap_dm_timer_stop(gptimer);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
period -= 1;
omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device clockevent_gpt = {
.name = "gp timer",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.set_next_event = omap2_gp_timer_set_next_event,
.set_mode = omap2_gp_timer_set_mode,
};
/**
* omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
* @id: GPTIMER to use (1..MAX_GPTIMER_ID)
*
* Define the GPTIMER that the system should use for the tick timer.
* Meant to be called from board-*.c files in the event that GPTIMER1, the
* default, is unsuitable. Returns -EINVAL on error or 0 on success.
*/
int __init omap2_gp_clockevent_set_gptimer(u8 id)
{
if (id < 1 || id > MAX_GPTIMER_ID)
return -EINVAL;
BUG_ON(inited);
gptimer_id = id;
return 0;
}
static void __init omap2_gp_clockevent_init(void)
{
u32 tick_rate;
int src;
char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
inited = 1;
sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
omap_hwmod_setup_one(clockevent_hwmod_name);
gptimer = omap_dm_timer_request_specific(gptimer_id);
BUG_ON(gptimer == NULL);
gptimer_wakeup = gptimer;
#if defined(CONFIG_OMAP_32K_TIMER)
src = OMAP_TIMER_SRC_32_KHZ;
#else
src = OMAP_TIMER_SRC_SYS_CLK;
WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
"secure 32KiHz clock source\n");
#endif
if (gptimer_id != 12)
WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
"timer-gp: omap_dm_timer_set_source() failed\n");
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
gptimer_id, tick_rate);
omap2_gp_timer_irq.dev_id = (void *)gptimer;
setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
clockevent_gpt.shift);
clockevent_gpt.max_delta_ns =
clockevent_delta2ns(0xffffffff, &clockevent_gpt);
clockevent_gpt.min_delta_ns =
clockevent_delta2ns(3, &clockevent_gpt);
/* Timer internal resynch latency. */
clockevent_gpt.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_gpt);
}
/* Clocksource code */
#ifdef CONFIG_OMAP_32K_TIMER
/*
* When 32k-timer is enabled, don't use GPTimer for clocksource
* instead, just leave default clocksource which uses the 32k
* sync counter. See clocksource setup in plat-omap/counter_32k.c
*/
static void __init omap2_gp_clocksource_init(void)
{
omap_init_clocksource_32k();
}
#else
/*
* clocksource
*/
static DEFINE_CLOCK_DATA(cd);
static struct omap_dm_timer *gpt_clocksource;
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
}
static struct clocksource clocksource_gpt = {
.name = "gp timer",
.rating = 300,
.read = clocksource_read_cycles,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void notrace dmtimer_update_sched_clock(void)
{
u32 cyc;
cyc = omap_dm_timer_read_counter(gpt_clocksource);
update_sched_clock(&cd, cyc, (u32)~0);
}
/* Setup free-running counter for clocksource */
static void __init omap2_gp_clocksource_init(void)
{
static struct omap_dm_timer *gpt;
u32 tick_rate;
static char err1[] __initdata = KERN_ERR
"%s: failed to request dm-timer\n";
static char err2[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
gpt = omap_dm_timer_request();
if (!gpt)
printk(err1, clocksource_gpt.name);
gpt_clocksource = gpt;
omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
omap_dm_timer_set_load_start(gpt, 1, 0);
init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
if (clocksource_register_hz(&clocksource_gpt, tick_rate))
printk(err2, clocksource_gpt.name);
}
#endif
static void __init omap2_gp_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
if (cpu_is_omap44xx()) {
twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
BUG_ON(!twd_base);
}
#endif
omap_dm_timer_init();
omap2_gp_clockevent_init();
omap2_gp_clocksource_init();
}
struct sys_timer omap_timer = {
.init = omap2_gp_timer_init,
};

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