i2c: mediatek: Add offsets array for new i2c registers
New i2c registers would have different offsets, so we use different offsets array to distinguish different i2c registers version. Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Qii Wang
Wolfram Sang
parent
0ec4b562c3
commit
bc6eaf1709
@ -106,34 +106,62 @@ enum mtk_trans_op {
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};
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enum I2C_REGS_OFFSET {
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OFFSET_DATA_PORT = 0x0,
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OFFSET_SLAVE_ADDR = 0x04,
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OFFSET_INTR_MASK = 0x08,
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OFFSET_INTR_STAT = 0x0c,
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OFFSET_CONTROL = 0x10,
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OFFSET_TRANSFER_LEN = 0x14,
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OFFSET_TRANSAC_LEN = 0x18,
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OFFSET_DELAY_LEN = 0x1c,
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OFFSET_TIMING = 0x20,
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OFFSET_START = 0x24,
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OFFSET_EXT_CONF = 0x28,
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OFFSET_FIFO_STAT = 0x30,
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OFFSET_FIFO_THRESH = 0x34,
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OFFSET_FIFO_ADDR_CLR = 0x38,
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OFFSET_IO_CONFIG = 0x40,
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OFFSET_RSV_DEBUG = 0x44,
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OFFSET_HS = 0x48,
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OFFSET_SOFTRESET = 0x50,
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OFFSET_DCM_EN = 0x54,
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OFFSET_PATH_DIR = 0x60,
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OFFSET_DEBUGSTAT = 0x64,
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OFFSET_DEBUGCTRL = 0x68,
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OFFSET_TRANSFER_LEN_AUX = 0x6c,
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OFFSET_CLOCK_DIV = 0x70,
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OFFSET_DATA_PORT,
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OFFSET_SLAVE_ADDR,
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OFFSET_INTR_MASK,
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OFFSET_INTR_STAT,
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OFFSET_CONTROL,
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OFFSET_TRANSFER_LEN,
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OFFSET_TRANSAC_LEN,
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OFFSET_DELAY_LEN,
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OFFSET_TIMING,
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OFFSET_START,
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OFFSET_EXT_CONF,
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OFFSET_FIFO_STAT,
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OFFSET_FIFO_THRESH,
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OFFSET_FIFO_ADDR_CLR,
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OFFSET_IO_CONFIG,
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OFFSET_RSV_DEBUG,
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OFFSET_HS,
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OFFSET_SOFTRESET,
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OFFSET_DCM_EN,
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OFFSET_PATH_DIR,
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OFFSET_DEBUGSTAT,
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OFFSET_DEBUGCTRL,
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OFFSET_TRANSFER_LEN_AUX,
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OFFSET_CLOCK_DIV,
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};
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static const u16 mt_i2c_regs_v1[] = {
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[OFFSET_DATA_PORT] = 0x0,
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[OFFSET_SLAVE_ADDR] = 0x4,
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[OFFSET_INTR_MASK] = 0x8,
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[OFFSET_INTR_STAT] = 0xc,
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[OFFSET_CONTROL] = 0x10,
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[OFFSET_TRANSFER_LEN] = 0x14,
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[OFFSET_TRANSAC_LEN] = 0x18,
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[OFFSET_DELAY_LEN] = 0x1c,
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[OFFSET_TIMING] = 0x20,
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[OFFSET_START] = 0x24,
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[OFFSET_EXT_CONF] = 0x28,
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[OFFSET_FIFO_STAT] = 0x30,
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[OFFSET_FIFO_THRESH] = 0x34,
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[OFFSET_FIFO_ADDR_CLR] = 0x38,
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[OFFSET_IO_CONFIG] = 0x40,
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[OFFSET_RSV_DEBUG] = 0x44,
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[OFFSET_HS] = 0x48,
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[OFFSET_SOFTRESET] = 0x50,
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[OFFSET_DCM_EN] = 0x54,
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[OFFSET_PATH_DIR] = 0x60,
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[OFFSET_DEBUGSTAT] = 0x64,
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[OFFSET_DEBUGCTRL] = 0x68,
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[OFFSET_TRANSFER_LEN_AUX] = 0x6c,
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[OFFSET_CLOCK_DIV] = 0x70,
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};
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struct mtk_i2c_compatible {
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const struct i2c_adapter_quirks *quirks;
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const u16 *regs;
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unsigned char pmic_i2c: 1;
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unsigned char dcm: 1;
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unsigned char auto_restart: 1;
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@ -181,6 +209,7 @@ static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
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};
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static const struct mtk_i2c_compatible mt2712_compat = {
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.regs = mt_i2c_regs_v1,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 1,
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@ -191,6 +220,7 @@ static const struct mtk_i2c_compatible mt2712_compat = {
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static const struct mtk_i2c_compatible mt6577_compat = {
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.quirks = &mt6577_i2c_quirks,
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.regs = mt_i2c_regs_v1,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 0,
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@ -201,6 +231,7 @@ static const struct mtk_i2c_compatible mt6577_compat = {
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static const struct mtk_i2c_compatible mt6589_compat = {
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.quirks = &mt6577_i2c_quirks,
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.regs = mt_i2c_regs_v1,
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.pmic_i2c = 1,
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.dcm = 0,
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.auto_restart = 0,
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@ -211,6 +242,7 @@ static const struct mtk_i2c_compatible mt6589_compat = {
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static const struct mtk_i2c_compatible mt7622_compat = {
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.quirks = &mt7622_i2c_quirks,
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.regs = mt_i2c_regs_v1,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 1,
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@ -220,6 +252,7 @@ static const struct mtk_i2c_compatible mt7622_compat = {
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};
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static const struct mtk_i2c_compatible mt8173_compat = {
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.regs = mt_i2c_regs_v1,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 1,
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@ -238,6 +271,17 @@ static const struct of_device_id mtk_i2c_of_match[] = {
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};
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MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
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static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
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{
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return readw(i2c->base + i2c->dev_comp->regs[reg]);
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}
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static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
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enum I2C_REGS_OFFSET reg)
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{
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writew(val, i2c->base + i2c->dev_comp->regs[reg]);
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}
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static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
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{
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int ret;
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@ -278,31 +322,31 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
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{
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u16 control_reg;
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writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
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mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
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/* Set ioconfig */
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if (i2c->use_push_pull)
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writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
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mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
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else
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writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
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mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
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if (i2c->dev_comp->dcm)
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writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
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mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
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if (i2c->dev_comp->timing_adjust)
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writew(I2C_DEFAULT_CLK_DIV - 1, i2c->base + OFFSET_CLOCK_DIV);
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mtk_i2c_writew(i2c, I2C_DEFAULT_CLK_DIV - 1, OFFSET_CLOCK_DIV);
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writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
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writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
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mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
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mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
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/* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
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if (i2c->have_pmic)
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writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
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mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
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control_reg = I2C_CONTROL_ACKERR_DET_EN |
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I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
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writew(control_reg, i2c->base + OFFSET_CONTROL);
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writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
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mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
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mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
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writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
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udelay(50);
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@ -454,7 +498,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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reinit_completion(&i2c->msg_complete);
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control_reg = readw(i2c->base + OFFSET_CONTROL) &
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control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
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~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
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if ((i2c->speed_hz > MAX_FS_MODE_SPEED) || (left_num >= 1))
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control_reg |= I2C_CONTROL_RS;
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@ -462,40 +506,41 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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if (i2c->op == I2C_MASTER_WRRD)
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control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
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writew(control_reg, i2c->base + OFFSET_CONTROL);
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mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
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/* set start condition */
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if (i2c->speed_hz <= I2C_DEFAULT_SPEED)
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writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
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mtk_i2c_writew(i2c, I2C_ST_START_CON, OFFSET_EXT_CONF);
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else
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writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
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mtk_i2c_writew(i2c, I2C_FS_START_CON, OFFSET_EXT_CONF);
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addr_reg = i2c_8bit_addr_from_msg(msgs);
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writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
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mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
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/* Clear interrupt status */
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
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writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
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mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
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mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
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/* Enable interrupt */
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
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mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
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/* Set transfer and transaction len */
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if (i2c->op == I2C_MASTER_WRRD) {
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if (i2c->dev_comp->aux_len_reg) {
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writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
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writew((msgs + 1)->len, i2c->base +
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OFFSET_TRANSFER_LEN_AUX);
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mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
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mtk_i2c_writew(i2c, (msgs + 1)->len,
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OFFSET_TRANSFER_LEN_AUX);
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} else {
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writew(msgs->len | ((msgs + 1)->len) << 8,
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i2c->base + OFFSET_TRANSFER_LEN);
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mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
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OFFSET_TRANSFER_LEN);
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}
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writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
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mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
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} else {
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writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
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writew(num, i2c->base + OFFSET_TRANSAC_LEN);
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mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
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mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
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}
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/* Prepare buffer data to start transfer */
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@ -607,14 +652,14 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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if (left_num >= 1)
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start_reg |= I2C_RS_MUL_CNFG;
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}
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writew(start_reg, i2c->base + OFFSET_START);
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mtk_i2c_writew(i2c, start_reg, OFFSET_START);
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ret = wait_for_completion_timeout(&i2c->msg_complete,
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i2c->adap.timeout);
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/* Clear interrupt mask */
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writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
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mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
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if (i2c->op == I2C_MASTER_WR) {
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dma_unmap_single(i2c->dev, wpaddr,
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@ -724,8 +769,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
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if (i2c->auto_restart)
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restart_flag = I2C_RS_TRANSFER;
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intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
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writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
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intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
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mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
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/*
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* when occurs ack error, i2c controller generate two interrupts
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@ -737,8 +782,8 @@ static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
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if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
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i2c->ignore_restart_irq = false;
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i2c->irq_stat = 0;
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writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
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i2c->base + OFFSET_START);
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mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
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I2C_TRANSAC_START, OFFSET_START);
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} else {
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if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
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complete(&i2c->msg_complete);
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