soc/tegra: Changes for v6.5-rc1
This adds initial support for identifying the Tegra264 SoC family and fixes potential issues when reading from the FUSE block. A new software wake event for the AON cluster is added on Tegra234 and the debugfs initialization is drastically simplified. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmSDRAMTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoePdD/kBmBNU0jOYOPCIDvL9/ZGallfogOyQ 7+MEyY/POCYiWiBFS2qixGHr9yu5KgmEc8y7Mq7C7/PmC5y4EoLuZF7QRiCUl78t wyCROYb0WqBivAMdDFyXyxxJDCmNXGUqZyx6QpGQlJEwWlrJMExQsaw9F6366/JR q0QPkKtzGGVXwxwpH3XdrfD/9cUOhTe8oGZ9uPW/q3j0JqO1x9pcnVSUWU3nXeEy pvQjJjXAlB+9imAYuykDZMTUhlTqTrQTREk4JlG1UQkrs9vh4SDrPYh7IKlhbKct /crML7JOZwoIAQ2lmapqrSijS03jo3F1RvEJVigYSXZhkFFwRRxuUs70jD/zGYbO FIKzkQAr0cY7Dphkos3H8Rneyd87kJ7f1LDLNnTDXU/LaGWzZSaxJFqbTlRPL/Pr HC6oRtwhD1FDEZO74lxfRDrlWiX6xBHsB+uOhTHM65e7whWO216YQDS8hyxHcnUb fV51tuo3Fs5Hlb9nsYnFS7hE4YEQ3Tmq2fI/wHSesmMm14U3DMkhIvUff8dZLRc3 Wp/3XsRPfHuh1kZCHi4VDUeHSY07W1uqkBqrYBOXugNc7ZLiVhQV5lCRFMJPPvCz wS0d0CUNhxa7tcXu/GLaMCm5CsUkovC1cC2YqqLqk8PtfABX1OCZZadn4qUk53wl hlMER8mbyF0Ypw== =mlOG -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSTUe4ACgkQYKtH/8kJ UidTRBAAnWhSOO8MaR7tmDnJO7ldOcUYWpoWViLM4Cgt6WLt0HM5F3Dre0PtTgWS Fv0CCIuRVDk9UK2Sg3XG27aOkJmGgK2s5ZHROfk2WlacOXkLL3/C3ieZcXRom5rn BQXAXLGd1sgTHQ7VSLDYApw//XpwmSczE7HeYZ+96z0XUuCFgQJgAHWisN7cPc4m PjY55BIZKLvVCFRb09Zu8uZaXYtp/w8EEmgYioV2PbuM4nbdjb32ivs76G3+A80T 8gLqx5AO/0kx3roZSlgP9AgHAXy2snT42Hc+o/1EiblwKICXv/wmVFP3Z2a8596y y81kPfgARm09YV/9ehKoJVxxYEmG3i97SA1ATc5Y7whtmGSB+11AFZyedf6iaXk1 MT6AIKNgVES6Xa5kIJ2DgxCaUMe7VhvfohN8VIaeqDY4Iyo/XwlW4RsWId5saL5a BPSlLBplhKYdy8O9H0WDEc+c1Gkk8zT/O5rA6rITmbqF8sMvzyKTEtslyx5vPzp4 ZaiD6XMQHFNQUC1v4i+zV5MkYoTT04ML4GGwd8AjkVPQUSaOUOBMDP9cHEWttFpT NLdk36ZSu1Yz/dahBHTHrwCvejcTl7V+KoB1Fhc19sK1wZIVfdd2jt4sjm+QLr2T 3cxcjnvozKtyRCcEt1+r9BpnF6t05eSGNS0ZS124MS61wwewKqY= =rooh -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v6.5-rc1 This adds initial support for identifying the Tegra264 SoC family and fixes potential issues when reading from the FUSE block. A new software wake event for the AON cluster is added on Tegra234 and the debugfs initialization is drastically simplified. * tag 'tegra-for-6.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Use devm_clk_notifier_register() soc/tegra: pmc: Simplify debugfs initialization soc/tegra: fuse: Fix Tegra234 fuse size soc/tegra: pmc: Add AON SW Wake support for Tegra234 soc/tegra: fuse: Add support for Tegra264 Link: https://lore.kernel.org/r/20230609193620.2275240-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
bc889e870e
@ -663,7 +663,7 @@ static const struct nvmem_keepout tegra234_fuse_keepouts[] = {
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static const struct tegra_fuse_info tegra234_fuse_info = {
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.read = tegra30_fuse_read,
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.size = 0x98c,
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.size = 0xf90,
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.spare = 0x280,
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};
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/export.h>
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@ -62,6 +62,7 @@ bool tegra_is_silicon(void)
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switch (tegra_get_chip_id()) {
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case TEGRA194:
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case TEGRA234:
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case TEGRA264:
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if (tegra_get_platform() == 0)
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return true;
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@ -396,7 +396,6 @@ struct tegra_pmc_soc {
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* @clk: pointer to pclk clock
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* @soc: pointer to SoC data structure
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* @tz_only: flag specifying if the PMC can only be accessed via TrustZone
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* @debugfs: pointer to debugfs entry
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* @rate: currently configured rate of pclk
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* @suspend_mode: lowest suspend mode available
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* @cpu_good_time: CPU power good time (in microseconds)
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@ -431,7 +430,6 @@ struct tegra_pmc {
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void __iomem *aotag;
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void __iomem *scratch;
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struct clk *clk;
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struct dentry *debugfs;
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const struct tegra_pmc_soc *soc;
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bool tz_only;
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@ -1190,16 +1188,6 @@ static int powergate_show(struct seq_file *s, void *data)
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DEFINE_SHOW_ATTRIBUTE(powergate);
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static int tegra_powergate_debugfs_init(void)
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{
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pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
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&powergate_fops);
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if (!pmc->debugfs)
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return -ENOMEM;
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return 0;
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}
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static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
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struct device_node *np)
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{
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@ -3004,7 +2992,8 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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*/
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if (pmc->clk) {
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pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
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err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
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err = devm_clk_notifier_register(&pdev->dev, pmc->clk,
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&pmc->clk_nb);
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if (err) {
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dev_err(&pdev->dev,
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"failed to register clk notifier\n");
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@ -3026,19 +3015,13 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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tegra_pmc_reset_sysfs_init(pmc);
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if (IS_ENABLED(CONFIG_DEBUG_FS)) {
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err = tegra_powergate_debugfs_init();
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if (err < 0)
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goto cleanup_sysfs;
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}
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err = tegra_pmc_pinctrl_init(pmc);
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if (err)
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goto cleanup_debugfs;
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goto cleanup_sysfs;
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err = tegra_pmc_regmap_init(pmc);
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if (err < 0)
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goto cleanup_debugfs;
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goto cleanup_sysfs;
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err = tegra_powergate_init(pmc, pdev->dev.of_node);
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if (err < 0)
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@ -3061,16 +3044,15 @@ static int tegra_pmc_probe(struct platform_device *pdev)
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if (pmc->soc->set_wake_filters)
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pmc->soc->set_wake_filters(pmc);
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debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops);
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return 0;
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cleanup_powergates:
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tegra_powergate_remove_all(pdev->dev.of_node);
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cleanup_debugfs:
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debugfs_remove(pmc->debugfs);
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cleanup_sysfs:
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device_remove_file(&pdev->dev, &dev_attr_reset_reason);
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device_remove_file(&pdev->dev, &dev_attr_reset_level);
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clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
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return err;
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}
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@ -4250,6 +4232,7 @@ static const struct tegra_wake_event tegra234_wake_events[] = {
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TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
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TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)),
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TEGRA_WAKE_IRQ("rtc", 73, 10),
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TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),
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};
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static const struct tegra_pmc_soc tegra234_pmc_soc = {
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __SOC_TEGRA_FUSE_H__
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@ -17,6 +17,7 @@
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#define TEGRA186 0x18
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#define TEGRA194 0x19
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#define TEGRA234 0x23
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#define TEGRA264 0x26
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#define TEGRA_FUSE_SKU_CALIB_0 0xf0
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#define TEGRA30_FUSE_SATA_CALIB 0x124
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