This pull request contains Broadcom SoCs drivers changes for 5.10,
please pull the following: - Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller and adds support for the 6318, 6328, 6362, 63268. - Florian adds support for tuning the Bus Interface Unit on 72164 and 72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the 64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB driver to support breakpoint notifications. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAl9ZkK4ACgkQh9CWnEQH BwS8bQ//dn66KKeK2Fcw6pofTypsE7y69P2Jz7vA8IkYigNaNwIWABXXE+/FXrPE ZVk9se/ZAI/kvWQXKj5T2JyjXWU8jphidwX0aK1xUymab60W6EdZUJcTiKdsdamA KGSAQ0jjWaNuZHnNR2nsqa4OLDrnQz2ujdWCnz9SSBNtPFcAknbj+nkicbpWmHb7 1fjBXg7e+RkUuaHGNETIkKnjdEA/e2frlTCzwendsLTgJkhbr9j9y6jAOtJiXjE4 +UQd84cEPsuvSrx6dx6pnCVoL19m2aPFE9JTDVCXVYCOinjm+gQDXQTl8w+HvoZn /w0deVOJSOF+YHoRbC7xLghaY2jjRmM86jjmopSB7/OF5KUbkuMj1Nz5xQxUI7gA BuvRQvry+TedEiY1vfsDnrJZpv3vZTS2BRkTfiZXvhtfDM/unMr9L6vScxzQU7gA Gj2hPEai3bB+pfTB+e1H4IAWFmQXgS+3Q+JpCtgHjZFZtmYy89MaJK5TY88pYceR ZfnK6aHhHXNF3L594CYCNxZBovC2Jt/Mp6+MIPgFpvwTFKhqoLIjUP5bnuZRqHZ6 yVz0WJgU6R7FPtp8uTwES5moreeAWMdVdzHdZvTkOrPzRvBpT1tMWpk00eFaAn7E PlTdM5OMuxDi2tZKcLNCW92To1Un0YRnMLZh8Q5sSS9MekY++hk= =njcZ -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux into arm/drivers This pull request contains Broadcom SoCs drivers changes for 5.10, please pull the following: - Alvaro adds support for the BCM63xx (DSL) SoCs power domain controller and adds support for the 6318, 6328, 6362, 63268. - Florian adds support for tuning the Bus Interface Unit on 72164 and 72165, enables the Brahma-B53 and Cortex-A72 read-ahead cache for the 64-bit capable ARCH_BRCMSTB platforms, and finally updates the GISB driver to support breakpoint notifications. * tag 'arm-soc/for-5.10/drivers' of https://github.com/Broadcom/stblinux: bus: brcmstb_gisb: Add support for breakpoint interrupts dt-bindings: bus: Document breakpoint interrupt for gisb-arb soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 MIPS: BMIPS: dts: add BCM63268 power domain support MIPS: BMIPS: dts: add BCM6362 power domain support MIPS: BMIPS: dts: add BCM6328 power domain support soc: bcm: add BCM63xx power domain driver MIPS: BMIPS: add BCM6318 power domain definitions MIPS: BMIPS: add BCM63268 power domain definitions MIPS: BMIPS: add BCM6362 power domain definitions MIPS: BMIPS: add BCM6328 power domain definitions dt-bindings: soc: brcm: add BCM63xx power domain binding soc: bcm: brcmstb: biuctrl: Enable Read-ahead cache bus: brcmstb_gisb: Shorten prints Link: https://lore.kernel.org/r/20200912032153.1216354-3-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
bd2fad8cd3
@ -10,7 +10,8 @@ Required properties:
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"brcm,bcm7038-gisb-arb" for 130nm chips
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- reg: specifies the base physical address and size of the registers
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- interrupts: specifies the two interrupts (timeout and TEA) to be used from
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the parent interrupt controller
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the parent interrupt controller. A third optional interrupt may be specified
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for breakpoints.
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Optional properties:
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@ -0,0 +1,44 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/power/brcm,bcm63xx-power.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: BCM63xx power domain driver
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maintainers:
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- Álvaro Fernández Rojas <noltari@gmail.com>
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description: |
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BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
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to enable/disable certain components in order to save power.
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properties:
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compatible:
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items:
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- enum:
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- brcm,bcm6318-power-controller
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- brcm,bcm6328-power-controller
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- brcm,bcm6362-power-controller
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- brcm,bcm63268-power-controller
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reg:
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maxItems: 1
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"#power-domain-cells":
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const: 1
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required:
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- compatible
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- reg
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- "#power-domain-cells"
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additionalProperties: false
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examples:
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- |
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periph_pwr: power-controller@10001848 {
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compatible = "brcm,bcm6328-power-controller";
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reg = <0x10001848 0x4>;
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#power-domain-cells = <1>;
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};
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@ -3491,6 +3491,7 @@ F: arch/mips/bmips/*
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F: arch/mips/boot/dts/brcm/bcm*.dts*
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F: arch/mips/include/asm/mach-bmips/*
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F: arch/mips/kernel/*bmips*
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F: drivers/soc/bcm/bcm63xx
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F: drivers/irqchip/irq-bcm63*
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F: drivers/irqchip/irq-bcm7*
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F: drivers/irqchip/irq-brcmstb*
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@ -117,6 +117,12 @@
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status = "disabled";
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};
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periph_pwr: power-controller@1000184c {
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compatible = "brcm,bcm6328-power-controller";
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reg = <0x1000184c 0x4>;
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#power-domain-cells = <1>;
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};
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ehci: usb@10002500 {
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compatible = "brcm,bcm63268-ehci", "generic-ehci";
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reg = <0x10002500 0x100>;
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@ -110,6 +110,12 @@
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status = "disabled";
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};
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periph_pwr: power-controller@10001848 {
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compatible = "brcm,bcm6328-power-controller";
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reg = <0x10001848 0x4>;
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#power-domain-cells = <1>;
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};
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ehci: usb@10002500 {
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compatible = "brcm,bcm6328-ehci", "generic-ehci";
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reg = <0x10002500 0x100>;
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@ -108,6 +108,12 @@
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status = "disabled";
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};
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periph_pwr: power-controller@10001848 {
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compatible = "brcm,bcm6362-power-controller";
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reg = <0x10001848 0x4>;
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#power-domain-cells = <1>;
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};
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leds0: led-controller@10001900 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -30,8 +30,22 @@
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#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
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#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
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#define ARB_BP_CAP_CLEAR (1 << 0)
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#define ARB_BP_CAP_STATUS_PROT_SHIFT 14
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#define ARB_BP_CAP_STATUS_TYPE (1 << 13)
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#define ARB_BP_CAP_STATUS_RSP_SHIFT 10
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#define ARB_BP_CAP_STATUS_MASK GENMASK(1, 0)
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#define ARB_BP_CAP_STATUS_BS_SHIFT 2
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#define ARB_BP_CAP_STATUS_WRITE (1 << 1)
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#define ARB_BP_CAP_STATUS_VALID (1 << 0)
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enum {
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ARB_TIMER,
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ARB_BP_CAP_CLR,
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ARB_BP_CAP_HI_ADDR,
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ARB_BP_CAP_ADDR,
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ARB_BP_CAP_STATUS,
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ARB_BP_CAP_MASTER,
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ARB_ERR_CAP_CLR,
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ARB_ERR_CAP_HI_ADDR,
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ARB_ERR_CAP_ADDR,
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@ -41,6 +55,11 @@ enum {
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static const int gisb_offsets_bcm7038[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_BP_CAP_CLR] = 0x014,
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[ARB_BP_CAP_HI_ADDR] = -1,
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[ARB_BP_CAP_ADDR] = 0x0b8,
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[ARB_BP_CAP_STATUS] = 0x0c0,
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[ARB_BP_CAP_MASTER] = -1,
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[ARB_ERR_CAP_CLR] = 0x0c4,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x0c8,
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@ -50,6 +69,11 @@ static const int gisb_offsets_bcm7038[] = {
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static const int gisb_offsets_bcm7278[] = {
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[ARB_TIMER] = 0x008,
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[ARB_BP_CAP_CLR] = 0x01c,
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[ARB_BP_CAP_HI_ADDR] = -1,
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[ARB_BP_CAP_ADDR] = 0x220,
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[ARB_BP_CAP_STATUS] = 0x230,
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[ARB_BP_CAP_MASTER] = 0x234,
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[ARB_ERR_CAP_CLR] = 0x7f8,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x7e0,
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@ -59,6 +83,11 @@ static const int gisb_offsets_bcm7278[] = {
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static const int gisb_offsets_bcm7400[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_BP_CAP_CLR] = 0x014,
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[ARB_BP_CAP_HI_ADDR] = -1,
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[ARB_BP_CAP_ADDR] = 0x0b8,
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[ARB_BP_CAP_STATUS] = 0x0c0,
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[ARB_BP_CAP_MASTER] = 0x0c4,
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[ARB_ERR_CAP_CLR] = 0x0c8,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x0cc,
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@ -68,6 +97,11 @@ static const int gisb_offsets_bcm7400[] = {
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static const int gisb_offsets_bcm7435[] = {
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[ARB_TIMER] = 0x00c,
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[ARB_BP_CAP_CLR] = 0x014,
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[ARB_BP_CAP_HI_ADDR] = -1,
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[ARB_BP_CAP_ADDR] = 0x158,
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[ARB_BP_CAP_STATUS] = 0x160,
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[ARB_BP_CAP_MASTER] = 0x164,
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[ARB_ERR_CAP_CLR] = 0x168,
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[ARB_ERR_CAP_HI_ADDR] = -1,
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[ARB_ERR_CAP_ADDR] = 0x16c,
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@ -77,6 +111,11 @@ static const int gisb_offsets_bcm7435[] = {
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static const int gisb_offsets_bcm7445[] = {
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[ARB_TIMER] = 0x008,
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[ARB_BP_CAP_CLR] = 0x010,
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[ARB_BP_CAP_HI_ADDR] = -1,
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[ARB_BP_CAP_ADDR] = 0x1d8,
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[ARB_BP_CAP_STATUS] = 0x1e0,
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[ARB_BP_CAP_MASTER] = 0x1e4,
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[ARB_ERR_CAP_CLR] = 0x7e4,
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[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
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[ARB_ERR_CAP_ADDR] = 0x7ec,
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@ -125,6 +164,16 @@ static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
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return value;
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}
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static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
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{
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u64 value;
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value = gisb_read(gdev, ARB_BP_CAP_ADDR);
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value |= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;
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return value;
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}
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static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
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{
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int offset = gdev->gisb_offsets[reg];
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@ -210,8 +259,8 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
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m_name = m_fmt;
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}
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pr_crit("%s: %s at 0x%llx [%c %s], core: %s\n",
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__func__, reason, arb_addr,
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pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
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reason, arb_addr,
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cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
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cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
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m_name);
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@ -259,6 +308,41 @@ static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
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{
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struct brcmstb_gisb_arb_device *gdev = dev_id;
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const char *m_name;
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u32 bp_status;
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u64 arb_addr;
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u32 master;
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char m_fmt[11];
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bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);
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/* Invalid captured address, bail out */
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if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
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return IRQ_HANDLED;
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/* Read the address and master */
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arb_addr = gisb_read_bp_address(gdev);
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master = gisb_read(gdev, ARB_BP_CAP_MASTER);
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m_name = brcmstb_gisb_master_to_str(gdev, master);
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if (!m_name) {
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snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
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m_name = m_fmt;
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}
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pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
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arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
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m_name);
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/* clear the GISB error */
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gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
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return IRQ_HANDLED;
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}
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/*
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* Dump out gisb errors on die or panic.
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*/
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@ -317,13 +401,14 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
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struct brcmstb_gisb_arb_device *gdev;
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const struct of_device_id *of_id;
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struct resource *r;
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int err, timeout_irq, tea_irq;
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int err, timeout_irq, tea_irq, bp_irq;
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unsigned int num_masters, j = 0;
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int i, first, last;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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timeout_irq = platform_get_irq(pdev, 0);
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tea_irq = platform_get_irq(pdev, 1);
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bp_irq = platform_get_irq(pdev, 2);
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gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
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if (!gdev)
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@ -356,6 +441,15 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
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if (err < 0)
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return err;
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/* Interrupt is optional */
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if (bp_irq > 0) {
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err = devm_request_irq(&pdev->dev, bp_irq,
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brcmstb_gisb_bp_handler, 0, pdev->name,
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gdev);
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if (err < 0)
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return err;
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}
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/* If we do not have a valid mask, assume all masters are enabled */
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if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
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&gdev->valid_mask))
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@ -22,6 +22,15 @@ config RASPBERRYPI_POWER
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This enables support for the RPi power domains which can be enabled
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or disabled via the RPi firmware.
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config SOC_BCM63XX
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bool "Broadcom 63xx SoC drivers"
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depends on BMIPS_GENERIC || COMPILE_TEST
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help
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Enables drivers for the Broadcom 63xx series of chips.
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Drivers can be enabled individually within this menu.
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If unsure, say N.
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config SOC_BRCMSTB
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bool "Broadcom STB SoC drivers"
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depends on ARM || ARM64 || BMIPS_GENERIC || COMPILE_TEST
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@ -33,6 +42,7 @@ config SOC_BRCMSTB
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If unsure, say N.
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source "drivers/soc/bcm/bcm63xx/Kconfig"
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source "drivers/soc/bcm/brcmstb/Kconfig"
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endmenu
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@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_BCM2835_POWER) += bcm2835-power.o
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obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o
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obj-$(CONFIG_SOC_BCM63XX) += bcm63xx/
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obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/
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12
drivers/soc/bcm/bcm63xx/Kconfig
Normal file
12
drivers/soc/bcm/bcm63xx/Kconfig
Normal file
@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-only
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if SOC_BCM63XX
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|
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config BCM63XX_POWER
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bool "BCM63xx power domain driver"
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depends on BMIPS_GENERIC || (COMPILE_TEST && OF)
|
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select PM_GENERIC_DOMAINS if PM
|
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help
|
||||
This enables support for the BCM63xx power domains controller on
|
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BCM6318, BCM6328, BCM6362 and BCM63268 SoCs.
|
||||
|
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endif # SOC_BCM63XX
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2
drivers/soc/bcm/bcm63xx/Makefile
Normal file
2
drivers/soc/bcm/bcm63xx/Makefile
Normal file
@ -0,0 +1,2 @@
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||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_BCM63XX_POWER) += bcm63xx-power.o
|
||||
378
drivers/soc/bcm/bcm63xx/bcm63xx-power.c
Normal file
378
drivers/soc/bcm/bcm63xx/bcm63xx-power.c
Normal file
@ -0,0 +1,378 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* BCM63xx Power Domain Controller Driver
|
||||
*
|
||||
* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/soc/bcm6318-pm.h>
|
||||
#include <dt-bindings/soc/bcm6328-pm.h>
|
||||
#include <dt-bindings/soc/bcm6362-pm.h>
|
||||
#include <dt-bindings/soc/bcm63268-pm.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
struct bcm63xx_power_dev {
|
||||
struct generic_pm_domain genpd;
|
||||
struct bcm63xx_power *power;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
struct bcm63xx_power {
|
||||
void __iomem *base;
|
||||
spinlock_t lock;
|
||||
struct bcm63xx_power_dev *dev;
|
||||
struct genpd_onecell_data genpd_data;
|
||||
struct generic_pm_domain **genpd;
|
||||
};
|
||||
|
||||
struct bcm63xx_power_data {
|
||||
const char * const name;
|
||||
uint8_t bit;
|
||||
unsigned int flags;
|
||||
};
|
||||
|
||||
static int bcm63xx_power_get_state(struct bcm63xx_power_dev *pmd, bool *is_on)
|
||||
{
|
||||
struct bcm63xx_power *power = pmd->power;
|
||||
|
||||
if (!pmd->mask) {
|
||||
*is_on = false;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*is_on = !(__raw_readl(power->base) & pmd->mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_power_set_state(struct bcm63xx_power_dev *pmd, bool on)
|
||||
{
|
||||
struct bcm63xx_power *power = pmd->power;
|
||||
unsigned long flags;
|
||||
uint32_t val;
|
||||
|
||||
if (!pmd->mask)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&power->lock, flags);
|
||||
val = __raw_readl(power->base);
|
||||
if (on)
|
||||
val &= ~pmd->mask;
|
||||
else
|
||||
val |= pmd->mask;
|
||||
__raw_writel(val, power->base);
|
||||
spin_unlock_irqrestore(&power->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_power_on(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct bcm63xx_power_dev *pmd = container_of(genpd,
|
||||
struct bcm63xx_power_dev, genpd);
|
||||
|
||||
return bcm63xx_power_set_state(pmd, true);
|
||||
}
|
||||
|
||||
static int bcm63xx_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct bcm63xx_power_dev *pmd = container_of(genpd,
|
||||
struct bcm63xx_power_dev, genpd);
|
||||
|
||||
return bcm63xx_power_set_state(pmd, false);
|
||||
}
|
||||
|
||||
static int bcm63xx_power_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource *res;
|
||||
const struct bcm63xx_power_data *entry, *table;
|
||||
struct bcm63xx_power *power;
|
||||
unsigned int ndom;
|
||||
uint8_t max_bit = 0;
|
||||
int ret;
|
||||
|
||||
power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
|
||||
if (!power)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
power->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(power->base))
|
||||
return PTR_ERR(power->base);
|
||||
|
||||
table = of_device_get_match_data(dev);
|
||||
if (!table)
|
||||
return -EINVAL;
|
||||
|
||||
power->genpd_data.num_domains = 0;
|
||||
ndom = 0;
|
||||
for (entry = table; entry->name; entry++) {
|
||||
max_bit = max(max_bit, entry->bit);
|
||||
ndom++;
|
||||
}
|
||||
|
||||
if (!ndom)
|
||||
return -ENODEV;
|
||||
|
||||
power->genpd_data.num_domains = max_bit + 1;
|
||||
|
||||
power->dev = devm_kcalloc(dev, power->genpd_data.num_domains,
|
||||
sizeof(struct bcm63xx_power_dev),
|
||||
GFP_KERNEL);
|
||||
if (!power->dev)
|
||||
return -ENOMEM;
|
||||
|
||||
power->genpd = devm_kcalloc(dev, power->genpd_data.num_domains,
|
||||
sizeof(struct generic_pm_domain *),
|
||||
GFP_KERNEL);
|
||||
if (!power->genpd)
|
||||
return -ENOMEM;
|
||||
|
||||
power->genpd_data.domains = power->genpd;
|
||||
|
||||
ndom = 0;
|
||||
for (entry = table; entry->name; entry++) {
|
||||
struct bcm63xx_power_dev *pmd = &power->dev[ndom];
|
||||
bool is_on;
|
||||
|
||||
pmd->power = power;
|
||||
pmd->mask = BIT(entry->bit);
|
||||
pmd->genpd.name = entry->name;
|
||||
pmd->genpd.flags = entry->flags;
|
||||
|
||||
ret = bcm63xx_power_get_state(pmd, &is_on);
|
||||
if (ret)
|
||||
dev_warn(dev, "unable to get current state for %s\n",
|
||||
pmd->genpd.name);
|
||||
|
||||
pmd->genpd.power_on = bcm63xx_power_on;
|
||||
pmd->genpd.power_off = bcm63xx_power_off;
|
||||
|
||||
pm_genpd_init(&pmd->genpd, NULL, !is_on);
|
||||
power->genpd[entry->bit] = &pmd->genpd;
|
||||
|
||||
ndom++;
|
||||
}
|
||||
|
||||
spin_lock_init(&power->lock);
|
||||
|
||||
ret = of_genpd_add_provider_onecell(np, &power->genpd_data);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register genpd driver: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(dev, "registered %u power domains\n", ndom);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct bcm63xx_power_data bcm6318_power_domains[] = {
|
||||
{
|
||||
.name = "pcie",
|
||||
.bit = BCM6318_POWER_DOMAIN_PCIE,
|
||||
}, {
|
||||
.name = "usb",
|
||||
.bit = BCM6318_POWER_DOMAIN_USB,
|
||||
}, {
|
||||
.name = "ephy0",
|
||||
.bit = BCM6318_POWER_DOMAIN_EPHY0,
|
||||
}, {
|
||||
.name = "ephy1",
|
||||
.bit = BCM6318_POWER_DOMAIN_EPHY1,
|
||||
}, {
|
||||
.name = "ephy2",
|
||||
.bit = BCM6318_POWER_DOMAIN_EPHY2,
|
||||
}, {
|
||||
.name = "ephy3",
|
||||
.bit = BCM6318_POWER_DOMAIN_EPHY3,
|
||||
}, {
|
||||
.name = "ldo2p5",
|
||||
.bit = BCM6318_POWER_DOMAIN_LDO2P5,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "ldo2p9",
|
||||
.bit = BCM6318_POWER_DOMAIN_LDO2P9,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "sw1p0",
|
||||
.bit = BCM6318_POWER_DOMAIN_SW1P0,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "pad",
|
||||
.bit = BCM6318_POWER_DOMAIN_PAD,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
|
||||
static const struct bcm63xx_power_data bcm6328_power_domains[] = {
|
||||
{
|
||||
.name = "adsl2-mips",
|
||||
.bit = BCM6328_POWER_DOMAIN_ADSL2_MIPS,
|
||||
}, {
|
||||
.name = "adsl2-phy",
|
||||
.bit = BCM6328_POWER_DOMAIN_ADSL2_PHY,
|
||||
}, {
|
||||
.name = "adsl2-afe",
|
||||
.bit = BCM6328_POWER_DOMAIN_ADSL2_AFE,
|
||||
}, {
|
||||
.name = "sar",
|
||||
.bit = BCM6328_POWER_DOMAIN_SAR,
|
||||
}, {
|
||||
.name = "pcm",
|
||||
.bit = BCM6328_POWER_DOMAIN_PCM,
|
||||
}, {
|
||||
.name = "usbd",
|
||||
.bit = BCM6328_POWER_DOMAIN_USBD,
|
||||
}, {
|
||||
.name = "usbh",
|
||||
.bit = BCM6328_POWER_DOMAIN_USBH,
|
||||
}, {
|
||||
.name = "pcie",
|
||||
.bit = BCM6328_POWER_DOMAIN_PCIE,
|
||||
}, {
|
||||
.name = "robosw",
|
||||
.bit = BCM6328_POWER_DOMAIN_ROBOSW,
|
||||
}, {
|
||||
.name = "ephy",
|
||||
.bit = BCM6328_POWER_DOMAIN_EPHY,
|
||||
}, {
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
|
||||
static const struct bcm63xx_power_data bcm6362_power_domains[] = {
|
||||
{
|
||||
.name = "sar",
|
||||
.bit = BCM6362_POWER_DOMAIN_SAR,
|
||||
}, {
|
||||
.name = "ipsec",
|
||||
.bit = BCM6362_POWER_DOMAIN_IPSEC,
|
||||
}, {
|
||||
.name = "mips",
|
||||
.bit = BCM6362_POWER_DOMAIN_MIPS,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "dect",
|
||||
.bit = BCM6362_POWER_DOMAIN_DECT,
|
||||
}, {
|
||||
.name = "usbh",
|
||||
.bit = BCM6362_POWER_DOMAIN_USBH,
|
||||
}, {
|
||||
.name = "usbd",
|
||||
.bit = BCM6362_POWER_DOMAIN_USBD,
|
||||
}, {
|
||||
.name = "robosw",
|
||||
.bit = BCM6362_POWER_DOMAIN_ROBOSW,
|
||||
}, {
|
||||
.name = "pcm",
|
||||
.bit = BCM6362_POWER_DOMAIN_PCM,
|
||||
}, {
|
||||
.name = "periph",
|
||||
.bit = BCM6362_POWER_DOMAIN_PERIPH,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "adsl-phy",
|
||||
.bit = BCM6362_POWER_DOMAIN_ADSL_PHY,
|
||||
}, {
|
||||
.name = "gmii-pads",
|
||||
.bit = BCM6362_POWER_DOMAIN_GMII_PADS,
|
||||
}, {
|
||||
.name = "fap",
|
||||
.bit = BCM6362_POWER_DOMAIN_FAP,
|
||||
}, {
|
||||
.name = "pcie",
|
||||
.bit = BCM6362_POWER_DOMAIN_PCIE,
|
||||
}, {
|
||||
.name = "wlan-pads",
|
||||
.bit = BCM6362_POWER_DOMAIN_WLAN_PADS,
|
||||
}, {
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
|
||||
static const struct bcm63xx_power_data bcm63268_power_domains[] = {
|
||||
{
|
||||
.name = "sar",
|
||||
.bit = BCM63268_POWER_DOMAIN_SAR,
|
||||
}, {
|
||||
.name = "ipsec",
|
||||
.bit = BCM63268_POWER_DOMAIN_IPSEC,
|
||||
}, {
|
||||
.name = "mips",
|
||||
.bit = BCM63268_POWER_DOMAIN_MIPS,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "dect",
|
||||
.bit = BCM63268_POWER_DOMAIN_DECT,
|
||||
}, {
|
||||
.name = "usbh",
|
||||
.bit = BCM63268_POWER_DOMAIN_USBH,
|
||||
}, {
|
||||
.name = "usbd",
|
||||
.bit = BCM63268_POWER_DOMAIN_USBD,
|
||||
}, {
|
||||
.name = "robosw",
|
||||
.bit = BCM63268_POWER_DOMAIN_ROBOSW,
|
||||
}, {
|
||||
.name = "pcm",
|
||||
.bit = BCM63268_POWER_DOMAIN_PCM,
|
||||
}, {
|
||||
.name = "periph",
|
||||
.bit = BCM63268_POWER_DOMAIN_PERIPH,
|
||||
.flags = GENPD_FLAG_ALWAYS_ON,
|
||||
}, {
|
||||
.name = "vdsl-phy",
|
||||
.bit = BCM63268_POWER_DOMAIN_VDSL_PHY,
|
||||
}, {
|
||||
.name = "vdsl-mips",
|
||||
.bit = BCM63268_POWER_DOMAIN_VDSL_MIPS,
|
||||
}, {
|
||||
.name = "fap",
|
||||
.bit = BCM63268_POWER_DOMAIN_FAP,
|
||||
}, {
|
||||
.name = "pcie",
|
||||
.bit = BCM63268_POWER_DOMAIN_PCIE,
|
||||
}, {
|
||||
.name = "wlan-pads",
|
||||
.bit = BCM63268_POWER_DOMAIN_WLAN_PADS,
|
||||
}, {
|
||||
/* sentinel */
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id bcm63xx_power_of_match[] = {
|
||||
{
|
||||
.compatible = "brcm,bcm6318-power-controller",
|
||||
.data = &bcm6318_power_domains,
|
||||
}, {
|
||||
.compatible = "brcm,bcm6328-power-controller",
|
||||
.data = &bcm6328_power_domains,
|
||||
}, {
|
||||
.compatible = "brcm,bcm6362-power-controller",
|
||||
.data = &bcm6362_power_domains,
|
||||
}, {
|
||||
.compatible = "brcm,bcm63268-power-controller",
|
||||
.data = &bcm63268_power_domains,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver bcm63xx_power_driver = {
|
||||
.driver = {
|
||||
.name = "bcm63xx-power-controller",
|
||||
.of_match_table = bcm63xx_power_of_match,
|
||||
},
|
||||
.probe = bcm63xx_power_probe,
|
||||
};
|
||||
builtin_platform_driver(bcm63xx_power_driver);
|
||||
@ -13,6 +13,22 @@
|
||||
#include <linux/syscore_ops.h>
|
||||
#include <linux/soc/brcmstb/brcmstb.h>
|
||||
|
||||
#define RACENPREF_MASK 0x3
|
||||
#define RACPREFINST_SHIFT 0
|
||||
#define RACENINST_SHIFT 2
|
||||
#define RACPREFDATA_SHIFT 4
|
||||
#define RACENDATA_SHIFT 6
|
||||
#define RAC_CPU_SHIFT 8
|
||||
#define RACCFG_MASK 0xff
|
||||
#define DPREF_LINE_2_SHIFT 24
|
||||
#define DPREF_LINE_2_MASK 0xff
|
||||
|
||||
/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
|
||||
#define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
|
||||
RACENPREF_MASK << RACENINST_SHIFT | \
|
||||
1 << RACPREFDATA_SHIFT | \
|
||||
RACENPREF_MASK << RACENDATA_SHIFT)
|
||||
|
||||
#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
|
||||
#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
|
||||
#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
|
||||
@ -31,11 +47,21 @@ static void __iomem *cpubiuctrl_base;
|
||||
static bool mcp_wr_pairing_en;
|
||||
static const int *cpubiuctrl_regs;
|
||||
|
||||
enum cpubiuctrl_regs {
|
||||
CPU_CREDIT_REG = 0,
|
||||
CPU_MCP_FLOW_REG,
|
||||
CPU_WRITEBACK_CTRL_REG,
|
||||
RAC_CONFIG0_REG,
|
||||
RAC_CONFIG1_REG,
|
||||
NUM_CPU_BIUCTRL_REGS,
|
||||
};
|
||||
|
||||
static inline u32 cbc_readl(int reg)
|
||||
{
|
||||
int offset = cpubiuctrl_regs[reg];
|
||||
|
||||
if (offset == -1)
|
||||
if (offset == -1 ||
|
||||
(IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
|
||||
return (u32)-1;
|
||||
|
||||
return readl_relaxed(cpubiuctrl_base + offset);
|
||||
@ -45,22 +71,19 @@ static inline void cbc_writel(u32 val, int reg)
|
||||
{
|
||||
int offset = cpubiuctrl_regs[reg];
|
||||
|
||||
if (offset == -1)
|
||||
if (offset == -1 ||
|
||||
(IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
|
||||
return;
|
||||
|
||||
writel(val, cpubiuctrl_base + offset);
|
||||
}
|
||||
|
||||
enum cpubiuctrl_regs {
|
||||
CPU_CREDIT_REG = 0,
|
||||
CPU_MCP_FLOW_REG,
|
||||
CPU_WRITEBACK_CTRL_REG
|
||||
};
|
||||
|
||||
static const int b15_cpubiuctrl_regs[] = {
|
||||
[CPU_CREDIT_REG] = 0x184,
|
||||
[CPU_MCP_FLOW_REG] = -1,
|
||||
[CPU_WRITEBACK_CTRL_REG] = -1,
|
||||
[RAC_CONFIG0_REG] = -1,
|
||||
[RAC_CONFIG1_REG] = -1,
|
||||
};
|
||||
|
||||
/* Odd cases, e.g: 7260A0 */
|
||||
@ -68,22 +91,26 @@ static const int b53_cpubiuctrl_no_wb_regs[] = {
|
||||
[CPU_CREDIT_REG] = 0x0b0,
|
||||
[CPU_MCP_FLOW_REG] = 0x0b4,
|
||||
[CPU_WRITEBACK_CTRL_REG] = -1,
|
||||
[RAC_CONFIG0_REG] = 0x78,
|
||||
[RAC_CONFIG1_REG] = 0x7c,
|
||||
};
|
||||
|
||||
static const int b53_cpubiuctrl_regs[] = {
|
||||
[CPU_CREDIT_REG] = 0x0b0,
|
||||
[CPU_MCP_FLOW_REG] = 0x0b4,
|
||||
[CPU_WRITEBACK_CTRL_REG] = 0x22c,
|
||||
[RAC_CONFIG0_REG] = 0x78,
|
||||
[RAC_CONFIG1_REG] = 0x7c,
|
||||
};
|
||||
|
||||
static const int a72_cpubiuctrl_regs[] = {
|
||||
[CPU_CREDIT_REG] = 0x18,
|
||||
[CPU_MCP_FLOW_REG] = 0x1c,
|
||||
[CPU_WRITEBACK_CTRL_REG] = 0x20,
|
||||
[RAC_CONFIG0_REG] = 0x08,
|
||||
[RAC_CONFIG1_REG] = 0x0c,
|
||||
};
|
||||
|
||||
#define NUM_CPU_BIUCTRL_REGS 3
|
||||
|
||||
static int __init mcp_write_pairing_set(void)
|
||||
{
|
||||
u32 creds = 0;
|
||||
@ -110,6 +137,8 @@ static int __init mcp_write_pairing_set(void)
|
||||
static const u32 a72_b53_mach_compat[] = {
|
||||
0x7211,
|
||||
0x7216,
|
||||
0x72164,
|
||||
0x72165,
|
||||
0x7255,
|
||||
0x7260,
|
||||
0x7268,
|
||||
@ -117,6 +146,61 @@ static const u32 a72_b53_mach_compat[] = {
|
||||
0x7278,
|
||||
};
|
||||
|
||||
/* The read-ahead cache present in the Brahma-B53 CPU is a special piece of
|
||||
* hardware after the integrated L2 cache of the B53 CPU complex whose purpose
|
||||
* is to prefetch instruction and/or data with a line size of either 64 bytes
|
||||
* or 256 bytes. The rationale is that the data-bus of the CPU interface is
|
||||
* optimized for 256-byte transactions, and enabling the read-ahead cache
|
||||
* provides a significant performance boost (typically twice the performance
|
||||
* for a memcpy benchmark application).
|
||||
*
|
||||
* The read-ahead cache is transparent for Virtual Address cache maintenance
|
||||
* operations: IC IVAU, DC IVAC, DC CVAC, DC CVAU and DC CIVAC. So no special
|
||||
* handling is needed for the DMA API above and beyond what is included in the
|
||||
* arm64 implementation.
|
||||
*
|
||||
* In addition, since the Point of Unification is typically between L1 and L2
|
||||
* for the Brahma-B53 processor no special read-ahead cache handling is needed
|
||||
* for the IC IALLU and IC IALLUIS cache maintenance operations.
|
||||
*
|
||||
* However, it is not possible to specify the cache level (L3) for the cache
|
||||
* maintenance instructions operating by set/way to operate on the read-ahead
|
||||
* cache. The read-ahead cache will maintain coherency when inner cache lines
|
||||
* are cleaned by set/way, but if it is necessary to invalidate inner cache
|
||||
* lines by set/way to maintain coherency with system masters operating on
|
||||
* shared memory that does not have hardware support for coherency, then it
|
||||
* will also be necessary to explicitly invalidate the read-ahead cache.
|
||||
*/
|
||||
static void __init a72_b53_rac_enable_all(struct device_node *np)
|
||||
{
|
||||
unsigned int cpu;
|
||||
u32 enable = 0, pref_dist, shift;
|
||||
|
||||
if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
|
||||
return;
|
||||
|
||||
if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
|
||||
return;
|
||||
|
||||
pref_dist = cbc_readl(RAC_CONFIG1_REG);
|
||||
for_each_possible_cpu(cpu) {
|
||||
shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
|
||||
enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
|
||||
if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
|
||||
enable &= ~(RACENPREF_MASK << shift);
|
||||
enable |= 3 << shift;
|
||||
pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
cbc_writel(enable, RAC_CONFIG0_REG);
|
||||
cbc_writel(pref_dist, RAC_CONFIG1_REG);
|
||||
|
||||
pr_info("%pOF: Broadcom %s read-ahead cache\n",
|
||||
np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
|
||||
"Cortex-A72" : "Brahma-B53");
|
||||
}
|
||||
|
||||
static void __init mcp_a72_b53_set(void)
|
||||
{
|
||||
unsigned int i;
|
||||
@ -262,6 +346,7 @@ static int __init brcmstb_biuctrl_init(void)
|
||||
return ret;
|
||||
}
|
||||
|
||||
a72_b53_rac_enable_all(np);
|
||||
mcp_a72_b53_set();
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
|
||||
|
||||
17
include/dt-bindings/soc/bcm6318-pm.h
Normal file
17
include/dt-bindings/soc/bcm6318-pm.h
Normal file
@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef __DT_BINDINGS_BMIPS_BCM6318_PM_H
|
||||
#define __DT_BINDINGS_BMIPS_BCM6318_PM_H
|
||||
|
||||
#define BCM6318_POWER_DOMAIN_PCIE 0
|
||||
#define BCM6318_POWER_DOMAIN_USB 1
|
||||
#define BCM6318_POWER_DOMAIN_EPHY0 2
|
||||
#define BCM6318_POWER_DOMAIN_EPHY1 3
|
||||
#define BCM6318_POWER_DOMAIN_EPHY2 4
|
||||
#define BCM6318_POWER_DOMAIN_EPHY3 5
|
||||
#define BCM6318_POWER_DOMAIN_LDO2P5 6
|
||||
#define BCM6318_POWER_DOMAIN_LDO2P9 7
|
||||
#define BCM6318_POWER_DOMAIN_SW1P0 8
|
||||
#define BCM6318_POWER_DOMAIN_PAD 9
|
||||
|
||||
#endif /* __DT_BINDINGS_BMIPS_BCM6318_PM_H */
|
||||
21
include/dt-bindings/soc/bcm63268-pm.h
Normal file
21
include/dt-bindings/soc/bcm63268-pm.h
Normal file
@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef __DT_BINDINGS_BMIPS_BCM63268_PM_H
|
||||
#define __DT_BINDINGS_BMIPS_BCM63268_PM_H
|
||||
|
||||
#define BCM63268_POWER_DOMAIN_SAR 0
|
||||
#define BCM63268_POWER_DOMAIN_IPSEC 1
|
||||
#define BCM63268_POWER_DOMAIN_MIPS 2
|
||||
#define BCM63268_POWER_DOMAIN_DECT 3
|
||||
#define BCM63268_POWER_DOMAIN_USBH 4
|
||||
#define BCM63268_POWER_DOMAIN_USBD 5
|
||||
#define BCM63268_POWER_DOMAIN_ROBOSW 6
|
||||
#define BCM63268_POWER_DOMAIN_PCM 7
|
||||
#define BCM63268_POWER_DOMAIN_PERIPH 8
|
||||
#define BCM63268_POWER_DOMAIN_VDSL_PHY 9
|
||||
#define BCM63268_POWER_DOMAIN_VDSL_MIPS 10
|
||||
#define BCM63268_POWER_DOMAIN_FAP 11
|
||||
#define BCM63268_POWER_DOMAIN_PCIE 12
|
||||
#define BCM63268_POWER_DOMAIN_WLAN_PADS 13
|
||||
|
||||
#endif /* __DT_BINDINGS_BMIPS_BCM63268_PM_H */
|
||||
17
include/dt-bindings/soc/bcm6328-pm.h
Normal file
17
include/dt-bindings/soc/bcm6328-pm.h
Normal file
@ -0,0 +1,17 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef __DT_BINDINGS_BMIPS_BCM6328_PM_H
|
||||
#define __DT_BINDINGS_BMIPS_BCM6328_PM_H
|
||||
|
||||
#define BCM6328_POWER_DOMAIN_ADSL2_MIPS 0
|
||||
#define BCM6328_POWER_DOMAIN_ADSL2_PHY 1
|
||||
#define BCM6328_POWER_DOMAIN_ADSL2_AFE 2
|
||||
#define BCM6328_POWER_DOMAIN_SAR 3
|
||||
#define BCM6328_POWER_DOMAIN_PCM 4
|
||||
#define BCM6328_POWER_DOMAIN_USBD 5
|
||||
#define BCM6328_POWER_DOMAIN_USBH 6
|
||||
#define BCM6328_POWER_DOMAIN_PCIE 7
|
||||
#define BCM6328_POWER_DOMAIN_ROBOSW 8
|
||||
#define BCM6328_POWER_DOMAIN_EPHY 9
|
||||
|
||||
#endif /* __DT_BINDINGS_BMIPS_BCM6328_PM_H */
|
||||
21
include/dt-bindings/soc/bcm6362-pm.h
Normal file
21
include/dt-bindings/soc/bcm6362-pm.h
Normal file
@ -0,0 +1,21 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef __DT_BINDINGS_BMIPS_BCM6362_PM_H
|
||||
#define __DT_BINDINGS_BMIPS_BCM6362_PM_H
|
||||
|
||||
#define BCM6362_POWER_DOMAIN_SAR 0
|
||||
#define BCM6362_POWER_DOMAIN_IPSEC 1
|
||||
#define BCM6362_POWER_DOMAIN_MIPS 2
|
||||
#define BCM6362_POWER_DOMAIN_DECT 3
|
||||
#define BCM6362_POWER_DOMAIN_USBH 4
|
||||
#define BCM6362_POWER_DOMAIN_USBD 5
|
||||
#define BCM6362_POWER_DOMAIN_ROBOSW 6
|
||||
#define BCM6362_POWER_DOMAIN_PCM 7
|
||||
#define BCM6362_POWER_DOMAIN_PERIPH 8
|
||||
#define BCM6362_POWER_DOMAIN_ADSL_PHY 9
|
||||
#define BCM6362_POWER_DOMAIN_GMII_PADS 10
|
||||
#define BCM6362_POWER_DOMAIN_FAP 11
|
||||
#define BCM6362_POWER_DOMAIN_PCIE 12
|
||||
#define BCM6362_POWER_DOMAIN_WLAN_PADS 13
|
||||
|
||||
#endif /* __DT_BINDINGS_BMIPS_BCM6362_PM_H */
|
||||
Loading…
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Reference in New Issue
Block a user