pinctrl: rockchip: Add iomux-route switching support
On the some rockchip SOCS, some things like rk3399 specific uart2 can use multiple pins. Somewhere between the pin io-cells and the uart it seems to have some sort of switch to decide to which pin to actually route the data. +-------+ +--------+ /- GPIO4_B0 (pinmux 2) | uart2 | -- | switch | --- GPIO4_C0 (pinmux 2) +-------+ +--------+ \- GPIO4_C3 (pinmux 2) (switch selects one of the 3 pins base on the GRF_SOC_CON7[BIT0, BIT1]) The routing switch is determined by one pin of a specific group to be set to its special pinmux function. If the pinmux setting is wrong for that pin the ip block won't work correctly anyway. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -146,6 +146,7 @@ struct rockchip_drv {
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* @irq_lock: bus lock for irq chip
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* @new_irqs: newly configured irqs which must be muxed as GPIOs in
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* irq_bus_sync_unlock()
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* @route_mask: bits describing the routing pins of per bank
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*/
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struct rockchip_pin_bank {
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void __iomem *reg_base;
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@ -170,6 +171,7 @@ struct rockchip_pin_bank {
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u32 toggle_edge_mode;
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struct mutex irq_lock;
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u32 new_irqs;
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u32 route_mask;
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};
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#define PIN_BANK(id, pins, label) \
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@ -292,6 +294,22 @@ struct rockchip_pin_bank {
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.pull_type[3] = pull3, \
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}
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @bank_num: bank number.
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* @pin: index at register or used to calc index.
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* @func: the min pin.
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* @route_offset: the max pin.
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* @route_val: the register offset.
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*/
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struct rockchip_mux_route_data {
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u8 bank_num;
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u8 pin;
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u8 func;
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u32 route_offset;
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u32 route_val;
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};
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/**
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*/
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struct rockchip_pin_ctrl {
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@ -304,6 +322,8 @@ struct rockchip_pin_ctrl {
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int pmu_mux_offset;
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int grf_drv_offset;
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int pmu_drv_offset;
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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@ -585,6 +605,30 @@ static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
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*bit = data->bit;
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}
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static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
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int mux, u32 *reg, u32 *value)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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struct rockchip_pin_ctrl *ctrl = info->ctrl;
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struct rockchip_mux_route_data *data;
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int i;
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for (i = 0; i < ctrl->niomux_routes; i++) {
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data = &ctrl->iomux_routes[i];
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if ((data->bank_num == bank->bank_num) &&
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(data->pin == pin) && (data->func == mux))
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break;
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}
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if (i >= ctrl->niomux_routes)
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return false;
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*reg = data->route_offset;
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*value = data->route_val;
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return true;
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}
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static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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@ -683,7 +727,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data, rmask;
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u32 data, rmask, route_reg, route_val;
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ret = rockchip_verify_mux(bank, pin, mux);
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if (ret < 0)
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@ -719,6 +763,15 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
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ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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&route_val)) {
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ret = regmap_write(regmap, route_reg, route_val);
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if (ret)
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return ret;
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}
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}
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data = (mask << (bit + 16));
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rmask = data | (data >> 16);
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data |= (mux & mask) << bit;
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@ -2585,6 +2638,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
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bank_pins += 8;
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}
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/* calculate the per-bank route_mask */
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for (j = 0; j < ctrl->niomux_routes; j++) {
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int pin = 0;
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if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
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pin = ctrl->iomux_routes[j].pin;
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bank->route_mask |= BIT(pin);
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}
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}
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}
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return ctrl;
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