pch_can: Rename function/macro name
For easy to read/understand, Rename function/macro name. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Tomoya
David S. Miller
parent
7f2bc50efe
commit
bd58cbc322
@ -32,8 +32,6 @@
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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#define PCH_ENABLE 1 /* The enable flag */
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#define PCH_DISABLE 0 /* The disable flag */
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#define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
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#define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
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#define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
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@ -78,11 +76,12 @@
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#define PCH_BUS_OFF BIT(7)
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/* bit position of certain controller bits. */
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#define PCH_BIT_BRP 0
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#define PCH_BIT_SJW 6
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#define PCH_BIT_TSEG1 8
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#define PCH_BIT_TSEG2 12
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#define PCH_BIT_BRPE_BRPE 6
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#define PCH_BIT_BRP_SHIFT 0
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#define PCH_BIT_SJW_SHIFT 6
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#define PCH_BIT_TSEG1_SHIFT 8
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#define PCH_BIT_TSEG2_SHIFT 12
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#define PCH_BIT_BRPE_BRPE_SHIFT 6
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#define PCH_MSK_BITT_BRP 0x3f
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#define PCH_MSK_BRPE_BRPE 0x3c0
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#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
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@ -170,19 +169,16 @@ struct pch_can_regs {
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struct pch_can_priv {
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struct can_priv can;
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unsigned int can_num;
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struct pci_dev *dev;
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int tx_enable[PCH_TX_OBJ_END];
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int rx_enable[PCH_TX_OBJ_END];
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int rx_link[PCH_TX_OBJ_END];
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unsigned int int_enables;
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unsigned int int_stat;
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u32 tx_enable[PCH_TX_OBJ_END];
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u32 rx_enable[PCH_TX_OBJ_END];
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u32 rx_link[PCH_TX_OBJ_END];
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u32 int_enables;
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struct net_device *ndev;
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unsigned int msg_obj[PCH_TX_OBJ_END];
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struct pch_can_regs __iomem *regs;
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struct napi_struct napi;
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unsigned int tx_obj; /* Point next Tx Obj index */
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unsigned int use_msi;
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int tx_obj; /* Point next Tx Obj index */
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int use_msi;
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};
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static struct can_bittiming_const pch_can_bittiming_const = {
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@ -245,14 +241,27 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
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iowrite32(reg_val, &priv->regs->opt);
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}
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static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
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{
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int counter = PCH_COUNTER_LIMIT;
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u32 ifx_creq;
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iowrite32(num, creq_addr);
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while (counter) {
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ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
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if (!ifx_creq)
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break;
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counter--;
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udelay(1);
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}
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if (!counter)
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pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
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}
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static void pch_can_set_int_enables(struct pch_can_priv *priv,
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enum pch_can_mode interrupt_no)
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{
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switch (interrupt_no) {
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case PCH_CAN_ENABLE:
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pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
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break;
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case PCH_CAN_DISABLE:
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pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
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break;
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@ -271,25 +280,8 @@ static void pch_can_set_int_enables(struct pch_can_priv *priv,
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}
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}
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static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
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{
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u32 counter = PCH_COUNTER_LIMIT;
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u32 ifx_creq;
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iowrite32(num, creq_addr);
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while (counter) {
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ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
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if (!ifx_creq)
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break;
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counter--;
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udelay(1);
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}
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if (!counter)
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pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
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}
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static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
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u32 set, enum pch_ifreg dir)
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int set, enum pch_ifreg dir)
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{
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u32 ie;
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@ -300,27 +292,27 @@ static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
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/* Reading the receive buffer data from RAM to Interface1 registers */
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
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pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
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/* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
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&priv->regs->ifregs[dir].cmask);
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if (set == PCH_ENABLE) {
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if (set) {
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/* Setting the MsgVal and RxIE bits */
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pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
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pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
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} else if (set == PCH_DISABLE) {
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} else {
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/* Resetting the MsgVal and RxIE bits */
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pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
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pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
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}
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pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
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pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
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}
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static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
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static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
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{
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int i;
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@ -329,7 +321,7 @@ static void pch_can_set_rx_all(struct pch_can_priv *priv, u32 set)
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pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
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}
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static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
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static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
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{
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int i;
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@ -338,16 +330,16 @@ static void pch_can_set_tx_all(struct pch_can_priv *priv, u32 set)
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pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
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}
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static int pch_can_int_pending(struct pch_can_priv *priv)
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static u32 pch_can_int_pending(struct pch_can_priv *priv)
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{
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return ioread32(&priv->regs->intr) & 0xffff;
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}
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static void pch_can_clear_buffers(struct pch_can_priv *priv)
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static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
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{
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int i;
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int i; /* Msg Obj ID (1~32) */
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for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
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for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
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iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
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iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
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iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
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@ -361,24 +353,7 @@ static void pch_can_clear_buffers(struct pch_can_priv *priv)
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
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PCH_CMASK_ARB | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
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}
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for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
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iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[1].cmask);
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iowrite32(0xffff, &priv->regs->ifregs[1].mask1);
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iowrite32(0xffff, &priv->regs->ifregs[1].mask2);
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iowrite32(0x0, &priv->regs->ifregs[1].id1);
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iowrite32(0x0, &priv->regs->ifregs[1].id2);
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iowrite32(0x0, &priv->regs->ifregs[1].mcont);
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iowrite32(0x0, &priv->regs->ifregs[1].data[0]);
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iowrite32(0x0, &priv->regs->ifregs[1].data[1]);
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iowrite32(0x0, &priv->regs->ifregs[1].data[2]);
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iowrite32(0x0, &priv->regs->ifregs[1].data[3]);
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
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PCH_CMASK_ARB | PCH_CMASK_CTRL,
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&priv->regs->ifregs[1].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
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}
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}
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@ -389,7 +364,7 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
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for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
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iowrite32(PCH_CMASK_RX_TX_GET,
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&priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
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iowrite32(0x0, &priv->regs->ifregs[0].id1);
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iowrite32(0x0, &priv->regs->ifregs[0].id2);
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@ -403,6 +378,9 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
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/* In case FIFO mode, Last EoB of Rx Obj must be 1 */
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if (i == PCH_RX_OBJ_END)
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pch_can_bit_set(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_EOB);
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else
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_EOB);
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iowrite32(0, &priv->regs->ifregs[0].mask1);
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@ -414,13 +392,13 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
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PCH_CMASK_ARB | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, i);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
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}
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for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
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iowrite32(PCH_CMASK_RX_TX_GET,
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&priv->regs->ifregs[1].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
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pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
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/* Resetting DIR bit for reception */
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iowrite32(0x0, &priv->regs->ifregs[1].id1);
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@ -441,7 +419,7 @@ static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
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PCH_CMASK_ARB | PCH_CMASK_CTRL,
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&priv->regs->ifregs[1].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[1].creq, i);
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pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
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}
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}
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@ -451,7 +429,7 @@ static void pch_can_init(struct pch_can_priv *priv)
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pch_can_set_run_mode(priv, PCH_CAN_STOP);
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/* Clearing all the message object buffers. */
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pch_can_clear_buffers(priv);
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pch_can_clear_if_buffers(priv);
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/* Configuring the respective message object as either rx/tx object. */
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pch_can_config_rx_tx_buffers(priv);
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@ -496,7 +474,7 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, mask);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
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} else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
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/* Setting CMASK for clearing interrupts for
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frame transmission. */
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@ -512,7 +490,7 @@ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
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pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
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PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
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PCH_IF_MCONT_TXRQXT);
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pch_can_check_if_busy(&priv->regs->ifregs[1].creq, mask);
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pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
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}
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}
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@ -637,7 +615,7 @@ static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
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/* Clearing NewDat & IntPnd */
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pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
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PCH_IF_MCONT_INTPND);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
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} else if (obj_id > PCH_FIFO_THRESH) {
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pch_can_int_clr(priv, obj_id);
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} else if (obj_id == PCH_FIFO_THRESH) {
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@ -659,7 +637,7 @@ static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
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PCH_IF_MCONT_MSGLOST);
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iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
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&priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_id);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
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skb = alloc_can_err_skb(ndev, &cf);
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if (!skb)
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@ -689,7 +667,7 @@ static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
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do {
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/* Reading the messsage object from the Message RAM */
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iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[0].creq, obj_num);
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pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
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/* Reading the MCONT register. */
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reg = ioread32(&priv->regs->ifregs[0].mcont);
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@ -758,7 +736,7 @@ static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
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can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
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iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
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&priv->regs->ifregs[1].cmask);
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pch_can_check_if_busy(&priv->regs->ifregs[1].creq, int_stat);
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pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
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dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
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PCH_IF_MCONT_DLC);
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stats->tx_bytes += dlc;
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@ -767,7 +745,7 @@ static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
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netif_wake_queue(ndev);
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}
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static int pch_can_rx_poll(struct napi_struct *napi, int quota)
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static int pch_can_poll(struct napi_struct *napi, int quota)
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{
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struct net_device *ndev = napi->dev;
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struct pch_can_priv *priv = netdev_priv(ndev);
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@ -832,10 +810,10 @@ static int pch_set_bittiming(struct net_device *ndev)
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brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
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canbit = brp & PCH_MSK_BITT_BRP;
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canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
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canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
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canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
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bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
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canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
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canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
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canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
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bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
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iowrite32(canbit, &priv->regs->bitt);
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iowrite32(bepe, &priv->regs->brpe);
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pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
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@ -947,7 +925,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct pch_can_priv *priv = netdev_priv(ndev);
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struct can_frame *cf = (struct can_frame *)skb->data;
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int tx_buffer_avail = 0;
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int tx_obj_no;
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int i;
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if (can_dropped_invalid_skb(ndev, skb))
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@ -957,16 +935,16 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
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if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
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netif_stop_queue(ndev);
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tx_buffer_avail = priv->tx_obj;
|
||||
tx_obj_no = priv->tx_obj;
|
||||
priv->tx_obj = PCH_TX_OBJ_START;
|
||||
} else {
|
||||
tx_buffer_avail = priv->tx_obj;
|
||||
tx_obj_no = priv->tx_obj;
|
||||
priv->tx_obj++;
|
||||
}
|
||||
|
||||
/* Reading the Msg Obj from the Msg RAM to the Interface register. */
|
||||
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
|
||||
pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
|
||||
pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
|
||||
|
||||
/* Setting the CMASK register. */
|
||||
pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
|
||||
@ -995,7 +973,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
|
||||
&priv->regs->ifregs[1].data[i / 2]);
|
||||
}
|
||||
|
||||
can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_END - 1);
|
||||
can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
|
||||
|
||||
/* Updating the size of the data. */
|
||||
pch_can_bit_clear(&priv->regs->ifregs[1].mcont, 0x0f);
|
||||
@ -1010,7 +988,7 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
|
||||
pch_can_bit_set(&priv->regs->ifregs[1].mcont,
|
||||
PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
|
||||
|
||||
pch_can_check_if_busy(&priv->regs->ifregs[1].creq, tx_buffer_avail);
|
||||
pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
|
||||
|
||||
return NETDEV_TX_OK;
|
||||
}
|
||||
@ -1064,7 +1042,7 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
|
||||
ie = PCH_IF_MCONT_TXIE;
|
||||
|
||||
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
|
||||
pch_can_check_if_busy(&priv->regs->ifregs[dir].creq, buff_num);
|
||||
pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
|
||||
|
||||
if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
|
||||
((ioread32(&priv->regs->ifregs[dir].mcont)) & ie)) {
|
||||
@ -1076,37 +1054,37 @@ static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
|
||||
}
|
||||
|
||||
static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
|
||||
u32 buffer_num, u32 set)
|
||||
u32 buffer_num, int set)
|
||||
{
|
||||
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
|
||||
pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
|
||||
pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
|
||||
iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
|
||||
&priv->regs->ifregs[0].cmask);
|
||||
if (set == PCH_ENABLE)
|
||||
if (set)
|
||||
pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
|
||||
PCH_IF_MCONT_EOB);
|
||||
else
|
||||
pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
|
||||
|
||||
pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
|
||||
pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
|
||||
}
|
||||
|
||||
static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
|
||||
u32 buffer_num, u32 *link)
|
||||
{
|
||||
iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
|
||||
pch_can_check_if_busy(&priv->regs->ifregs[0].creq, buffer_num);
|
||||
pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
|
||||
|
||||
if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
|
||||
*link = PCH_DISABLE;
|
||||
*link = 0;
|
||||
else
|
||||
*link = PCH_ENABLE;
|
||||
*link = 1;
|
||||
}
|
||||
|
||||
static int pch_can_get_buffer_status(struct pch_can_priv *priv)
|
||||
{
|
||||
return (ioread32(&priv->regs->treq1) & 0xffff) |
|
||||
((ioread32(&priv->regs->treq2) & 0xffff) << 16);
|
||||
(ioread32(&priv->regs->treq2) << 16);
|
||||
}
|
||||
|
||||
static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
@ -1114,7 +1092,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
|
||||
int i; /* Counter variable. */
|
||||
int retval; /* Return value. */
|
||||
u32 buf_stat; /* Variable for reading the transmit buffer status. */
|
||||
u32 counter = 0xFFFFFF;
|
||||
int counter = PCH_COUNTER_LIMIT;
|
||||
|
||||
struct net_device *dev = pci_get_drvdata(pdev);
|
||||
struct pch_can_priv *priv = netdev_priv(dev);
|
||||
@ -1291,7 +1269,7 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
|
||||
ndev->netdev_ops = &pch_can_netdev_ops;
|
||||
priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
|
||||
|
||||
netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_END);
|
||||
netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
|
||||
|
||||
rc = register_candev(ndev);
|
||||
if (rc) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user