drm/amd/pm: correct the pcie width for smu 13.0.0
correct the pcie width value in pp_dpm_pcie for smu 13.0.0 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -1140,7 +1140,6 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
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struct smu_13_0_dpm_table *single_dpm_table;
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struct smu_13_0_pcie_table *pcie_table;
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const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
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uint32_t gen_speed, lane_width;
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int i, curr_freq, size = 0;
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int32_t min_value, max_value;
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@ -1256,7 +1255,7 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
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(pcie_table->pcie_lane[i] == 6) ? "x16" : "",
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pcie_table->clk_freq[i],
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(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
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(lane_width == DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?
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(lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
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"*" : "");
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break;
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