Merge branch 'v4.7-shared/clkids' into v4.7-clk/next
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bdb4da8619
@ -136,7 +136,7 @@
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#define DCLK_VOP1_DIV 183
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#define DCLK_VOP1_DIV 183
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#define DCLK_M0_PERILP 184
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#define DCLK_M0_PERILP 184
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#define FCLK_CM0S 190
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#define FCLK_CM0S 190
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/* aclk gates */
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/* aclk gates */
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#define ACLK_PERIHP 192
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#define ACLK_PERIHP 192
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@ -207,11 +207,11 @@
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#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
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#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
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#define ACLK_ADB400M_PD_CORE_L 258
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#define ACLK_ADB400M_PD_CORE_L 258
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#define ACLK_ADB400M_PD_CORE_B 259
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#define ACLK_ADB400M_PD_CORE_B 259
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#define ACLK_PERF_CORE_L 260
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#define ACLK_PERF_CORE_L 260
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#define ACLK_PERF_CORE_B 261
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#define ACLK_PERF_CORE_B 261
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#define ACLK_GIC_PRE 262
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#define ACLK_GIC_PRE 262
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#define ACLK_VOP0_PRE 263
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#define ACLK_VOP0_PRE 263
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#define ACLK_VOP1_PRE 264
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#define ACLK_VOP1_PRE 264
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/* pclk gates */
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/* pclk gates */
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#define PCLK_PERIHP 320
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#define PCLK_PERIHP 320
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@ -279,12 +279,12 @@
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#define PCLK_EFUSE1024S 382
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#define PCLK_EFUSE1024S 382
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#define PCLK_PMU_INTR_ARB 383
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#define PCLK_PMU_INTR_ARB 383
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#define PCLK_MAILBOX0 384
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#define PCLK_MAILBOX0 384
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#define PCLK_USBPHY_MUX_G 385
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#define PCLK_USBPHY_MUX_G 385
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#define PCLK_UPHY0_TCPHY_G 386
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#define PCLK_UPHY0_TCPHY_G 386
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#define PCLK_UPHY0_TCPD_G 387
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#define PCLK_UPHY0_TCPD_G 387
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#define PCLK_UPHY1_TCPHY_G 388
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#define PCLK_UPHY1_TCPHY_G 388
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#define PCLK_UPHY1_TCPD_G 389
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#define PCLK_UPHY1_TCPD_G 389
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#define PCLK_ALIVE 390
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#define PCLK_ALIVE 390
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/* hclk gates */
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/* hclk gates */
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#define HCLK_PERIHP 448
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#define HCLK_PERIHP 448
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