iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: qcom: videocc-sm8350: Set delay for Venus CLK resets

Browse Source 
Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8350, see [1].

[1] dfe241edf2

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-16-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio 2024-02-06 19:43:49 +01:00 committed by Bjorn Andersson
parent 4e32a9c2a3
commit bdc8fc1ecc
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/qcom/videocc-sm8350.c
View File

@ -488,10 +488,10 @@ static struct clk_regmap *video_cc_sm8350_clocks[] = {
static const struct qcom_reset_map video_cc_sm8350_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0xc34, .bit = 2, .udelay = 400 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0xcd4, .bit = 2, .udelay = 400 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};