drm/i915/gt: Skip TLB invalidations once wedged
Skip all further TLB invalidations once the device is wedged and had been reset, as, on such cases, it can no longer process instructions on the GPU and the user no longer has access to the TLB's in each engine. So, an attempt to do a TLB cache invalidation will produce a timeout. That helps to reduce the performance regression introduced by TLB invalidate logic. Cc: stable@vger.kernel.org Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Signed-off-by: Chris Wilson <chris.p.wilson@intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5aa86564b9ec5fe7fe605c1dd7de76855401ed73.1658924372.git.mchehab@kernel.org
This commit is contained in:
parent
dfc83de118
commit
be0366f168
@ -934,6 +934,9 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
|
||||
if (I915_SELFTEST_ONLY(gt->awake == -ENODEV))
|
||||
return;
|
||||
|
||||
if (intel_gt_is_wedged(gt))
|
||||
return;
|
||||
|
||||
if (GRAPHICS_VER(i915) == 12) {
|
||||
regs = gen12_regs;
|
||||
num = ARRAY_SIZE(gen12_regs);
|
||||
|
Loading…
x
Reference in New Issue
Block a user