drm/amdgpu: add convert for new gfx type
Add convert for CP RS64 related gfx ip type. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2211,6 +2211,39 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
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case AMDGPU_UCODE_ID_IMU_D:
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*type = GFX_FW_TYPE_IMU_D;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_PFP:
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*type = GFX_FW_TYPE_RS64_PFP;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_ME:
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*type = GFX_FW_TYPE_RS64_ME;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC:
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*type = GFX_FW_TYPE_RS64_MEC;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
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*type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
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*type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
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*type = GFX_FW_TYPE_RS64_ME_P0_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
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*type = GFX_FW_TYPE_RS64_ME_P1_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
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break;
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case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
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*type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
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break;
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case AMDGPU_UCODE_ID_MAXIMUM:
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default:
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return -EINVAL;
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@ -389,6 +389,17 @@ enum AMDGPU_UCODE_ID {
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AMDGPU_UCODE_ID_CP_CE,
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AMDGPU_UCODE_ID_CP_PFP,
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AMDGPU_UCODE_ID_CP_ME,
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AMDGPU_UCODE_ID_CP_RS64_PFP,
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AMDGPU_UCODE_ID_CP_RS64_ME,
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AMDGPU_UCODE_ID_CP_RS64_MEC,
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AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
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AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
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AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
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AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
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AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
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AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
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AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
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AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
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AMDGPU_UCODE_ID_CP_MEC1,
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AMDGPU_UCODE_ID_CP_MEC1_JT,
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AMDGPU_UCODE_ID_CP_MEC2,
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