ARM: i.MX: clock fixes
- fix wrong timer clock on i.MX25 leading to strange timing inconsistencies - fix SPI clocks for i.MX27 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABCAAGBQJRENdUAAoJEPFlmONMx+ezRhsP/0dUD6AzT8KOCFJfvIn1K0RB 5BpMOZ1jMFOAnOvWo2a7kEOJlSPtvhDX8qmvxrbSeSyqtFVg3Wa5SJzAkQw9XG1W wr7igB4/MKlPfxo+s/9ULt7omnjVOo+d3qngsZsisc7tv7Qk4VytDrpiKvVuDVCp gSHp5b+2ak50+HGb/hgrFlMPbhCoJtmtRcjsWpd10lFeDfcioIKHLmMmjhe9BVP0 L+x8Ize2koLK+JzH2mKe0agCT93BkziJozygb8KHKfPfg6SDT6q+a/NTaccELbWa /3EWd3EZvE3BMF0f8VKvDMvqpbR+tjxJ0TQKvlN6BjLkeGF4rLHFRfYtnJ7NWqWu QQ/iVpvM3BU75P+1zGw4it3R6XMyaN9OiuypkkcWPimqHh2UnQLb6nO/r+HpxbkU LL/PD1RyFrCwLeZ1kcqg1O9B3JPNQ697f5zkrzUNf44ltJzfcsBHFX9bEYEwUfNt AGzfGokQi829eDmJiAeEjpUZOBJpK4wEqzXOiCCxE+O/LeoJyt1IbiBpmDauSGcx T7v4jCAbABMLJ/Rfo4qbclrEhGW/dG83JiqtB1bOuxTlDvCgwoP2+icKU069O5sD 6wg1o7Bddk5XNa7cUqPbi1XNI1gEtp9QSGI7HpUGJstUKzNbJeB+XEyXQvQsqb+P vyKmMVKc+ceriX6BOuar =CRoU -----END PGP SIGNATURE----- Merge tag 'arm-imx-clk-fixes' of git://git.pengutronix.de/git/imx/linux-2.6 into next/fixes-non-critical ARM: i.MX: clock fixes - fix wrong timer clock on i.MX25 leading to strange timing inconsistencies - fix SPI clocks for i.MX27 * tag 'arm-imx-clk-fixes' of git://git.pengutronix.de/git/imx/linux-2.6: ARM: i.MX25: clk: parent per5_clk to AHB clock ARM: imx27: clk-imx27: SPI: Rename IPG clock and add PER clock Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -224,6 +224,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
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clk_prepare_enable(clk[emi_ahb]);
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/* Clock source for gpt must be derived from AHB */
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clk_set_parent(clk[per5_sel], clk[ahb]);
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clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
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@ -228,9 +228,12 @@ int __init mx27_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
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clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
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clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
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clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
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clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
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clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
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clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
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clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
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clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
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clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
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clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
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clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
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clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
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clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
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clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
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