drm/radeon: prep for r6xx/r7xx support
- add r6xx/r7xx regs and macros - add r6xx/r7xx chip families - fix register access for regs with offsets >= 0x10000 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
995e37cafb
commit
befb73c232
@ -89,6 +89,20 @@ u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
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return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
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}
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u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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if (addr < 0x10000)
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ret = DRM_READ32(dev_priv->mmio, addr);
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else {
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DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
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ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
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}
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return ret;
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}
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static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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u32 ret;
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@ -134,6 +134,16 @@ enum radeon_family {
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CHIP_RV560,
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CHIP_RV570,
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CHIP_R580,
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CHIP_R600,
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CHIP_RV610,
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CHIP_RV630,
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CHIP_RV620,
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CHIP_RV635,
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CHIP_RV670,
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CHIP_RS780,
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CHIP_RV770,
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CHIP_RV730,
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CHIP_RV710,
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CHIP_LAST,
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};
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@ -317,6 +327,26 @@ typedef struct drm_radeon_private {
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int num_gb_pipes;
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int track_flush;
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drm_local_map_t *mmio;
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/* r6xx/r7xx pipe/shader config */
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int r600_max_pipes;
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int r600_max_tile_pipes;
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int r600_max_simds;
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int r600_max_backends;
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int r600_max_gprs;
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int r600_max_threads;
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int r600_max_stack_entries;
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int r600_max_hw_contexts;
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int r600_max_gs_threads;
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int r600_sx_max_export_size;
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int r600_sx_max_export_pos_size;
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int r600_sx_max_export_smx_size;
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int r600_sq_num_cf_insts;
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int r700_sx_num_of_sets;
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int r700_sc_prim_fifo_size;
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int r700_sc_hiz_tile_fifo_size;
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int r700_sc_earlyz_tile_fifo_fize;
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} drm_radeon_private_t;
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typedef struct drm_radeon_buf_priv {
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@ -366,6 +396,7 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi
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extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
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extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
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extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
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extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
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extern void radeon_freelist_reset(struct drm_device * dev);
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extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
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@ -436,6 +467,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
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/* Register definitions, register access macros and drmAddMap constants
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* for Radeon kernel driver.
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*/
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#define RADEON_MM_INDEX 0x0000
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#define RADEON_MM_DATA 0x0004
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#define RADEON_AGP_COMMAND 0x0f60
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#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
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@ -645,6 +678,19 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
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#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
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#define R600_SCRATCH_REG0 0x8500
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#define R600_SCRATCH_REG1 0x8504
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#define R600_SCRATCH_REG2 0x8508
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#define R600_SCRATCH_REG3 0x850c
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#define R600_SCRATCH_REG4 0x8510
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#define R600_SCRATCH_REG5 0x8514
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#define R600_SCRATCH_REG6 0x8518
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#define R600_SCRATCH_REG7 0x851c
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#define R600_SCRATCH_UMSK 0x8540
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#define R600_SCRATCH_ADDR 0x8544
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#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
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#define RADEON_GEN_INT_CNTL 0x0040
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# define RADEON_CRTC_VBLANK_MASK (1 << 0)
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# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
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@ -924,6 +970,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
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#define RADEON_CP_RB_CNTL 0x0704
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# define RADEON_BUF_SWAP_32BIT (2 << 16)
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# define RADEON_RB_NO_UPDATE (1 << 27)
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# define RADEON_RB_RPTR_WR_ENA (1 << 31)
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#define RADEON_CP_RB_RPTR_ADDR 0x070c
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#define RADEON_CP_RB_RPTR 0x0710
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#define RADEON_CP_RB_WPTR 0x0714
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@ -985,6 +1032,14 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
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# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
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# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
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# define R600_IT_INDIRECT_BUFFER 0x00003200
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# define R600_IT_ME_INITIALIZE 0x00004400
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# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
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# define R600_IT_EVENT_WRITE 0x00004600
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# define R600_IT_SET_CONFIG_REG 0x00006800
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# define R600_SET_CONFIG_REG_OFFSET 0x00008000
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# define R600_SET_CONFIG_REG_END 0x0000ac00
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#define RADEON_CP_PACKET_MASK 0xC0000000
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#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
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#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
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@ -1183,6 +1238,422 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
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#define R500_D1_VBLANK_INTERRUPT (1 << 4)
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#define R500_D2_VBLANK_INTERRUPT (1 << 5)
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/* R6xx/R7xx registers */
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#define R600_MC_VM_FB_LOCATION 0x2180
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#define R600_MC_VM_AGP_TOP 0x2184
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#define R600_MC_VM_AGP_BOT 0x2188
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#define R600_MC_VM_AGP_BASE 0x218c
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#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
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#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
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#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
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#define R700_MC_VM_FB_LOCATION 0x2024
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#define R700_MC_VM_AGP_TOP 0x2028
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#define R700_MC_VM_AGP_BOT 0x202c
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#define R700_MC_VM_AGP_BASE 0x2030
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#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
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#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
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#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
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#define R600_MCD_RD_A_CNTL 0x219c
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#define R600_MCD_RD_B_CNTL 0x21a0
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#define R600_MCD_WR_A_CNTL 0x21a4
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#define R600_MCD_WR_B_CNTL 0x21a8
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#define R600_MCD_RD_SYS_CNTL 0x2200
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#define R600_MCD_WR_SYS_CNTL 0x2214
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#define R600_MCD_RD_GFX_CNTL 0x21fc
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#define R600_MCD_RD_HDP_CNTL 0x2204
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#define R600_MCD_RD_PDMA_CNTL 0x2208
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#define R600_MCD_RD_SEM_CNTL 0x220c
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#define R600_MCD_WR_GFX_CNTL 0x2210
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#define R600_MCD_WR_HDP_CNTL 0x2218
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#define R600_MCD_WR_PDMA_CNTL 0x221c
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#define R600_MCD_WR_SEM_CNTL 0x2220
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# define R600_MCD_L1_TLB (1 << 0)
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# define R600_MCD_L1_FRAG_PROC (1 << 1)
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# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
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# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
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# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
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# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
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# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
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# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
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# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
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# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
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# define R600_MCD_SEMAPHORE_MODE (1 << 10)
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# define R600_MCD_WAIT_L2_QUERY (1 << 11)
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# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
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# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
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#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
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#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
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#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
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#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
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#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
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#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
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#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
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# define R700_ENABLE_L1_TLB (1 << 0)
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# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
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# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
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# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
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# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
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# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
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#define R700_MC_ARB_RAMCFG 0x2760
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# define R700_NOOFBANK_SHIFT 0
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# define R700_NOOFBANK_MASK 0x3
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# define R700_NOOFRANK_SHIFT 2
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# define R700_NOOFRANK_MASK 0x1
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# define R700_NOOFROWS_SHIFT 3
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# define R700_NOOFROWS_MASK 0x7
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# define R700_NOOFCOLS_SHIFT 6
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# define R700_NOOFCOLS_MASK 0x3
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# define R700_CHANSIZE_SHIFT 8
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# define R700_CHANSIZE_MASK 0x1
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# define R700_BURSTLENGTH_SHIFT 9
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# define R700_BURSTLENGTH_MASK 0x1
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#define R600_RAMCFG 0x2408
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# define R600_NOOFBANK_SHIFT 0
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# define R600_NOOFBANK_MASK 0x1
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# define R600_NOOFRANK_SHIFT 1
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# define R600_NOOFRANK_MASK 0x1
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# define R600_NOOFROWS_SHIFT 2
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# define R600_NOOFROWS_MASK 0x7
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# define R600_NOOFCOLS_SHIFT 5
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# define R600_NOOFCOLS_MASK 0x3
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# define R600_CHANSIZE_SHIFT 7
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# define R600_CHANSIZE_MASK 0x1
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# define R600_BURSTLENGTH_SHIFT 8
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# define R600_BURSTLENGTH_MASK 0x1
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#define R600_VM_L2_CNTL 0x1400
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# define R600_VM_L2_CACHE_EN (1 << 0)
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# define R600_VM_L2_FRAG_PROC (1 << 1)
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# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
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# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
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# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
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#define R600_VM_L2_CNTL2 0x1404
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# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
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# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
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#define R600_VM_L2_CNTL3 0x1408
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# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
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# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
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# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
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# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
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# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
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#define R600_VM_L2_STATUS 0x140c
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#define R600_VM_CONTEXT0_CNTL 0x1410
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# define R600_VM_ENABLE_CONTEXT (1 << 0)
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# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
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#define R600_VM_CONTEXT0_CNTL2 0x1430
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#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
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#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
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#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
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#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
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#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
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#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
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#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
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#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
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#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
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#define R600_HDP_HOST_PATH_CNTL 0x2c00
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#define R600_GRBM_CNTL 0x8000
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# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define R600_GRBM_STATUS 0x8010
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# define R600_CMDFIFO_AVAIL_MASK 0x1f
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# define R700_CMDFIFO_AVAIL_MASK 0xf
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# define R600_GUI_ACTIVE (1 << 31)
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#define R600_GRBM_STATUS2 0x8014
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#define R600_GRBM_SOFT_RESET 0x8020
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# define R600_SOFT_RESET_CP (1 << 0)
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#define R600_WAIT_UNTIL 0x8040
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#define R600_CP_SEM_WAIT_TIMER 0x85bc
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#define R600_CP_ME_CNTL 0x86d8
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# define R600_CP_ME_HALT (1 << 28)
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#define R600_CP_QUEUE_THRESHOLDS 0x8760
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# define R600_ROQ_IB1_START(x) ((x) << 0)
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# define R600_ROQ_IB2_START(x) ((x) << 8)
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#define R600_CP_MEQ_THRESHOLDS 0x8764
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# define R700_STQ_SPLIT(x) ((x) << 0)
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# define R600_MEQ_END(x) ((x) << 16)
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# define R600_ROQ_END(x) ((x) << 24)
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#define R600_CP_PERFMON_CNTL 0x87fc
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#define R600_CP_RB_BASE 0xc100
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#define R600_CP_RB_CNTL 0xc104
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# define R600_RB_BUFSZ(x) ((x) << 0)
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# define R600_RB_BLKSZ(x) ((x) << 8)
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# define R600_RB_NO_UPDATE (1 << 27)
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# define R600_RB_RPTR_WR_ENA (1 << 31)
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#define R600_CP_RB_RPTR_WR 0xc108
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#define R600_CP_RB_RPTR_ADDR 0xc10c
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#define R600_CP_RB_RPTR_ADDR_HI 0xc110
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#define R600_CP_RB_WPTR 0xc114
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#define R600_CP_RB_WPTR_ADDR 0xc118
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#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
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#define R600_CP_RB_RPTR 0x8700
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#define R600_CP_RB_WPTR_DELAY 0x8704
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#define R600_CP_PFP_UCODE_ADDR 0xc150
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#define R600_CP_PFP_UCODE_DATA 0xc154
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#define R600_CP_ME_RAM_RADDR 0xc158
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#define R600_CP_ME_RAM_WADDR 0xc15c
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#define R600_CP_ME_RAM_DATA 0xc160
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#define R600_CP_DEBUG 0xc1fc
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#define R600_PA_CL_ENHANCE 0x8a14
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# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
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# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
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#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
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#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
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#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
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# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
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# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
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#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
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#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
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#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
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#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
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# define R600_S0_X(x) ((x) << 0)
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# define R600_S0_Y(x) ((x) << 4)
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# define R600_S1_X(x) ((x) << 8)
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# define R600_S1_Y(x) ((x) << 12)
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# define R600_S2_X(x) ((x) << 16)
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# define R600_S2_Y(x) ((x) << 20)
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# define R600_S3_X(x) ((x) << 24)
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# define R600_S3_Y(x) ((x) << 28)
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# define R600_S4_X(x) ((x) << 0)
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# define R600_S4_Y(x) ((x) << 4)
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# define R600_S5_X(x) ((x) << 8)
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# define R600_S5_Y(x) ((x) << 12)
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# define R600_S6_X(x) ((x) << 16)
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# define R600_S6_Y(x) ((x) << 20)
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# define R600_S7_X(x) ((x) << 24)
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# define R600_S7_Y(x) ((x) << 28)
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#define R600_PA_SC_FIFO_SIZE 0x8bd0
|
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# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
|
||||
# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
|
||||
# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
|
||||
#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
|
||||
# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
|
||||
# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
|
||||
# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
|
||||
#define R600_PA_SC_ENHANCE 0x8bf0
|
||||
# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
|
||||
# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
|
||||
#define R600_PA_SC_CLIPRECT_RULE 0x2820c
|
||||
#define R700_PA_SC_EDGERULE 0x28230
|
||||
#define R600_PA_SC_LINE_STIPPLE 0x28a0c
|
||||
#define R600_PA_SC_MODE_CNTL 0x28a4c
|
||||
#define R600_PA_SC_AA_CONFIG 0x28c04
|
||||
|
||||
#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
|
||||
# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
|
||||
# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
|
||||
# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
|
||||
#define R600_SX_DEBUG_1 0x9054
|
||||
# define R600_SMX_EVENT_RELEASE (1 << 0)
|
||||
# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
|
||||
#define R700_SX_DEBUG_1 0x9058
|
||||
# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
|
||||
#define R600_SX_MISC 0x28350
|
||||
|
||||
#define R600_DB_DEBUG 0x9830
|
||||
# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
|
||||
#define R600_DB_WATERMARKS 0x9838
|
||||
# define R600_DEPTH_FREE(x) ((x) << 0)
|
||||
# define R600_DEPTH_FLUSH(x) ((x) << 5)
|
||||
# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
|
||||
# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
|
||||
#define R700_DB_DEBUG3 0x98b0
|
||||
# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
|
||||
#define RV700_DB_DEBUG4 0x9b8c
|
||||
# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
|
||||
|
||||
#define R600_VGT_CACHE_INVALIDATION 0x88c4
|
||||
# define R600_CACHE_INVALIDATION(x) ((x) << 0)
|
||||
# define R600_VC_ONLY 0
|
||||
# define R600_TC_ONLY 1
|
||||
# define R600_VC_AND_TC 2
|
||||
# define R700_AUTO_INVLD_EN(x) ((x) << 6)
|
||||
# define R700_NO_AUTO 0
|
||||
# define R700_ES_AUTO 1
|
||||
# define R700_GS_AUTO 2
|
||||
# define R700_ES_AND_GS_AUTO 3
|
||||
#define R600_VGT_GS_PER_ES 0x88c8
|
||||
#define R600_VGT_ES_PER_GS 0x88cc
|
||||
#define R600_VGT_GS_PER_VS 0x88e8
|
||||
#define R600_VGT_GS_VERTEX_REUSE 0x88d4
|
||||
#define R600_VGT_NUM_INSTANCES 0x8974
|
||||
#define R600_VGT_STRMOUT_EN 0x28ab0
|
||||
#define R600_VGT_EVENT_INITIATOR 0x28a90
|
||||
# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
|
||||
#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
|
||||
# define R600_VTX_REUSE_DEPTH_MASK 0xff
|
||||
#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
|
||||
# define R600_DEALLOC_DIST_MASK 0x7f
|
||||
|
||||
#define R600_CB_COLOR0_BASE 0x28040
|
||||
#define R600_CB_COLOR1_BASE 0x28044
|
||||
#define R600_CB_COLOR2_BASE 0x28048
|
||||
#define R600_CB_COLOR3_BASE 0x2804c
|
||||
#define R600_CB_COLOR4_BASE 0x28050
|
||||
#define R600_CB_COLOR5_BASE 0x28054
|
||||
#define R600_CB_COLOR6_BASE 0x28058
|
||||
#define R600_CB_COLOR7_BASE 0x2805c
|
||||
#define R600_CB_COLOR7_FRAG 0x280fc
|
||||
|
||||
#define R600_TC_CNTL 0x9608
|
||||
# define R600_TC_L2_SIZE(x) ((x) << 5)
|
||||
# define R600_L2_DISABLE_LATE_HIT (1 << 9)
|
||||
|
||||
#define R600_ARB_POP 0x2418
|
||||
# define R600_ENABLE_TC128 (1 << 30)
|
||||
#define R600_ARB_GDEC_RD_CNTL 0x246c
|
||||
|
||||
#define R600_TA_CNTL_AUX 0x9508
|
||||
# define R600_DISABLE_CUBE_WRAP (1 << 0)
|
||||
# define R600_DISABLE_CUBE_ANISO (1 << 1)
|
||||
# define R700_GETLOD_SELECT(x) ((x) << 2)
|
||||
# define R600_SYNC_GRADIENT (1 << 24)
|
||||
# define R600_SYNC_WALKER (1 << 25)
|
||||
# define R600_SYNC_ALIGNER (1 << 26)
|
||||
# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
|
||||
# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
|
||||
|
||||
#define R700_TCP_CNTL 0x9610
|
||||
|
||||
#define R600_SMX_DC_CTL0 0xa020
|
||||
# define R700_USE_HASH_FUNCTION (1 << 0)
|
||||
# define R700_CACHE_DEPTH(x) ((x) << 1)
|
||||
# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
|
||||
# define R700_STALL_ON_EVENT (1 << 11)
|
||||
#define R700_SMX_EVENT_CTL 0xa02c
|
||||
# define R700_ES_FLUSH_CTL(x) ((x) << 0)
|
||||
# define R700_GS_FLUSH_CTL(x) ((x) << 3)
|
||||
# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
|
||||
# define R700_SYNC_FLUSH_CTL (1 << 8)
|
||||
|
||||
#define R600_SQ_CONFIG 0x8c00
|
||||
# define R600_VC_ENABLE (1 << 0)
|
||||
# define R600_EXPORT_SRC_C (1 << 1)
|
||||
# define R600_DX9_CONSTS (1 << 2)
|
||||
# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
|
||||
# define R600_DX10_CLAMP (1 << 4)
|
||||
# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
|
||||
# define R600_PS_PRIO(x) ((x) << 24)
|
||||
# define R600_VS_PRIO(x) ((x) << 26)
|
||||
# define R600_GS_PRIO(x) ((x) << 28)
|
||||
# define R600_ES_PRIO(x) ((x) << 30)
|
||||
#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
|
||||
# define R600_NUM_PS_GPRS(x) ((x) << 0)
|
||||
# define R600_NUM_VS_GPRS(x) ((x) << 16)
|
||||
# define R700_DYN_GPR_ENABLE (1 << 27)
|
||||
# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
|
||||
#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
|
||||
# define R600_NUM_GS_GPRS(x) ((x) << 0)
|
||||
# define R600_NUM_ES_GPRS(x) ((x) << 16)
|
||||
#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
|
||||
# define R600_NUM_PS_THREADS(x) ((x) << 0)
|
||||
# define R600_NUM_VS_THREADS(x) ((x) << 8)
|
||||
# define R600_NUM_GS_THREADS(x) ((x) << 16)
|
||||
# define R600_NUM_ES_THREADS(x) ((x) << 24)
|
||||
#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
|
||||
# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
|
||||
# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
|
||||
#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
|
||||
# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
|
||||
# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
|
||||
#define R600_SQ_MS_FIFO_SIZES 0x8cf0
|
||||
# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
|
||||
# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
|
||||
# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
|
||||
# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
|
||||
# define R700_SIMDA_RING0(x) ((x) << 0)
|
||||
# define R700_SIMDA_RING1(x) ((x) << 8)
|
||||
# define R700_SIMDB_RING0(x) ((x) << 16)
|
||||
# define R700_SIMDB_RING1(x) ((x) << 24)
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
|
||||
#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
|
||||
|
||||
#define R600_SPI_PS_IN_CONTROL_0 0x286cc
|
||||
# define R600_NUM_INTERP(x) ((x) << 0)
|
||||
# define R600_POSITION_ENA (1 << 8)
|
||||
# define R600_POSITION_CENTROID (1 << 9)
|
||||
# define R600_POSITION_ADDR(x) ((x) << 10)
|
||||
# define R600_PARAM_GEN(x) ((x) << 15)
|
||||
# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
|
||||
# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
|
||||
# define R600_PERSP_GRADIENT_ENA (1 << 28)
|
||||
# define R600_LINEAR_GRADIENT_ENA (1 << 29)
|
||||
# define R600_POSITION_SAMPLE (1 << 30)
|
||||
# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
|
||||
#define R600_SPI_PS_IN_CONTROL_1 0x286d0
|
||||
# define R600_GEN_INDEX_PIX (1 << 0)
|
||||
# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
|
||||
# define R600_FRONT_FACE_ENA (1 << 8)
|
||||
# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
|
||||
# define R600_FRONT_FACE_ALL_BITS (1 << 11)
|
||||
# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
|
||||
# define R600_FOG_ADDR(x) ((x) << 17)
|
||||
# define R600_FIXED_PT_POSITION_ENA (1 << 24)
|
||||
# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
|
||||
# define R700_POSITION_ULC (1 << 30)
|
||||
#define R600_SPI_INPUT_Z 0x286d8
|
||||
|
||||
#define R600_SPI_CONFIG_CNTL 0x9100
|
||||
# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
|
||||
# define R600_DISABLE_INTERP_1 (1 << 5)
|
||||
#define R600_SPI_CONFIG_CNTL_1 0x913c
|
||||
# define R600_VTX_DONE_DELAY(x) ((x) << 0)
|
||||
# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
|
||||
|
||||
#define R600_GB_TILING_CONFIG 0x98f0
|
||||
# define R600_PIPE_TILING(x) ((x) << 1)
|
||||
# define R600_BANK_TILING(x) ((x) << 4)
|
||||
# define R600_GROUP_SIZE(x) ((x) << 6)
|
||||
# define R600_ROW_TILING(x) ((x) << 8)
|
||||
# define R600_BANK_SWAPS(x) ((x) << 11)
|
||||
# define R600_SAMPLE_SPLIT(x) ((x) << 14)
|
||||
# define R600_BACKEND_MAP(x) ((x) << 16)
|
||||
#define R600_DCP_TILING_CONFIG 0x6ca0
|
||||
#define R600_HDP_TILING_CONFIG 0x2f3c
|
||||
|
||||
#define R600_CC_RB_BACKEND_DISABLE 0x98f4
|
||||
#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
|
||||
# define R600_BACKEND_DISABLE(x) ((x) << 16)
|
||||
|
||||
#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
|
||||
#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
|
||||
# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
|
||||
# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
|
||||
# define R600_INACTIVE_SIMDS(x) ((x) << 16)
|
||||
# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
|
||||
|
||||
#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
|
||||
#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
|
||||
#define R700_CGTS_TCC_DISABLE 0x9148
|
||||
#define R700_CGTS_USER_TCC_DISABLE 0x914c
|
||||
|
||||
/* Constants */
|
||||
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
|
||||
|
||||
@ -1192,6 +1663,11 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
|
||||
#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
|
||||
#define RADEON_LAST_DISPATCH 1
|
||||
|
||||
#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
|
||||
#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
|
||||
#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
|
||||
#define R600_LAST_SWI_REG R600_SCRATCH_REG3
|
||||
|
||||
#define RADEON_MAX_VB_AGE 0x7fffffff
|
||||
#define RADEON_MAX_VB_VERTS (0xffff)
|
||||
|
||||
@ -1200,7 +1676,15 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
|
||||
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
|
||||
|
||||
#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
|
||||
#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
|
||||
#define RADEON_WRITE(reg, val) \
|
||||
do { \
|
||||
if (reg < 0x10000) { \
|
||||
DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
|
||||
} else { \
|
||||
DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
|
||||
DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
|
||||
} \
|
||||
} while (0)
|
||||
#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
|
||||
#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
|
||||
|
||||
@ -1370,6 +1854,24 @@ do { \
|
||||
OUT_RING( age ); \
|
||||
} while (0)
|
||||
|
||||
#define R600_DISPATCH_AGE(age) do { \
|
||||
OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
|
||||
OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
|
||||
OUT_RING(age); \
|
||||
} while (0)
|
||||
|
||||
#define R600_FRAME_AGE(age) do { \
|
||||
OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
|
||||
OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
|
||||
OUT_RING(age); \
|
||||
} while (0)
|
||||
|
||||
#define R600_CLEAR_AGE(age) do { \
|
||||
OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
|
||||
OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
|
||||
OUT_RING(age); \
|
||||
} while (0)
|
||||
|
||||
/* ================================================================
|
||||
* Ring control
|
||||
*/
|
||||
|
||||
@ -304,6 +304,8 @@ typedef union {
|
||||
|
||||
#define RADEON_SCRATCH_REG_OFFSET 32
|
||||
|
||||
#define R600_SCRATCH_REG_OFFSET 256
|
||||
|
||||
#define RADEON_NR_SAREA_CLIPRECTS 12
|
||||
|
||||
/* There are 2 heaps (local/GART). Each region within a heap is a
|
||||
@ -526,7 +528,8 @@ typedef struct drm_radeon_init {
|
||||
RADEON_INIT_CP = 0x01,
|
||||
RADEON_CLEANUP_CP = 0x02,
|
||||
RADEON_INIT_R200_CP = 0x03,
|
||||
RADEON_INIT_R300_CP = 0x04
|
||||
RADEON_INIT_R300_CP = 0x04,
|
||||
RADEON_INIT_R600_CP = 0x05
|
||||
} func;
|
||||
unsigned long sarea_priv_offset;
|
||||
int is_pci;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user