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RISC-V Patches for the 6.3 Merge Window, Part 2

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* Some cleanups and fixes for the Zbb-optimized string routines.
 * Support for custom (vendor or implementation defined) perf events.
 * COMMAND_LINE_SIZE has been increased to 1024.
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Merge tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull more RISC-V updates from Palmer Dabbelt:

 - Some cleanups and fixes for the Zbb-optimized string routines

 - Support for custom (vendor or implementation defined) perf events

 - COMMAND_LINE_SIZE has been increased to 1024

* tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Bump COMMAND_LINE_SIZE value to 1024
  drivers/perf: RISC-V: Allow programming custom firmware events
  riscv, lib: Fix Zbb strncmp
  RISC-V: improve string-function assembly
This commit is contained in:
Linus Torvalds 2023-03-03 09:32:51 -08:00
commit bf1a1bad82
5 changed files with 29 additions and 22 deletions
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8
arch/riscv/include/uapi/asm/setup.h Normal file
View File

@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
#ifndef _UAPI_ASM_RISCV_SETUP_H
#define _UAPI_ASM_RISCV_SETUP_H
#define COMMAND_LINE_SIZE 1024
#endif /* _UAPI_ASM_RISCV_SETUP_H */

6
arch/riscv/lib/strcmp.S
View File

@ -40,7 +40,9 @@ SYM_FUNC_START(strcmp)
ret ret
/* /*
* Variant of strcmp using the ZBB extension if available * Variant of strcmp using the ZBB extension if available.
* The code was published as part of the bitmanip manual
* in Appendix A.
*/ */
#ifdef CONFIG_RISCV_ISA_ZBB #ifdef CONFIG_RISCV_ISA_ZBB
strcmp_zbb: strcmp_zbb:
@ -57,7 +59,7 @@ strcmp_zbb:
* a1 - string2 * a1 - string2
* *
* Clobbers * Clobbers
* t0, t1, t2, t3, t4, t5 * t0, t1, t2, t3, t4
*/ */
or t2, a0, a1 or t2, a0, a1

10
arch/riscv/lib/strlen.S
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@ -96,7 +96,7 @@ strlen_zbb:
* of valid bytes in this chunk. * of valid bytes in this chunk.
*/ */
srli a0, t1, 3 srli a0, t1, 3
bgtu t3, a0, 3f bgtu t3, a0, 2f
/* Prepare for the word comparison loop. */ /* Prepare for the word comparison loop. */
addi t2, t0, SZREG addi t2, t0, SZREG
@ -112,20 +112,20 @@ strlen_zbb:
addi t0, t0, SZREG addi t0, t0, SZREG
orc.b t1, t1 orc.b t1, t1
beq t1, t3, 1b beq t1, t3, 1b
2:
not t1, t1 not t1, t1
CZ t1, t1 CZ t1, t1
srli t1, t1, 3
/* Get number of processed words. */ /* Get number of processed bytes. */
sub t2, t0, t2 sub t2, t0, t2
/* Add number of characters in the first word. */ /* Add number of characters in the first word. */
add a0, a0, t2 add a0, a0, t2
srli t1, t1, 3
/* Add number of characters in the last word. */ /* Add number of characters in the last word. */
add a0, a0, t1 add a0, a0, t1
3: 2:
ret ret
.option pop .option pop

20
arch/riscv/lib/strncmp.S
View File

@ -70,7 +70,7 @@ strncmp_zbb:
li t5, -1 li t5, -1
and t2, t2, SZREG-1 and t2, t2, SZREG-1
add t4, a0, a2 add t4, a0, a2
bnez t2, 4f bnez t2, 3f
/* Adjust limit for fast-path. */ /* Adjust limit for fast-path. */
andi t6, t4, -SZREG andi t6, t4, -SZREG
@ -78,11 +78,13 @@ strncmp_zbb:
/* Main loop for aligned string. */ /* Main loop for aligned string. */
.p2align 3 .p2align 3
1: 1:
bgt a0, t6, 3f bge a0, t6, 3f
REG_L t0, 0(a0) REG_L t0, 0(a0)
REG_L t1, 0(a1) REG_L t1, 0(a1)
orc.b t3, t0 orc.b t3, t0
bne t3, t5, 2f bne t3, t5, 2f
orc.b t3, t1
bne t3, t5, 2f
addi a0, a0, SZREG addi a0, a0, SZREG
addi a1, a1, SZREG addi a1, a1, SZREG
beq t0, t1, 1b beq t0, t1, 1b
@ -114,23 +116,21 @@ strncmp_zbb:
ret ret
/* Simple loop for misaligned strings. */ /* Simple loop for misaligned strings. */
3:
/* Restore limit for slow-path. */
.p2align 3 .p2align 3
4: 3:
bge a0, t4, 6f bge a0, t4, 5f
lbu t0, 0(a0) lbu t0, 0(a0)
lbu t1, 0(a1) lbu t1, 0(a1)
addi a0, a0, 1 addi a0, a0, 1
addi a1, a1, 1 addi a1, a1, 1
bne t0, t1, 5f bne t0, t1, 4f
bnez t0, 4b bnez t0, 3b
5: 4:
sub a0, t0, t1 sub a0, t0, t1
ret ret
6: 5:
li a0, 0 li a0, 0
ret ret

7
drivers/perf/riscv_pmu_sbi.c
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@ -436,11 +436,8 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
bSoftware = config >> 63; bSoftware = config >> 63;
raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK; raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK;
if (bSoftware) { if (bSoftware) {
if (raw_config_val < SBI_PMU_FW_MAX) ret = (raw_config_val & 0xFFFF) |
ret = (raw_config_val & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16);
(SBI_PMU_EVENT_TYPE_FW << 16);
else
return -EINVAL;
} else { } else {
ret = RISCV_PMU_RAW_EVENT_IDX; ret = RISCV_PMU_RAW_EVENT_IDX;
*econfig = raw_config_val; *econfig = raw_config_val;