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drm/xe/irq: Drop commented-out code for non-existent media engines

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Although the hardware team has set aside some register bits for extra
media engines, no platform supported by the Xe driver today has VCS4-7
or VECS2-3.  Drop the corresponding code (which was already commented
out); we can bring it back easily enough if such engines show up on a
future platform.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230401002106.588656-8-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-03-31 17:21:05 -07:00 committed by Rodrigo Vivi
parent c94cd8f2d2
commit bf26d6984c
1 changed files with 0 additions and 12 deletions
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12
drivers/gpu/drm/xe/xe_irq.c
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@ -150,13 +150,7 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~dmask);
xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~dmask);
xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~dmask);
//if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
// intel_uncore_write(uncore, VCS4_VCS5_INTR_MASK, ~dmask);
//if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
// intel_uncore_write(uncore, VCS6_VCS7_INTR_MASK, ~dmask);
xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~dmask);
//if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
// intel_uncore_write(uncore, VECS2_VECS3_INTR_MASK, ~dmask);
if (ccs_mask & (BIT(0)|BIT(1)))
xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~dmask);
if (ccs_mask & (BIT(2)|BIT(3)))
@ -423,13 +417,7 @@ static void gt_irq_reset(struct xe_gt *gt)
xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~0);
xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~0);
xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~0);
// if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
// xe_mmio_write32(xe, VCS4_VCS5_INTR_MASK.reg, ~0);
// if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
// xe_mmio_write32(xe, VCS6_VCS7_INTR_MASK.reg, ~0);
xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~0);
// if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
// xe_mmio_write32(xe, VECS2_VECS3_INTR_MASK.reg, ~0);
if (ccs_mask & (BIT(0)|BIT(1)))
xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~0);
if (ccs_mask & (BIT(2)|BIT(3)))