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clk: renesas: rzg2l: Trust value returned by hardware

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The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b.  The
hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that
setting 0 is prohibited.  Hence rzg2l_cpg_sd_clk_mux_get_parent() should
just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock
parent index based on the value read.

Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-5-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2023-09-29 08:38:51 +03:00 committed by Geert Uytterhoeven
parent d2692ed490
commit bf51d3b2d0
1 changed files with 1 additions and 7 deletions
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8
drivers/clk/renesas/rzg2l-cpg.c
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@ -238,14 +238,8 @@ static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
val >>= GET_SHIFT(hwdata->conf); val >>= GET_SHIFT(hwdata->conf);
val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0);
if (val) {
val--;
} else {
/* Prohibited clk source, change it to 533 MHz(reset value) */
rzg2l_cpg_sd_clk_mux_set_parent(hw, 0);
}
return val; return val ? val - 1 : 0;
} }
static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = { static const struct clk_ops rzg2l_cpg_sd_clk_mux_ops = {