selftest: kvm: Add amx selftest
This selftest covers two aspects of AMX. The first is triggering #NM exception and checking the MSR XFD_ERR value. The second case is loading tile config and tile data into guest registers and trapping to the host side for a complete save/load of the guest state. TMM0 is also checked against memory data after save/restore. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20211223145322.2914028-4-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Yang Zhong
Paolo Bonzini
parent
6559b4a523
commit
bf70636d94
@ -82,6 +82,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/xen_shinfo_test
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TEST_GEN_PROGS_x86_64 += x86_64/xen_vmcall_test
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TEST_GEN_PROGS_x86_64 += x86_64/vmx_pi_mmio_test
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TEST_GEN_PROGS_x86_64 += x86_64/sev_migrate_tests
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TEST_GEN_PROGS_x86_64 += x86_64/amx_test
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TEST_GEN_PROGS_x86_64 += demand_paging_test
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TEST_GEN_PROGS_x86_64 += dirty_log_test
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TEST_GEN_PROGS_x86_64 += dirty_log_perf_test
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448
tools/testing/selftests/kvm/x86_64/amx_test.c
Normal file
448
tools/testing/selftests/kvm/x86_64/amx_test.c
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@ -0,0 +1,448 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* amx tests
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*
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* Copyright (C) 2021, Intel, Inc.
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*
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* Tests for amx #NM exception and save/restore.
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*/
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#define _GNU_SOURCE /* for program_invocation_short_name */
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/ioctl.h>
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#include <sys/syscall.h>
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#include "test_util.h"
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#include "kvm_util.h"
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#include "processor.h"
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#include "vmx.h"
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#ifndef __x86_64__
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# error This test is 64-bit only
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#endif
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#define VCPU_ID 0
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#define X86_FEATURE_XSAVE (1 << 26)
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#define X86_FEATURE_OSXSAVE (1 << 27)
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#define PAGE_SIZE (1 << 12)
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#define NUM_TILES 8
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#define TILE_SIZE 1024
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#define XSAVE_SIZE ((NUM_TILES * TILE_SIZE) + PAGE_SIZE)
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/* Tile configuration associated: */
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#define MAX_TILES 16
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#define RESERVED_BYTES 14
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#define XFEATURE_XTILECFG 17
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#define XFEATURE_XTILEDATA 18
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#define XFEATURE_MASK_XTILECFG (1 << XFEATURE_XTILECFG)
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#define XFEATURE_MASK_XTILEDATA (1 << XFEATURE_XTILEDATA)
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#define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILEDATA)
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#define TILE_CPUID 0x1d
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#define XSTATE_CPUID 0xd
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#define TILE_PALETTE_CPUID_SUBLEAVE 0x1
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#define XSTATE_USER_STATE_SUBLEAVE 0x0
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#define XSAVE_HDR_OFFSET 512
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struct xsave_data {
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u8 area[XSAVE_SIZE];
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} __aligned(64);
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struct tile_config {
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u8 palette_id;
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u8 start_row;
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u8 reserved[RESERVED_BYTES];
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u16 colsb[MAX_TILES];
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u8 rows[MAX_TILES];
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};
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struct tile_data {
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u8 data[NUM_TILES * TILE_SIZE];
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};
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struct xtile_info {
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u16 bytes_per_tile;
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u16 bytes_per_row;
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u16 max_names;
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u16 max_rows;
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u32 xsave_offset;
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u32 xsave_size;
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};
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static struct xtile_info xtile;
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static inline u64 __xgetbv(u32 index)
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{
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u32 eax, edx;
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asm volatile("xgetbv;"
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: "=a" (eax), "=d" (edx)
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: "c" (index));
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return eax + ((u64)edx << 32);
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}
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static inline void __xsetbv(u32 index, u64 value)
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{
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u32 eax = value;
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u32 edx = value >> 32;
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asm volatile("xsetbv" :: "a" (eax), "d" (edx), "c" (index));
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}
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static inline void __ldtilecfg(void *cfg)
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{
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asm volatile(".byte 0xc4,0xe2,0x78,0x49,0x00"
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: : "a"(cfg));
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}
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static inline void __tileloadd(void *tile)
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{
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asm volatile(".byte 0xc4,0xe2,0x7b,0x4b,0x04,0x10"
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: : "a"(tile), "d"(0));
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}
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static inline void __tilerelease(void)
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{
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asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0" ::);
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}
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static inline void __xsavec(struct xsave_data *data, uint64_t rfbm)
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{
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uint32_t rfbm_lo = rfbm;
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uint32_t rfbm_hi = rfbm >> 32;
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asm volatile("xsavec (%%rdi)"
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: : "D" (data), "a" (rfbm_lo), "d" (rfbm_hi)
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: "memory");
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}
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static inline void check_cpuid_xsave(void)
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{
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uint32_t eax, ebx, ecx, edx;
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eax = 1;
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ecx = 0;
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cpuid(&eax, &ebx, &ecx, &edx);
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if (!(ecx & X86_FEATURE_XSAVE))
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GUEST_ASSERT(!"cpuid: no CPU xsave support!");
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if (!(ecx & X86_FEATURE_OSXSAVE))
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GUEST_ASSERT(!"cpuid: no OS xsave support!");
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}
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static bool check_xsave_supports_xtile(void)
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{
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return __xgetbv(0) & XFEATURE_MASK_XTILE;
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}
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static bool enum_xtile_config(void)
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{
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u32 eax, ebx, ecx, edx;
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eax = TILE_CPUID;
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ecx = TILE_PALETTE_CPUID_SUBLEAVE;
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cpuid(&eax, &ebx, &ecx, &edx);
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if (!eax || !ebx || !ecx)
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return false;
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xtile.max_names = ebx >> 16;
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if (xtile.max_names < NUM_TILES)
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return false;
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xtile.bytes_per_tile = eax >> 16;
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if (xtile.bytes_per_tile < TILE_SIZE)
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return false;
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xtile.bytes_per_row = ebx;
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xtile.max_rows = ecx;
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return true;
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}
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static bool enum_xsave_tile(void)
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{
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u32 eax, ebx, ecx, edx;
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eax = XSTATE_CPUID;
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ecx = XFEATURE_XTILEDATA;
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cpuid(&eax, &ebx, &ecx, &edx);
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if (!eax || !ebx)
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return false;
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xtile.xsave_offset = ebx;
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xtile.xsave_size = eax;
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return true;
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}
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static bool check_xsave_size(void)
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{
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u32 eax, ebx, ecx, edx;
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bool valid = false;
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eax = XSTATE_CPUID;
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ecx = XSTATE_USER_STATE_SUBLEAVE;
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cpuid(&eax, &ebx, &ecx, &edx);
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if (ebx && ebx <= XSAVE_SIZE)
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valid = true;
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return valid;
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}
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static bool check_xtile_info(void)
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{
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bool ret = false;
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if (!check_xsave_size())
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return ret;
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if (!enum_xsave_tile())
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return ret;
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if (!enum_xtile_config())
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return ret;
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if (sizeof(struct tile_data) >= xtile.xsave_size)
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ret = true;
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return ret;
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}
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static void set_tilecfg(struct tile_config *cfg)
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{
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int i;
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/* Only palette id 1 */
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cfg->palette_id = 1;
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for (i = 0; i < xtile.max_names; i++) {
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cfg->colsb[i] = xtile.bytes_per_row;
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cfg->rows[i] = xtile.max_rows;
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}
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}
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static void set_xstatebv(void *data, uint64_t bv)
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{
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*(uint64_t *)(data + XSAVE_HDR_OFFSET) = bv;
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}
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static u64 get_xstatebv(void *data)
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{
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return *(u64 *)(data + XSAVE_HDR_OFFSET);
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}
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static void init_regs(void)
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{
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uint64_t cr4, xcr0;
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/* turn on CR4.OSXSAVE */
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cr4 = get_cr4();
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cr4 |= X86_CR4_OSXSAVE;
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set_cr4(cr4);
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xcr0 = __xgetbv(0);
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xcr0 |= XFEATURE_MASK_XTILE;
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__xsetbv(0x0, xcr0);
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}
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static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
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struct tile_data *tiledata,
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struct xsave_data *xsave_data)
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{
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init_regs();
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check_cpuid_xsave();
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GUEST_ASSERT(check_xsave_supports_xtile());
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GUEST_ASSERT(check_xtile_info());
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/* check xtile configs */
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GUEST_ASSERT(xtile.xsave_offset == 2816);
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GUEST_ASSERT(xtile.xsave_size == 8192);
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GUEST_ASSERT(xtile.max_names == 8);
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GUEST_ASSERT(xtile.bytes_per_tile == 1024);
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GUEST_ASSERT(xtile.bytes_per_row == 64);
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GUEST_ASSERT(xtile.max_rows == 16);
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GUEST_SYNC(1);
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/* xfd=0, enable amx */
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wrmsr(MSR_IA32_XFD, 0);
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GUEST_SYNC(2);
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GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == 0);
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set_tilecfg(amx_cfg);
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__ldtilecfg(amx_cfg);
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GUEST_SYNC(3);
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/* Check save/restore when trap to userspace */
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__tileloadd(tiledata);
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GUEST_SYNC(4);
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__tilerelease();
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GUEST_SYNC(5);
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/* bit 18 not in the XCOMP_BV after xsavec() */
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set_xstatebv(xsave_data, XFEATURE_MASK_XTILEDATA);
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__xsavec(xsave_data, XFEATURE_MASK_XTILEDATA);
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GUEST_ASSERT((get_xstatebv(xsave_data) & XFEATURE_MASK_XTILEDATA) == 0);
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/* xfd=0x40000, disable amx tiledata */
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wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);
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GUEST_SYNC(6);
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GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
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set_tilecfg(amx_cfg);
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__ldtilecfg(amx_cfg);
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/* Trigger #NM exception */
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__tileloadd(tiledata);
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GUEST_SYNC(10);
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GUEST_DONE();
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}
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void guest_nm_handler(struct ex_regs *regs)
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{
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/* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */
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GUEST_SYNC(7);
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GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
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GUEST_SYNC(8);
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GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
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/* Clear xfd_err */
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wrmsr(MSR_IA32_XFD_ERR, 0);
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/* xfd=0, enable amx */
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wrmsr(MSR_IA32_XFD, 0);
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GUEST_SYNC(9);
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}
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int main(int argc, char *argv[])
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{
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struct kvm_cpuid_entry2 *entry;
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struct kvm_regs regs1, regs2;
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bool amx_supported = false;
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struct kvm_vm *vm;
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struct kvm_run *run;
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struct kvm_x86_state *state;
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int xsave_restore_size = 0;
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vm_vaddr_t amx_cfg, tiledata, xsavedata;
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struct ucall uc;
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u32 amx_offset;
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int stage, ret;
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/* Create VM */
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vm = vm_create_default(VCPU_ID, 0, guest_code);
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entry = kvm_get_supported_cpuid_entry(1);
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if (!(entry->ecx & X86_FEATURE_XSAVE)) {
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print_skip("XSAVE feature not supported");
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exit(KSFT_SKIP);
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}
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if (kvm_get_cpuid_max_basic() >= 0xd) {
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entry = kvm_get_supported_cpuid_index(0xd, 0);
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amx_supported = entry && !!(entry->eax & XFEATURE_MASK_XTILE);
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if (!amx_supported) {
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print_skip("AMX is not supported by the vCPU (eax=0x%x)", entry->eax);
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exit(KSFT_SKIP);
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}
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/* Get xsave/restore max size */
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xsave_restore_size = entry->ecx;
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}
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run = vcpu_state(vm, VCPU_ID);
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vcpu_regs_get(vm, VCPU_ID, ®s1);
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/* Register #NM handler */
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vm_init_descriptor_tables(vm);
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vcpu_init_descriptor_tables(vm, VCPU_ID);
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vm_install_exception_handler(vm, NM_VECTOR, guest_nm_handler);
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/* amx cfg for guest_code */
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amx_cfg = vm_vaddr_alloc_page(vm);
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memset(addr_gva2hva(vm, amx_cfg), 0x0, getpagesize());
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/* amx tiledata for guest_code */
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tiledata = vm_vaddr_alloc_pages(vm, 2);
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memset(addr_gva2hva(vm, tiledata), rand() | 1, 2 * getpagesize());
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/* xsave data for guest_code */
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xsavedata = vm_vaddr_alloc_pages(vm, 3);
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memset(addr_gva2hva(vm, xsavedata), 0, 3 * getpagesize());
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vcpu_args_set(vm, VCPU_ID, 3, amx_cfg, tiledata, xsavedata);
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for (stage = 1; ; stage++) {
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_vcpu_run(vm, VCPU_ID);
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TEST_ASSERT(run->exit_reason == KVM_EXIT_IO,
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"Stage %d: unexpected exit reason: %u (%s),\n",
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stage, run->exit_reason,
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exit_reason_str(run->exit_reason));
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switch (get_ucall(vm, VCPU_ID, &uc)) {
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case UCALL_ABORT:
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TEST_FAIL("%s at %s:%ld", (const char *)uc.args[0],
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__FILE__, uc.args[1]);
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/* NOT REACHED */
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case UCALL_SYNC:
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switch (uc.args[1]) {
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case 1:
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case 2:
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case 3:
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case 5:
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case 6:
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case 7:
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case 8:
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fprintf(stderr, "GUEST_SYNC(%ld)\n", uc.args[1]);
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break;
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case 4:
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case 10:
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fprintf(stderr,
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"GUEST_SYNC(%ld), check save/restore status\n", uc.args[1]);
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/* Compacted mode, get amx offset by xsave area
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* size subtract 8K amx size.
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*/
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amx_offset = xsave_restore_size - NUM_TILES*TILE_SIZE;
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state = vcpu_save_state(vm, VCPU_ID);
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void *amx_start = (void *)state->xsave + amx_offset;
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void *tiles_data = (void *)addr_gva2hva(vm, tiledata);
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/* Only check TMM0 register, 1 tile */
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ret = memcmp(amx_start, tiles_data, TILE_SIZE);
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TEST_ASSERT(ret == 0, "memcmp failed, ret=%d\n", ret);
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kvm_x86_state_cleanup(state);
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break;
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case 9:
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fprintf(stderr,
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"GUEST_SYNC(%ld), #NM exception and enable amx\n", uc.args[1]);
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break;
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}
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break;
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case UCALL_DONE:
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fprintf(stderr, "UCALL_DONE\n");
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goto done;
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default:
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TEST_FAIL("Unknown ucall %lu", uc.cmd);
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}
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state = vcpu_save_state(vm, VCPU_ID);
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memset(®s1, 0, sizeof(regs1));
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vcpu_regs_get(vm, VCPU_ID, ®s1);
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kvm_vm_release(vm);
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/* Restore state in a new VM. */
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kvm_vm_restart(vm, O_RDWR);
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vm_vcpu_add(vm, VCPU_ID);
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vcpu_set_cpuid(vm, VCPU_ID, kvm_get_supported_cpuid());
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vcpu_load_state(vm, VCPU_ID, state);
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run = vcpu_state(vm, VCPU_ID);
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kvm_x86_state_cleanup(state);
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memset(®s2, 0, sizeof(regs2));
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vcpu_regs_get(vm, VCPU_ID, ®s2);
|
||||
TEST_ASSERT(!memcmp(®s1, ®s2, sizeof(regs2)),
|
||||
"Unexpected register values after vcpu_load_state; rdi: %lx rsi: %lx",
|
||||
(ulong) regs2.rdi, (ulong) regs2.rsi);
|
||||
}
|
||||
done:
|
||||
kvm_vm_free(vm);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user