KVM: x86: Implement Intel PT MSRs read/write emulation
This patch implement Intel Processor Trace MSRs read/write emulation. Intel PT MSRs read/write need to be emulated when Intel PT MSRs is intercepted in guest and during live migration. Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Chao Peng
Paolo Bonzini
parent
6c0f0bba85
commit
bf8c55d8dc
@ -140,6 +140,14 @@ module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
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#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
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#define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
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RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
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RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
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RTIT_STATUS_BYTECNT))
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#define MSR_IA32_RTIT_OUTPUT_BASE_MASK \
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(~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f)
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/*
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* These 2 parameters are used to config the controls for Pause-Loop Exiting:
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* ple_gap: upper bound on the amount of time between two successive
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@ -1354,6 +1362,79 @@ void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
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vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
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}
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static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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unsigned long value;
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/*
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* Any MSR write that attempts to change bits marked reserved will
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* case a #GP fault.
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*/
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if (data & vmx->pt_desc.ctl_bitmask)
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return 1;
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/*
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* Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
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* result in a #GP unless the same write also clears TraceEn.
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*/
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if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) &&
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((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN))
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return 1;
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/*
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* WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
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* and FabricEn would cause #GP, if
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* CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
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*/
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if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) &&
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!(data & RTIT_CTL_FABRIC_EN) &&
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_single_range_output))
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return 1;
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/*
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* MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
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* utilize encodings marked reserved will casue a #GP fault.
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*/
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value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods);
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if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) &&
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!test_bit((data & RTIT_CTL_MTC_RANGE) >>
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RTIT_CTL_MTC_RANGE_OFFSET, &value))
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return 1;
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value = intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_cycle_thresholds);
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if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
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!test_bit((data & RTIT_CTL_CYC_THRESH) >>
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RTIT_CTL_CYC_THRESH_OFFSET, &value))
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return 1;
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value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods);
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if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) &&
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!test_bit((data & RTIT_CTL_PSB_FREQ) >>
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RTIT_CTL_PSB_FREQ_OFFSET, &value))
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return 1;
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/*
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* If ADDRx_CFG is reserved or the encodings is >2 will
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* cause a #GP fault.
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*/
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value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET;
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if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2))
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return 1;
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value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET;
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if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2))
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return 1;
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value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET;
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if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2))
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return 1;
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value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET;
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if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2))
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return 1;
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return 0;
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}
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static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
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{
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unsigned long rip;
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@ -1555,6 +1636,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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struct shared_msr_entry *msr;
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u32 index;
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switch (msr_info->index) {
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#ifdef CONFIG_X86_64
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@ -1619,6 +1701,52 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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msr_info->data = vcpu->arch.ia32_xss;
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break;
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case MSR_IA32_RTIT_CTL:
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if (pt_mode != PT_MODE_HOST_GUEST)
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return 1;
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msr_info->data = vmx->pt_desc.guest.ctl;
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break;
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case MSR_IA32_RTIT_STATUS:
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if (pt_mode != PT_MODE_HOST_GUEST)
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return 1;
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msr_info->data = vmx->pt_desc.guest.status;
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break;
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case MSR_IA32_RTIT_CR3_MATCH:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_cr3_filtering))
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return 1;
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msr_info->data = vmx->pt_desc.guest.cr3_match;
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break;
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case MSR_IA32_RTIT_OUTPUT_BASE:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_topa_output) &&
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_single_range_output)))
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return 1;
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msr_info->data = vmx->pt_desc.guest.output_base;
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break;
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case MSR_IA32_RTIT_OUTPUT_MASK:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_topa_output) &&
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_single_range_output)))
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return 1;
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msr_info->data = vmx->pt_desc.guest.output_mask;
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break;
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case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
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index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_num_address_ranges)))
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return 1;
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if (index % 2)
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msr_info->data = vmx->pt_desc.guest.addr_b[index / 2];
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else
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msr_info->data = vmx->pt_desc.guest.addr_a[index / 2];
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break;
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case MSR_TSC_AUX:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
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@ -1648,6 +1776,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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int ret = 0;
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u32 msr_index = msr_info->index;
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u64 data = msr_info->data;
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u32 index;
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switch (msr_index) {
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case MSR_EFER:
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@ -1799,6 +1928,61 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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else
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clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
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break;
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case MSR_IA32_RTIT_CTL:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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vmx_rtit_ctl_check(vcpu, data))
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return 1;
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vmcs_write64(GUEST_IA32_RTIT_CTL, data);
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vmx->pt_desc.guest.ctl = data;
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break;
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case MSR_IA32_RTIT_STATUS:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
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(data & MSR_IA32_RTIT_STATUS_MASK))
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return 1;
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vmx->pt_desc.guest.status = data;
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break;
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case MSR_IA32_RTIT_CR3_MATCH:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_cr3_filtering))
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return 1;
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vmx->pt_desc.guest.cr3_match = data;
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break;
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case MSR_IA32_RTIT_OUTPUT_BASE:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
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(!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_topa_output) &&
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_single_range_output)) ||
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(data & MSR_IA32_RTIT_OUTPUT_BASE_MASK))
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return 1;
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vmx->pt_desc.guest.output_base = data;
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break;
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case MSR_IA32_RTIT_OUTPUT_MASK:
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
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(!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_topa_output) &&
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!intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_single_range_output)))
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return 1;
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vmx->pt_desc.guest.output_mask = data;
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break;
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case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
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index = msr_info->index - MSR_IA32_RTIT_ADDR0_A;
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if ((pt_mode != PT_MODE_HOST_GUEST) ||
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(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) ||
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(index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps,
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PT_CAP_num_address_ranges)))
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return 1;
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if (index % 2)
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vmx->pt_desc.guest.addr_b[index / 2] = data;
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else
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vmx->pt_desc.guest.addr_a[index / 2] = data;
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break;
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case MSR_TSC_AUX:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
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@ -69,6 +69,7 @@
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#include <asm/irq_remapping.h>
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#include <asm/mshyperv.h>
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#include <asm/hypervisor.h>
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#include <asm/intel_pt.h>
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#define CREATE_TRACE_POINTS
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#include "trace.h"
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@ -1124,7 +1125,13 @@ static u32 msrs_to_save[] = {
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#endif
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MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
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MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
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MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
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MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES,
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MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
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MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
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MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
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MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
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MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
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MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
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};
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static unsigned num_msrs_to_save;
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@ -4884,6 +4891,30 @@ static void kvm_init_msr_list(void)
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if (!kvm_x86_ops->rdtscp_supported())
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continue;
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break;
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case MSR_IA32_RTIT_CTL:
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case MSR_IA32_RTIT_STATUS:
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if (!kvm_x86_ops->pt_supported())
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continue;
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break;
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case MSR_IA32_RTIT_CR3_MATCH:
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if (!kvm_x86_ops->pt_supported() ||
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!intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
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continue;
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break;
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case MSR_IA32_RTIT_OUTPUT_BASE:
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case MSR_IA32_RTIT_OUTPUT_MASK:
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if (!kvm_x86_ops->pt_supported() ||
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(!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
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!intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
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continue;
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break;
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case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
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if (!kvm_x86_ops->pt_supported() ||
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msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
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intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
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continue;
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break;
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}
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default:
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break;
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}
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