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MIPS: microMIPS: Add instruction utility macros.

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Add two new macros for microMIPS. One checks if an exception was
taken in either microMIPS or classic MIPS mode. The other checks
if a microMIPS instruction is 16-bit or 32-bit in length.

[ralf@linux-mips.org: Removed unnecessary parenthesis as noted by
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>]

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: kevink@paralogos.com
Cc: ddaney.cavm@gmail.com
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Patchwork: https://patchwork.linux-mips.org/patch/4924/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 49df26472338b935fd5781bf94a77a88b148a716)
This commit is contained in:
Steven J. Hill 2013-02-05 16:52:03 -06:00 committed by Steven J. Hill
parent a6a4834cdb
commit bfd08baae4
1 changed files with 18 additions and 0 deletions
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18
arch/mips/include/asm/mipsregs.h
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@ -622,6 +622,24 @@
#ifndef __ASSEMBLY__
/*
* Macros for handling the ISA mode bit for microMIPS.
*/
#define get_isa16_mode(x) ((x) & 0x1)
#define msk_isa16_mode(x) ((x) & ~0x1)
#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
/*
* microMIPS instructions can be 16-bit or 32-bit in length. This
* returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
*/
static inline int mm_insn_16bit(u16 insn)
{
u16 opcode = (insn >> 10) & 0x7;
return (opcode >= 1 && opcode <= 3) ? 1 : 0;
}
/*
* Functions to access the R10000 performance counters. These are basically
* mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit