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SoC DT updates for v6.7

Browse Source 
There are a couple new SoCs that are supported for the first time:
 
  - AMD Pensando Elba is a data processing unit based on Cortex-A72
    CPU cores
 
  - Sophgo makes RISC-V based chips, and we now support the CV1800B
    chip used in the milkv-duo board and the massive sg2042 chip in the
    milkv-pioneer, a 64-core developer workstation.
 
  - Qualcomm Snapdragon 720G (sm7125) is a close relative of
    Snapdragon 7c and gets added with some Xiaomi phones
 
  - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive
    SoC and the RZ/G3S (R9A08G045) embedded SoC.
 
 There are also a bunch of newly supported machines that use
 already supported chips. On the 32-bit side, we have:
 
  - USRobotics USR8200 is a NAS/Firewall/router based on the ancient
    Intel IXP4xx platform
 
  - A couple of machines based on the NXP i.MX5 and i.MX6 platforms
 
  - One machine each for Allwinner V3s, Aspeed AST2600, Microchip
    sama5d29 and ST STM32mp157
 
 The other ones all use arm64 cores on chips from allwinner,
 amlogic, freescale, mediatek, qualcomm and rockchip.
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Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC DT updates from Arnd Bergmann:
 "There are a couple new SoCs that are supported for the first time:

   - AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU
     cores

   - Sophgo makes RISC-V based chips, and we now support the CV1800B
     chip used in the milkv-duo board and the massive sg2042 chip in the
     milkv-pioneer, a 64-core developer workstation.

   - Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon
     7c and gets added with some Xiaomi phones

   - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC
     and the RZ/G3S (R9A08G045) embedded SoC.

  There are also a bunch of newly supported machines that use already
  supported chips. On the 32-bit side, we have:

   - USRobotics USR8200 is a NAS/Firewall/router based on the ancient
     Intel IXP4xx platform

   - A couple of machines based on the NXP i.MX5 and i.MX6 platforms

   - One machine each for Allwinner V3s, Aspeed AST2600, Microchip
     sama5d29 and ST STM32mp157

  The other ones all use arm64 cores on chips from allwinner, amlogic,
  freescale, mediatek, qualcomm and rockchip"

* tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits)
  ARM: dts: BCM5301X: Set switch ports for Linksys EA9200
  ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports
  ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports
  ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT
  ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT
  ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U
  arm64: dts: socionext: add missing cache properties
  riscv: dts: thead: convert isa detection to new properties
  arm64: dts: Update cache properties for socionext
  arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
  arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support
  arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
  arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM
  arm64: dts: ti: k3-am62p: Add nodes for more IPs
  arm64: dts: rockchip: Add Turing RK1 SoM support
  dt-bindings: arm: rockchip: Add Turing RK1
  dt-bindings: vendor-prefixes: add turing
  arm64: dts: rockchip: Add DFI to rk3588s
  arm64: dts: rockchip: Add DFI to rk356x
  arm64: dts: rockchip: Always enable DFI on rk3399
  ...
This commit is contained in:
Linus Torvalds 2023-11-01 14:37:04 -10:00
commit c035f0268b
640 changed files with 31395 additions and 3114 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
Documentation/devicetree/bindings/arm/amd,pensando.yaml Normal file
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@ -0,0 +1,26 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amd,pensando.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMD Pensando SoC Platforms
maintainers:
- Brad Larson <blarson@amd.com>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Boards with Pensando Elba SoC
items:
- enum:
- amd,pensando-elba-ortano
- const: amd,pensando-elba
additionalProperties: true
...

3
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -155,6 +155,7 @@ properties:
- enum:
- bananapi,bpi-m2s
- khadas,vim3
- libretech,aml-a311d-cc
- radxa,zero2
- const: amlogic,a311d
- const: amlogic,g12b
@ -196,6 +197,7 @@ properties:
- hardkernel,odroid-hc4
- haochuangyi,h96-max
- khadas,vim3l
- libretech,aml-s905d3-cc
- seirobotics,sei610
- const: amlogic,sm1
@ -203,6 +205,7 @@ properties:
items:
- enum:
- amlogic,ad401
- amlogic,ad402
- const: amlogic,a1
- description: Boards with the Amlogic C3 C302X/C308L SoC

1
Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml
View File

@ -79,6 +79,7 @@ properties:
- facebook,elbert-bmc
- facebook,fuji-bmc
- facebook,greatlakes-bmc
- facebook,minerva-cmc
- facebook,yosemite4-bmc
- ibm,everest-bmc
- ibm,rainier-bmc

7
Documentation/devicetree/bindings/arm/atmel-at91.yaml
View File

@ -79,6 +79,13 @@ properties:
- const: atmel,sama5d2
- const: atmel,sama5
- description: Microchip SAMA5D29 Curiosity
items:
- const: microchip,sama5d29-curiosity
- const: atmel,sama5d29
- const: atmel,sama5d2
- const: atmel,sama5
- items:
- const: atmel,sama5d27
- const: atmel,sama5d2

43
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -25,8 +25,11 @@ properties:
- description: i.MX23 based Boards
items:
- enum:
- creative,x-fi3
- fsl,imx23-evk
- fsl,stmp378x-devb
- olimex,imx23-olinuxino
- sandisk,sansa_fuze_plus
- const: fsl,imx23
- description: i.MX25 Product Development Kit
@ -385,6 +388,12 @@ properties:
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- description: i.MX6Q Variscite VAR-SOM-MX6 Boards
items:
- const: variscite,mx6customboard
- const: variscite,var-som-imx6q
- const: fsl,imx6q
- description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x
items:
- const: tq,imx6q-mba6x-a
@ -975,7 +984,9 @@ properties:
- description: PHYTEC phyCORE-i.MX8MM SoM based boards
items:
- const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK
- enum:
- phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK
- phytec,imx8mm-phygate-tauri-l # phyGATE-Tauri-L Gateway
- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM
- const: fsl,imx8mm
@ -1389,6 +1400,13 @@ properties:
- fsl,ls1043a-qds
- const: fsl,ls1043a
- description: TQ-Systems LS1043A based Boards
items:
- enum:
- tq,ls1043a-tqmls1043a-mbls10xxa
- const: tq,ls1043a-tqmls1043a
- const: fsl,ls1043a
- description: LS1046A based Boards
items:
- enum:
@ -1397,6 +1415,13 @@ properties:
- fsl,ls1046a-rdb
- const: fsl,ls1046a
- description: TQ-Systems LS1046A based Boards
items:
- enum:
- tq,ls1046a-tqmls1046a-mbls10xxa
- const: tq,ls1046a-tqmls1046a
- const: fsl,ls1046a
- description: LS1088A based Boards
items:
- enum:
@ -1404,6 +1429,13 @@ properties:
- fsl,ls1088a-rdb
- const: fsl,ls1088a
- description: TQ-Systems LS1088A based Boards
items:
- enum:
- tq,ls1088a-tqmls1088a-mbls10xxa
- const: tq,ls1088a-tqmls1088a
- const: fsl,ls1088a
- description: LS2080A based Boards
items:
- enum:
@ -1429,7 +1461,7 @@ properties:
- fsl,lx2162a-qds
- const: fsl,lx2160a
- description: SolidRun LX2160A based Boards
- description: SolidRun LX2160A CEX-7 based Boards
items:
- enum:
- solidrun,clearfog-cx
@ -1437,6 +1469,13 @@ properties:
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
- description: SolidRun LX2162A SoM based Boards
items:
- enum:
- solidrun,lx2162a-clearfog
- const: solidrun,lx2162a-som
- const: fsl,lx2160a
- description: S32G2 based Boards
items:
- enum:

16
Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
View File

@ -16,12 +16,28 @@ properties:
oneOf:
- items:
- enum:
- adieng,coyote
- arcom,vulcan
- dlink,dsm-g600-a
- freecom,fsg-3
- gateway,7001
- gateworks,gw2348
- goramo,multilink-router
- intel,ixdp425
- intel,ixdpg425
- iom,nas-100d
- linksys,nslu2
- netgear,wg302v1
- netgear,wg302v2
- usr,8200
- welltech,epbx100
- linksys,wrv54g
- gemtek,gtwx5715
- const: intel,ixp42x
- items:
- enum:
- gateworks,gw2358
- intel,kixrp435
- const: intel,ixp43x
additionalProperties: true

16
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@ -133,11 +133,22 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
- description: Google Hayato rev5
items:
- const: google,hayato-rev5-sku2
- const: google,hayato-sku2
- const: google,hayato
- const: mediatek,mt8192
- description: Google Hayato
items:
- const: google,hayato-rev1
- const: google,hayato
- const: mediatek,mt8192
- description: Google Spherion rev4 (Acer Chromebook 514)
items:
- const: google,spherion-rev4
- const: google,spherion
- const: mediatek,mt8192
- description: Google Spherion (Acer Chromebook 514)
items:
- const: google,spherion-rev3
@ -248,6 +259,11 @@ properties:
- enum:
- mediatek,mt8365-evk
- const: mediatek,mt8365
- items:
- enum:
- mediatek,mt8395-evk
- const: mediatek,mt8395
- const: mediatek,mt8195
- items:
- enum:
- mediatek,mt8516-pumpkin

45
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@ -50,6 +50,7 @@ description: |
msm8998
qcs404
qcm2290
qcm6490
qdu1000
qrb2210
qrb4210
@ -79,6 +80,7 @@ description: |
sm6125
sm6350
sm6375
sm7125
sm7225
sm8150
sm8250
@ -189,6 +191,7 @@ properties:
- items:
- enum:
- longcheer,l9100
- samsung,a7
- sony,kanuti-tulip
- square,apq8039-t2
@ -391,6 +394,11 @@ properties:
- const: qcom,qrb2210
- const: qcom,qcm2290
- items:
- enum:
- fairphone,fp5
- const: qcom,qcm6490
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
items:
- enum:
@ -479,6 +487,11 @@ properties:
- const: google,lazor-rev8
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 (rev9)
items:
- const: google,lazor-rev9
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 (newest rev)
items:
- const: google,lazor
@ -500,6 +513,11 @@ properties:
- const: google,lazor-rev8-sku2
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with KB Backlight (rev9)
items:
- const: google,lazor-rev9-sku2
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with KB Backlight (newest rev)
items:
- const: google,lazor-sku2
@ -521,9 +539,16 @@ properties:
- const: google,lazor-rev8-sku0
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with LTE (rev9)
items:
- const: google,lazor-rev9-sku0
- const: google,lazor-rev9-sku10
- const: qcom,sc7180
- description: Acer Chromebook Spin 513 with LTE (newest rev)
items:
- const: google,lazor-sku0
- const: google,lazor-sku10
- const: qcom,sc7180
- description: Acer Chromebook 511 (rev4 - rev8)
@ -535,9 +560,16 @@ properties:
- const: google,lazor-rev8-sku4
- const: qcom,sc7180
- description: Acer Chromebook 511 (rev9)
items:
- const: google,lazor-rev9-sku4
- const: google,lazor-rev9-sku15
- const: qcom,sc7180
- description: Acer Chromebook 511 (newest rev)
items:
- const: google,lazor-sku4
- const: google,lazor-sku15
- const: qcom,sc7180
- description: Acer Chromebook 511 without Touchscreen (rev4)
@ -554,9 +586,16 @@ properties:
- const: google,lazor-rev8-sku6
- const: qcom,sc7180
- description: Acer Chromebook 511 without Touchscreen (rev9)
items:
- const: google,lazor-rev9-sku6
- const: google,lazor-rev9-sku18
- const: qcom,sc7180
- description: Acer Chromebook 511 without Touchscreen (newest rev)
items:
- const: google,lazor-sku6
- const: google,lazor-sku18
- const: qcom,sc7180
- description: Google Mrbland with AUO panel (rev0)
@ -943,6 +982,11 @@ properties:
- sony,pdx225
- const: qcom,sm6375
- items:
- enum:
- xiaomi,joyeuse
- const: qcom,sm7125
- items:
- enum:
- fairphone,fp4
@ -1086,6 +1130,7 @@ allOf:
- qcom,sm6115
- qcom,sm6125
- qcom,sm6350
- qcom,sm7125
- qcom,sm7225
- qcom,sm8150
- qcom,sm8250

25
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -660,6 +660,11 @@ properties:
- pine64,quartz64-b
- const: rockchip,rk3566
- description: Pine64 QuartzPro64
items:
- const: pine64,quartzpro64
- const: rockchip,rk3588
- description: Pine64 SoQuartz SoM
items:
- enum:
@ -669,6 +674,11 @@ properties:
- const: pine64,soquartz
- const: rockchip,rk3566
- description: Powkiddy RGB30
items:
- const: powkiddy,rgb30
- const: rockchip,rk3566
- description: Radxa Compute Module 3(CM3)
items:
- enum:
@ -870,6 +880,16 @@ properties:
- const: tronsmart,orion-r68-meta
- const: rockchip,rk3368
- description: Turing RK1
items:
- const: turing,rk1
- const: rockchip,rk3588
- description: Xunlong Orange Pi 5 Plus
items:
- const: xunlong,orangepi-5-plus
- const: rockchip,rk3588
- description: Xunlong Orange Pi R1 Plus / LTS
items:
- enum:
@ -877,6 +897,11 @@ properties:
- xunlong,orangepi-r1-plus-lts
- const: rockchip,rk3328
- description: Xunlong Orange Pi 5
items:
- const: xunlong,orangepi-5
- const: rockchip,rk3588s
- description: Zkmagic A95X Z2
items:
- const: zkmagic,a95x-z2

23
Documentation/devicetree/bindings/arm/sti.yaml
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sti.yaml#
@ -13,13 +13,20 @@ properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- st,stih415
- st,stih416
- st,stih407
- st,stih410
- st,stih418
oneOf:
- items:
- const: st,stih407-b2120
- const: st,stih407
- items:
- enum:
- st,stih410-b2120
- st,stih410-b2260
- const: st,stih410
- items:
- enum:
- st,stih418-b2199
- st,stih418-b2264
- const: st,stih418
additionalProperties: true

1
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@ -146,6 +146,7 @@ properties:
- lxa,stm32mp157c-mc1 # Linux Automation MC-1
- lxa,stm32mp157c-tac-gen1 # Linux Automation TAC (Generation 1)
- lxa,stm32mp157c-tac-gen2 # Linux Automation TAC (Generation 2)
- oct,stm32mp157c-osd32-red # Octavo OSD32MP1 RED board
- const: oct,stm32mp15xx-osd32
- enum:
- st,stm32mp157

16
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -51,6 +51,11 @@ properties:
- const: allwinner,parrot
- const: allwinner,sun8i-a33
- description: Anbernic RG-Nano
items:
- const: anbernic,rg-nano
- const: allwinner,sun8i-v3s
- description: Amarula A64 Relic
items:
- const: amarula,a64-relic
@ -151,6 +156,17 @@ properties:
- const: roofull,beelink-x2
- const: allwinner,sun8i-h3
- description: BigTreeTech Manta M4/8P
items:
- const: bigtreetech,cb1-manta
- const: bigtreetech,cb1
- const: allwinner,sun50i-h616
- description: BigTreeTech Pi
items:
- const: bigtreetech,pi
- const: allwinner,sun50i-h616
- description: Chuwi V7 CW0825
items:
- const: chuwi,v7-cw0825

393
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View File

@ -1,393 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra Power Management Controller (PMC)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra20-pmc
- nvidia,tegra30-pmc
- nvidia,tegra114-pmc
- nvidia,tegra124-pmc
- nvidia,tegra210-pmc
reg:
maxItems: 1
description:
Offset and length of the register set for the device.
clock-names:
items:
- const: pclk
- const: clk32k_in
description:
Must includes entries pclk and clk32k_in.
pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
input to Tegra.
clocks:
maxItems: 2
description:
Must contain an entry for each entry in clock-names.
See ../clocks/clocks-bindings.txt for details.
'#clock-cells':
const: 1
description:
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
PMC also has blink control which allows 32Khz clock output to
Tegra blink pad.
Consumer of PMC clock should specify the desired clock by having
the clock ID in its "clocks" phandle cell with pmc clock provider.
See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
clock IDs.
'#interrupt-cells':
const: 2
description:
Specifies number of cells needed to encode an interrupt source.
The value must be 2.
interrupt-controller: true
nvidia,invert-interrupt:
$ref: /schemas/types.yaml#/definitions/flag
description: Inverts the PMU interrupt signal.
The PMU is an external Power Management Unit, whose interrupt output
signal is fed into the PMC. This signal is optionally inverted, and
then fed into the ARM GIC. The PMC is not involved in the detection
or handling of this interrupt signal, merely its inversion.
nvidia,core-power-req-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description: Core power request active-high.
nvidia,sys-clock-req-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description: System clock request active-high.
nvidia,combined-power-req:
$ref: /schemas/types.yaml#/definitions/flag
description: combined power request for CPU and Core.
nvidia,cpu-pwr-good-en:
$ref: /schemas/types.yaml#/definitions/flag
description:
CPU power good signal from external PMIC to PMC is enabled.
nvidia,suspend-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
description:
The suspend mode that the platform should use.
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
Mode 2 is for LP2, CPU voltage off
nvidia,cpu-pwr-good-time:
$ref: /schemas/types.yaml#/definitions/uint32
description: CPU power good time in uSec.
nvidia,cpu-pwr-off-time:
$ref: /schemas/types.yaml#/definitions/uint32
description: CPU power off time in uSec.
nvidia,core-pwr-good-time:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
<Oscillator-stable-time Power-stable-time>
Core power good time in uSec.
nvidia,core-pwr-off-time:
$ref: /schemas/types.yaml#/definitions/uint32
description: Core power off time in uSec.
nvidia,lp0-vec:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
<start length> Starting address and length of LP0 vector.
The LP0 vector contains the warm boot code that is executed
by AVP when resuming from the LP0 state.
The AVP (Audio-Video Processor) is an ARM7 processor and
always being the first boot processor when chip is power on
or resume from deep sleep mode. When the system is resumed
from the deep sleep mode, the warm boot code will restore
some PLLs, clocks and then brings up CPU0 for resuming the
system.
core-supply:
description:
Phandle to voltage regulator connected to the SoC Core power rail.
core-domain:
type: object
description: |
The vast majority of hardware blocks of Tegra SoC belong to a
Core power domain, which has a dedicated voltage rail that powers
the blocks.
properties:
operating-points-v2:
description:
Should contain level, voltages and opp-supported-hw property.
The supported-hw is a bitfield indicating SoC speedo or process
ID mask.
"#power-domain-cells":
const: 0
required:
- operating-points-v2
- "#power-domain-cells"
additionalProperties: false
i2c-thermtrip:
type: object
description:
On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
hardware-triggered thermal reset will be enabled.
properties:
nvidia,i2c-controller-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
ID of I2C controller to send poweroff command to PMU.
Valid values are described in section 9.2.148
"APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
Manual.
nvidia,bus-addr:
$ref: /schemas/types.yaml#/definitions/uint32
description: Bus address of the PMU on the I2C bus.
nvidia,reg-addr:
$ref: /schemas/types.yaml#/definitions/uint32
description: PMU I2C register address to issue poweroff command.
nvidia,reg-data:
$ref: /schemas/types.yaml#/definitions/uint32
description: Poweroff command to write to PMU.
nvidia,pinmux-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Pinmux used by the hardware when issuing Poweroff command.
Defaults to 0. Valid values are described in section 12.5.2
"Pinmux Support" of the Tegra4 Technical Reference Manual.
required:
- nvidia,i2c-controller-id
- nvidia,bus-addr
- nvidia,reg-addr
- nvidia,reg-data
additionalProperties: false
powergates:
type: object
description: |
This node contains a hierarchy of power domain nodes, which should
match the powergates on the Tegra SoC. Each powergate node
represents a power-domain on the Tegra SoC that can be power-gated
by the Tegra PMC.
Hardware blocks belonging to a power domain should contain
"power-domains" property that is a phandle pointing to corresponding
powergate node.
The name of the powergate node should be one of the below. Note that
not every powergate is applicable to all Tegra devices and the following
list shows which powergates are applicable to which devices.
Please refer to Tegra TRM for mode details on the powergate nodes to
use for each power-gate block inside Tegra.
Name Description Devices Applicable
3d 3D Graphics Tegra20/114/124/210
3d0 3D Graphics 0 Tegra30
3d1 3D Graphics 1 Tegra30
aud Audio Tegra210
dfd Debug Tegra210
dis Display A Tegra114/124/210
disb Display B Tegra114/124/210
heg 2D Graphics Tegra30/114/124/210
iram Internal RAM Tegra124/210
mpe MPEG Encode All
nvdec NVIDIA Video Decode Engine Tegra210
nvjpg NVIDIA JPEG Engine Tegra210
pcie PCIE Tegra20/30/124/210
sata SATA Tegra30/124/210
sor Display interfaces Tegra124/210
ve2 Video Encode Engine 2 Tegra210
venc Video Encode Engine All
vdec Video Decode Engine Tegra20/30/114/124
vic Video Imaging Compositor Tegra124/210
xusba USB Partition A Tegra114/124/210
xusbb USB Partition B Tegra114/124/210
xusbc USB Partition C Tegra114/124/210
patternProperties:
"^[a-z0-9]+$":
type: object
additionalProperties: false
properties:
clocks:
minItems: 1
maxItems: 8
description:
Must contain an entry for each clock required by the PMC
for controlling a power-gate.
See ../clocks/clock-bindings.txt document for more details.
resets:
minItems: 1
maxItems: 8
description:
Must contain an entry for each reset required by the PMC
for controlling a power-gate.
See ../reset/reset.txt for more details.
power-domains:
maxItems: 1
'#power-domain-cells':
const: 0
description: Must be 0.
required:
- clocks
- resets
- '#power-domain-cells'
additionalProperties: false
patternProperties:
"^[a-f0-9]+-[a-f0-9]+$":
type: object
description:
This is a Pad configuration node. On Tegra SOCs a pad is a set of
pins which are configured as a group. The pin grouping is a fixed
attribute of the hardware. The PMC can be used to set pad power state
and signaling voltage. A pad can be either in active or power down mode.
The support for power state and signaling voltage configuration varies
depending on the pad in question. 3.3V and 1.8V signaling voltages
are supported on pins where software controllable signaling voltage
switching is available.
The pad configuration state nodes are placed under the pmc node and they
are referred to by the pinctrl client properties. For more information
see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The pad name should be used as the value of the pins property in pin
configuration nodes.
The following pads are present on Tegra124 and Tegra132
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
The following pads are present on Tegra210
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
properties:
pins:
$ref: /schemas/types.yaml#/definitions/string
description: Must contain name of the pad(s) to be configured.
low-power-enable:
$ref: /schemas/types.yaml#/definitions/flag
description: Configure the pad into power down mode.
low-power-disable:
$ref: /schemas/types.yaml#/definitions/flag
description: Configure the pad into active mode.
power-source:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
Power state can be configured on all Tegra124 and Tegra132
pads. None of the Tegra124 or Tegra132 pads support signaling
voltage switching.
All of the listed Tegra210 pads except pex-cntrl support power
state configuration. Signaling voltage switching is supported
on below Tegra210 pads.
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
sdmmc3, spi, spi-hv, and uart.
required:
- pins
additionalProperties: false
required:
- compatible
- reg
- clock-names
- clocks
- '#clock-cells'
additionalProperties: false
dependencies:
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/soc/tegra-pmc.h>
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x7000e400 0x400>;
core-supply = <&regulator>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <4587 3876>;
nvidia,core-pwr-off-time = <39065>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
pd_core: core-domain {
operating-points-v2 = <&core_opp_table>;
#power-domain-cells = <0>;
};
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
};

2
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@ -65,6 +65,8 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
- items:

43
Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
items:
- enum:
- sophgo,sg2042-aclint-mswi
- const: thead,c900-aclint-mswi
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 4095
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
interrupt-controller@94000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
interrupts-extended = <&cpu1intc 3>,
<&cpu2intc 3>,
<&cpu3intc 3>,
<&cpu4intc 3>;
reg = <0x94000000 0x00010000>;
};
...

4
Documentation/devicetree/bindings/nvmem/allwinner,sun4i-a10-sid.yaml
View File

@ -23,7 +23,9 @@ properties:
- const: allwinner,sun20i-d1-sid
- const: allwinner,sun50i-a64-sid
- items:
- const: allwinner,sun50i-a100-sid
- enum:
- allwinner,sun50i-a100-sid
- allwinner,sun50i-h616-sid
- const: allwinner,sun50i-a64-sid
- const: allwinner,sun50i-h5-sid
- const: allwinner,sun50i-h6-sid

1
Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
View File

@ -32,6 +32,7 @@ properties:
- rockchip,rk3308-pwm
- rockchip,rk3568-pwm
- rockchip,rk3588-pwm
- rockchip,rv1126-pwm
- const: rockchip,rk3328-pwm
reg:

1
Documentation/devicetree/bindings/riscv/cpus.yaml
View File

@ -47,6 +47,7 @@ properties:
- sifive,u74-mc
- thead,c906
- thead,c910
- thead,c920
- const: riscv
- items:
- enum:

32
Documentation/devicetree/bindings/riscv/sophgo.yaml Normal file
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@ -0,0 +1,32 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SoC-based boards
maintainers:
- Chao Wei <chao.wei@sophgo.com>
- Chen Wang <unicorn_wang@outlook.com>
description:
Sophgo SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- milkv,duo
- const: sophgo,cv1800b
- items:
- enum:
- milkv,pioneer
- const: sophgo,sg2042
additionalProperties: true
...

1
Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
View File

@ -23,6 +23,7 @@ properties:
- renesas,r9a07g043-sysc # RZ/G2UL and RZ/Five
- renesas,r9a07g044-sysc # RZ/G2{L,LC}
- renesas,r9a07g054-sysc # RZ/V2L
- renesas,r9a08g045-sysc # RZ/G3S
reg:
maxItems: 1

28
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
View File

@ -302,7 +302,7 @@ properties:
- description: R-Car E3 (R8A77990)
items:
- enum:
- renesas,ebisu # Ebisu (RTP0RC77990SEB0010S)
- renesas,ebisu # Ebisu (RTP0RC77990SEB0010S), Ebisu-4D (RTP0RC77990SEB0020S)
- const: renesas,r8a77990
- description: R-Car D3 (R8A77995)
@ -335,6 +335,13 @@ properties:
- const: renesas,spider-cpu
- const: renesas,r8a779f0
- description: R-Car S4-8 (R8A779F4)
items:
- enum:
- renesas,s4sk # R-Car S4 Starter Kit board (Y-ASK-RCAR-S4-1000BASE-T#WS12)
- const: renesas,r8a779f4
- const: renesas,r8a779f0
- description: R-Car V4H (R8A779G0)
items:
- enum:
@ -474,6 +481,25 @@ properties:
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- const: renesas,r9a09g011
- description: RZ/G3S (R9A08G045)
items:
- enum:
- renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
- description: RZ/G3S SMARC Module (SoM)
items:
- const: renesas,rzg3s-smarcm # RZ/G3S SMARC Module (SoM)
- const: renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
- description: RZ SMARC Carrier-II Evaluation Kit
items:
- const: renesas,smarc2-evk # RZ SMARC Carrier-II EVK
- const: renesas,rzg3s-smarcm # RZ/G3S SMARC SoM
- const: renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
additionalProperties: true
...

46
Documentation/devicetree/bindings/soc/sti/st,sti-syscon.yaml Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/sti/st,sti-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STi platform sysconfig
maintainers:
- Patrice Chotard <patrice.chotard@foss.st.com>
description: |
Binding for the various sysconfig nodes used within the STi
platform device-tree to point to some common configuration
registers used by other nodes.
properties:
compatible:
items:
- enum:
- st,stih407-core-syscfg
- st,stih407-flash-syscfg
- st,stih407-front-syscfg
- st,stih407-lpm-syscfg
- st,stih407-rear-syscfg
- st,stih407-sbc-reg-syscfg
- st,stih407-sbc-syscfg
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscfg_sbc: syscon@9620000 {
compatible = "st,stih407-sbc-syscfg", "syscon";
reg = <0x9620000 0x1000>;
};
...

416
Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml Normal file
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@ -0,0 +1,416 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra Power Management Controller (PMC)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra20-pmc
- nvidia,tegra30-pmc
- nvidia,tegra114-pmc
- nvidia,tegra124-pmc
- nvidia,tegra210-pmc
reg:
maxItems: 1
clock-names:
items:
# Tegra clock of the same name
- const: pclk
# 32 KHz clock input
- const: clk32k_in
clocks:
maxItems: 2
'#clock-cells':
const: 1
description: |
Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
control which allows 32Khz clock output to Tegra blink pad.
Consumer of PMC clock should specify the desired clock by having the
clock ID in its "clocks" phandle cell with PMC clock provider. See
include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
'#interrupt-cells':
const: 2
description: Specifies number of cells needed to encode an interrupt
source.
interrupt-controller: true
nvidia,invert-interrupt:
$ref: /schemas/types.yaml#/definitions/flag
description: Inverts the PMU interrupt signal. The PMU is an external Power
Management Unit, whose interrupt output signal is fed into the PMC. This
signal is optionally inverted, and then fed into the ARM GIC. The PMC is
not involved in the detection or handling of this interrupt signal,
merely its inversion.
nvidia,core-power-req-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description: core power request active-high
nvidia,sys-clock-req-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description: system clock request active-high
nvidia,combined-power-req:
$ref: /schemas/types.yaml#/definitions/flag
description: combined power request for CPU and core
nvidia,cpu-pwr-good-en:
$ref: /schemas/types.yaml#/definitions/flag
description: CPU power good signal from external PMIC to PMC is enabled
nvidia,suspend-mode:
$ref: /schemas/types.yaml#/definitions/uint32
description: the suspend mode that the platform should use
oneOf:
- description: LP0, CPU + Core voltage off and DRAM in self-refresh
const: 0
- description: LP1, CPU voltage off and DRAM in self-refresh
const: 1
- description: LP2, CPU voltage off
const: 2
nvidia,cpu-pwr-good-time:
$ref: /schemas/types.yaml#/definitions/uint32
description: CPU power good time in microseconds
nvidia,cpu-pwr-off-time:
$ref: /schemas/types.yaml#/definitions/uint32
description: CPU power off time in microseconds
nvidia,core-pwr-good-time:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: core power good time in microseconds
items:
- description: oscillator stable time
- description: power stable time
nvidia,core-pwr-off-time:
$ref: /schemas/types.yaml#/definitions/uint32
description: core power off time in microseconds
nvidia,lp0-vec:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Starting address and length of LP0 vector. The LP0 vector contains the
warm boot code that is executed by AVP when resuming from the LP0 state.
The AVP (Audio-Video Processor) is an ARM7 processor and always being
the first boot processor when chip is power on or resume from deep sleep
mode. When the system is resumed from the deep sleep mode, the warm boot
code will restore some PLLs, clocks and then brings up CPU0 for resuming
the system.
items:
- description: starting address of LP0 vector
- description: length of LP0 vector
core-supply:
description: phandle to voltage regulator connected to the SoC core power
rail
core-domain:
type: object
description: The vast majority of hardware blocks of Tegra SoC belong to a
core power domain, which has a dedicated voltage rail that powers the
blocks.
additionalProperties: false
properties:
operating-points-v2:
description: Should contain level, voltages and opp-supported-hw
property. The supported-hw is a bitfield indicating SoC speedo or
process ID mask.
"#power-domain-cells":
const: 0
required:
- operating-points-v2
- "#power-domain-cells"
i2c-thermtrip:
type: object
description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
exists, hardware-triggered thermal reset will be enabled.
additionalProperties: false
properties:
nvidia,i2c-controller-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: ID of I2C controller to send poweroff command to PMU.
Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0"
of the Tegra K1 Technical Reference Manual.
nvidia,bus-addr:
$ref: /schemas/types.yaml#/definitions/uint32
description: bus address of the PMU on the I2C bus
nvidia,reg-addr:
$ref: /schemas/types.yaml#/definitions/uint32
description: PMU I2C register address to issue poweroff command
nvidia,reg-data:
$ref: /schemas/types.yaml#/definitions/uint32
description: power-off command to write to PMU
nvidia,pinmux-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: Pinmux used by the hardware when issuing power-off command.
Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
Support" of the Tegra4 Technical Reference Manual.
required:
- nvidia,i2c-controller-id
- nvidia,bus-addr
- nvidia,reg-addr
- nvidia,reg-data
powergates:
type: object
additionalProperties: false
description: |
This node contains a hierarchy of power domain nodes, which should match
the powergates on the Tegra SoC. Each powergate node represents a power-
domain on the Tegra SoC that can be power-gated by the Tegra PMC.
Hardware blocks belonging to a power domain should contain "power-domains"
property that is a phandle pointing to corresponding powergate node.
The name of the powergate node should be one of the below. Note that not
every powergate is applicable to all Tegra devices and the following list
shows which powergates are applicable to which devices.
Please refer to Tegra TRM for mode details on the powergate nodes to use
for each power-gate block inside Tegra.
Name Description Devices Applicable
--------------------------------------------------------------
3d 3D Graphics Tegra20/114/124/210
3d0 3D Graphics 0 Tegra30
3d1 3D Graphics 1 Tegra30
aud Audio Tegra210
dfd Debug Tegra210
dis Display A Tegra114/124/210
disb Display B Tegra114/124/210
heg 2D Graphics Tegra30/114/124/210
iram Internal RAM Tegra124/210
mpe MPEG Encode All
nvdec NVIDIA Video Decode Engine Tegra210
nvjpg NVIDIA JPEG Engine Tegra210
pcie PCIE Tegra20/30/124/210
sata SATA Tegra30/124/210
sor Display interfaces Tegra124/210
ve2 Video Encode Engine 2 Tegra210
venc Video Encode Engine All
vdec Video Decode Engine Tegra20/30/114/124
vic Video Imaging Compositor Tegra124/210
xusba USB Partition A Tegra114/124/210
xusbb USB Partition B Tegra114/124/210
xusbc USB Partition C Tegra114/124/210
patternProperties:
"^[a-z0-9]+$":
type: object
additionalProperties: false
properties:
clocks:
minItems: 1
maxItems: 10
resets:
minItems: 1
maxItems: 8
power-domains:
maxItems: 1
'#power-domain-cells':
const: 0
description: Must be 0.
required:
- clocks
- resets
- '#power-domain-cells'
pinmux:
type: object
additionalProperties:
type: object
description: |
This is a pad configuration node. On Tegra SoCs a pad is a set of pins
which are configured as a group. The pin grouping is a fixed attribute
of the hardware. The PMC can be used to set pad power state and
signaling voltage. A pad can be either in active or power down mode.
The support for power state and signaling voltage configuration varies
depending on the pad in question. 3.3V and 1.8V signaling voltages are
supported on pins where software controllable signaling voltage
switching is available.
The pad configuration state nodes are placed under the pmc node and
they are referred to by the pinctrl client properties. For more
information see:
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
The pad name should be used as the value of the pins property in pin
configuration nodes.
The following pads are present on Tegra124 and Tegra132:
audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
usb_bias
The following pads are present on Tegra210:
audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
additionalProperties: false
properties:
pins:
$ref: /schemas/types.yaml#/definitions/string-array
description: Must contain name of the pad(s) to be configured.
low-power-enable:
$ref: /schemas/types.yaml#/definitions/flag
description: Configure the pad into power down mode.
low-power-disable:
$ref: /schemas/types.yaml#/definitions/flag
description: Configure the pad into active mode.
power-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
values are defined in:
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
Power state can be configured on all Tegra124 and Tegra132 pads.
None of the Tegra124 or Tegra132 pads support signaling voltage
switching. All of the listed Tegra210 pads except pex-cntrl support
power state configuration. Signaling voltage switching is supported
on the following Tegra210 pads:
audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
spi, spi-hv, uart
required:
- pins
required:
- compatible
- reg
- clock-names
- clocks
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra124-pmc
then:
properties:
pinmux:
additionalProperties:
type: object
properties:
pins:
items:
enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib,
dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
usb_bias ]
- if:
properties:
compatible:
contains:
const: nvidia,tegra210-pmc
then:
properties:
pinmux:
additionalProperties:
type: object
properties:
pins:
items:
enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
usb-bias ]
additionalProperties: false
dependencies:
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
"nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
examples:
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/soc/tegra-pmc.h>
pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x7000e400 0x400>;
core-supply = <&regulator>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
nvidia,cpu-pwr-good-time = <0>;
nvidia,cpu-pwr-off-time = <0>;
nvidia,core-pwr-good-time = <4587 3876>;
nvidia,core-pwr-off-time = <39065>;
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
pd_core: core-domain {
operating-points-v2 = <&core_opp_table>;
#power-domain-cells = <0>;
};
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
};

1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@ -37,6 +37,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:

43
Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml Normal file
View File

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo CLINT Timer
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
properties:
compatible:
items:
- enum:
- sophgo,sg2042-aclint-mtimer
- const: thead,c900-aclint-mtimer
reg:
maxItems: 1
interrupts-extended:
minItems: 1
maxItems: 4095
additionalProperties: false
required:
- compatible
- reg
- interrupts-extended
examples:
- |
timer@ac000000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
interrupts-extended = <&cpu1intc 7>,
<&cpu2intc 7>,
<&cpu3intc 7>,
<&cpu4intc 7>;
reg = <0xac000000 0x00010000>;
};
...

22
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -59,6 +59,8 @@ patternProperties:
description: AD Holdings Plc.
"^adi,.*":
description: Analog Devices, Inc.
"^adieng,.*":
description: ADI Engineering, Inc.
"^advantech,.*":
description: Advantech Corporation
"^aeroflexgaisler,.*":
@ -127,6 +129,8 @@ patternProperties:
description: Arasan Chip Systems
"^archermind,.*":
description: ArcherMind Technology (Nanjing) Co., Ltd.
"^arcom,.*":
description: Arcom Controllers
"^arctic,.*":
description: Arctic Sand
"^arcx,.*":
@ -194,6 +198,8 @@ patternProperties:
description: Shanghai Belling Co., Ltd.
"^bhf,.*":
description: Beckhoff Automation GmbH & Co. KG
"^bigtreetech,.*":
description: Shenzhen BigTree Tech Co., LTD
"^bitmain,.*":
description: Bitmain Technologies
"^blutek,.*":
@ -484,6 +490,8 @@ patternProperties:
description: FocalTech Systems Co.,Ltd
"^forlinx,.*":
description: Baoding Forlinx Embedded Technology Co., Ltd.
"^freecom,.*":
description: Freecom Gmbh
"^frida,.*":
description: Shenzhen Frida LCD Co., Ltd.
"^friendlyarm,.*":
@ -496,6 +504,8 @@ patternProperties:
description: FX Technology Ltd.
"^gardena,.*":
description: GARDENA GmbH
"^gateway,.*":
description: Gateway Communications
"^gateworks,.*":
description: Gateworks Corporation
"^gcw,.*":
@ -510,6 +520,8 @@ patternProperties:
description: GE Fanuc Intelligent Platforms Embedded Systems, Inc.
"^gemei,.*":
description: Gemei Digital Technology Co., Ltd.
"^gemtek,.*":
description: Gemtek Technology Co., Ltd.
"^genesys,.*":
description: Genesys Logic, Inc.
"^geniatech,.*":
@ -530,6 +542,8 @@ patternProperties:
description: Shenzhen Huiding Technology Co., Ltd.
"^google,.*":
description: Google, Inc.
"^goramo,.*":
description: Goramo Gorecki
"^gplus,.*":
description: GPLUS
"^grinn,.*":
@ -865,6 +879,8 @@ patternProperties:
description: MikroElektronika d.o.o.
"^mikrotik,.*":
description: MikroTik
"^milkv,.*":
description: MilkV Technology Co., Ltd
"^miniand,.*":
description: Miniand Tech
"^minix,.*":
@ -1279,6 +1295,8 @@ patternProperties:
description: Solomon Systech Limited
"^sony,.*":
description: Sony Corporation
"^sophgo,.*":
description: Sophgo Technology Inc.
"^sourceparts,.*":
description: Source Parts Inc.
"^spansion,.*":
@ -1426,6 +1444,8 @@ patternProperties:
description: Truly Semiconductors Limited
"^tsd,.*":
description: Theobroma Systems Design und Consulting GmbH
"^turing,.*":
description: Turing Machines, Inc.
"^tyan,.*":
description: Tyan Computer Corporation
"^u-blox,.*":
@ -1450,6 +1470,8 @@ patternProperties:
description: United Radiant Technology Corporation
"^usi,.*":
description: Universal Scientific Industrial Co., Ltd.
"^usr,.*":
description: U.S. Robotics Corporation
"^utoo,.*":
description: Aigo Digital Technology Co., Ltd.
"^v3,.*":

9
MAINTAINERS
View File

@ -20155,6 +20155,13 @@ F: drivers/char/sonypi.c
F: drivers/platform/x86/sony-laptop.c
F: include/linux/sony-laptop.h
SOPHGO DEVICETREES
M: Chao Wei <chao.wei@sophgo.com>
M: Chen Wang <unicorn_wang@outlook.com>
S: Maintained
F: arch/riscv/boot/dts/sophgo/
F: Documentation/devicetree/bindings/riscv/sophgo.yaml
SOUND
M: Jaroslav Kysela <perex@perex.cz>
M: Takashi Iwai <tiwai@suse.com>
@ -21923,9 +21930,11 @@ W: https://www.tq-group.com/en/products/tq-embedded/
F: arch/arm/boot/dts/imx*mba*.dts*
F: arch/arm/boot/dts/imx*tqma*.dts*
F: arch/arm/boot/dts/mba*.dtsi
F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts*
F: arch/arm64/boot/dts/freescale/imx*mba*.dts*
F: arch/arm64/boot/dts/freescale/imx*tqma*.dts*
F: arch/arm64/boot/dts/freescale/mba*.dtsi
F: arch/arm64/boot/dts/freescale/tqml*.dts*
F: drivers/gpio/gpio-tqmx86.c
F: drivers/mfd/tqmx86.c
F: drivers/watchdog/tqmx86_wdt.c

1
arch/arm/boot/dts/allwinner/Makefile
View File

@ -256,6 +256,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-t113s-mangopi-mq-r-t113.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-anbernic-rg-nano.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
sun8i-v40-bananapi-m2-berry.dtb

2
arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
View File

@ -338,6 +338,8 @@
resets = <&ccu RST_BUS_VE>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
allwinner,sram = <&ve_sram 1>;
interconnects = <&mbus 4>;
interconnect-names = "dma-mem";
};
mmc0: mmc@1c0f000 {

276
arch/arm/boot/dts/allwinner/sun8i-v3s-anbernic-rg-nano.dts Normal file
View File

@ -0,0 +1,276 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "sun8i-v3s.dtsi"
#include "sunxi-common-regulators.dtsi"
/ {
model = "Anbernic RG Nano";
compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s";
aliases {
rtc0 = &pcf8563;
rtc1 = &rtc;
serial0 = &uart0;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>;
default-brightness-level = <11>;
power-supply = <&reg_vcc5v0>;
pwms = <&pwm 0 40000 1>;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
button-a {
gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-A";
linux,code = <BTN_EAST>;
};
button-b {
gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-B";
linux,code = <BTN_SOUTH>;
};
button-down {
gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-DOWN";
linux,code = <BTN_DPAD_DOWN>;
};
button-left {
gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-LEFT";
linux,code = <BTN_DPAD_LEFT>;
};
button-right {
gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-RIGHT";
linux,code = <BTN_DPAD_RIGHT>;
};
button-se {
gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-SELECT";
linux,code = <BTN_SELECT>;
};
button-st {
gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-START";
linux,code = <BTN_START>;
};
button-tl {
gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-L";
linux,code = <BTN_TL>;
};
button-tr {
gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-R";
linux,code = <BTN_TR>;
};
button-up {
gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "DPAD-UP";
linux,code = <BTN_DPAD_UP>;
};
button-x {
gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-X";
linux,code = <BTN_NORTH>;
};
button-y {
gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
label = "BTN-Y";
linux,code = <BTN_WEST>;
};
};
};
&codec {
allwinner,audio-routing = "Speaker", "HP",
"MIC1", "Mic",
"Mic", "HBIAS";
allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */
status = "okay";
};
&ehci {
status = "okay";
};
&i2c0 {
status = "okay";
gpio_expander: gpio@20 {
compatible = "nxp,pcal6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&pio>;
interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */
vcc-supply = <&reg_vcc3v3>;
};
axp209: pmic@34 {
reg = <0x34>;
interrupt-parent = <&pio>;
interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */
};
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
#include "axp209.dtsi"
&battery_power_supply {
status = "okay";
};
&mmc0 {
broken-cd;
bus-width = <4>;
disable-wp;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
status = "okay";
};
&ohci {
status = "okay";
};
&pio {
vcc-pb-supply = <&reg_vcc3v3>;
vcc-pc-supply = <&reg_vcc3v3>;
vcc-pf-supply = <&reg_vcc3v3>;
vcc-pg-supply = <&reg_vcc3v3>;
spi0_no_miso_pins: spi0-no-miso-pins {
pins = "PC1", "PC2", "PC3";
function = "spi0";
};
};
&pwm {
pinctrl-0 = <&pwm0_pin>;
pinctrl-names = "default";
status = "okay";
};
/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */
&reg_dcdc2 {
regulator-always-on;
regulator-max-microvolt = <1250000>;
regulator-min-microvolt = <1250000>;
regulator-name = "vdd-cpu";
};
/* DCDC3 wired into every 3.3v input that isn't the RTC. */
&reg_dcdc3 {
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "vcc-io";
};
/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */
&reg_ldo1 {
regulator-always-on;
regulator-name = "vcc-rtc";
};
/* LDO2 wired into VCC-PLL and audio codec. */
&reg_ldo2 {
regulator-always-on;
regulator-max-microvolt = <3000000>;
regulator-min-microvolt = <3000000>;
regulator-name = "vcc-pll";
};
/* LDO3, LDO4, and LDO5 unused. */
&reg_ldo3 {
status = "disabled";
};
&reg_ldo4 {
status = "disabled";
};
/* RTC uses internal oscillator */
&rtc {
/delete-property/ clocks;
};
&spi0 {
pinctrl-0 = <&spi0_no_miso_pins>;
pinctrl-names = "default";
status = "okay";
display@0 {
compatible = "saef,sftc154b", "panel-mipi-dbi-spi";
reg = <0>;
backlight = <&backlight>;
dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */
reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
spi-max-frequency = <100000000>;
height-mm = <39>;
width-mm = <39>;
/* Set hb-porch to compensate for non-visible area */
panel-timing {
hactive = <240>;
vactive = <240>;
hback-porch = <80>;
vback-porch = <0>;
clock-frequency = <0>;
hfront-porch = <0>;
hsync-len = <0>;
vfront-porch = <0>;
vsync-len = <0>;
};
};
};
&uart0 {
pinctrl-0 = <&uart0_pb_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usb_power_supply {
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */
status = "okay";
};

35
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
View File

@ -319,6 +319,29 @@
#phy-cells = <1>;
};
ehci: usb@1c1a000 {
compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
reg = <0x01c1a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ohci: usb@1c1a400 {
compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
reg = <0x01c1a400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
<&ccu CLK_USB_OHCI0>;
resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
phys = <&usbphy 0>;
phy-names = "usb";
status = "disabled";
};
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
@ -414,6 +437,18 @@
bias-pull-up;
};
/omit-if-no-ref/
pwm0_pin: pwm0-pin {
pins = "PB4";
function = "pwm0";
};
/omit-if-no-ref/
pwm1_pin: pwm1-pin {
pins = "PB5";
function = "pwm1";
};
spi0_pins: spi0-pins {
pins = "PC0", "PC1", "PC2", "PC3";
function = "spi0";

1
arch/arm/boot/dts/aspeed/Makefile
View File

@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-fuji.dtb \
aspeed-bmc-facebook-galaxy100.dtb \
aspeed-bmc-facebook-greatlakes.dtb \
aspeed-bmc-facebook-minerva-cmc.dtb \
aspeed-bmc-facebook-minipack.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-facebook-wedge40.dtb \

66
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjade.dts
View File

@ -760,49 +760,63 @@
&gpio {
gpio-line-names =
/*A0-A7*/ "","","","S0_BMC_SPECIAL_BOOT","","","","",
/*B0-B7*/ "BMC_SELECT_EEPROM","","","",
"POWER_BUTTON","","","",
/*A0-A7*/ "","","","host0-special-boot","","","","",
/*B0-B7*/ "i2c-backup-sel","","","",
"power-button","presence-cpu0","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD",
"S1_DDR_SAVE","","",
/*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","",
"","",
/*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","",
/*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT",
"","","","","",
/*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
"","","","",
/*F0-F7*/ "ps0-pgood","ps1-pgood","power-chassis-control","s0-ddr-save",
"power-chassis-good", "s1-ddr-save","","",
/*G0-G7*/ "host0-ready","host0-shd-req-n","host0-shd-ack-n",
"s0-overtemp-n","","","","",
/*H0-H7*/ "uart1-mode1","uart2-mode1","uart3-mode1","uart4-mode1",
"ps0-vin-good","ps1-vin-good","","i2c6-reset-n",
/*I0-I7*/ "presence-ps0","presence-ps1","s1-special-boot","","","","","",
/*J0-J7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
"host0-reboot-ack-n","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","BMC_SYSRESET_L","SPI_AUTH_FAIL_L","","","",
/*M0-M7*/ "","","","","","","","",
/*L0-L7*/ "","","","host0-sysreset-n","s0-spi-auth-fail-n","","","",
/*M0-M7*/ "","","","","s0-i2c9-alert-n","s1-i2c9-alert-n","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
/*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
"OCP_MAIN_PWREN","RESET_BUTTON","","",
/*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","",
/*Q0-Q7*/ "","","","","","identify-button","led-identify","",
/*R0-R7*/ "","","ext-hightemp-n","","ocp-main-pwren","reset-button","","",
/*S0-S7*/ "s0-vr-hot-n","s1-vr-hot-n","","",
"rtc-battery-voltage-read-enable","vr-pmbus-sel-n","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "S0_BMC_PLIMIT","S1_FAULT_L","S1_FW_BOOT_OK","","",
"S1_SCP_AUTH_FAIL_L","S1_OVERTEMP_L","",
/*Y0-Y7*/ "","","","bmc-vga-en-n","","","","",
/*Z0-Z7*/ "s0-plimit","s1-fault-alert","s1-fw-boot-ok","s0-rtc-lock","",
"s1-sys-auth-failure-n","s1-overtemp-n","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "S1_HIGHTEMP_L","S1_BMC_PLIMIT","S0_BMC_DDR_ADDR",
"S1_BMC_DDR_ADR","","","","",
/*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
"BMC_OCP_PG";
/*AB0-AB7*/ "s1-hightemp-n","s1-plimit","s0-ddr-addr","s1-ddr-addr","","",
"","",
/*AC0-AC7*/ "sys-pwr-gd","","spi0-program-sel","spi0-backup-sel","bmc-ok",
"","presence-cpu1","ocp-pgood";
i2c4-o-en-hog {
gpio-hog;
gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_I2C4_O_EN";
line-name = "i2c4-o-en";
};
ocp-aux-pwren-hog {
gpio-hog;
gpios = <ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "ocp-aux-pwren";
};
bmc-ready {
gpio-hog;
gpios = <ASPEED_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "bmc-ready";
};
};

302
arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts
View File

@ -14,6 +14,42 @@
aliases {
serial7 = &uart8;
serial8 = &uart9;
/*
* I2C NVMe alias port
*/
i2c100 = &backplane_0;
i2c48 = &nvmeslot_0;
i2c49 = &nvmeslot_1;
i2c50 = &nvmeslot_2;
i2c51 = &nvmeslot_3;
i2c52 = &nvmeslot_4;
i2c53 = &nvmeslot_5;
i2c54 = &nvmeslot_6;
i2c55 = &nvmeslot_7;
i2c101 = &backplane_1;
i2c56 = &nvmeslot_8;
i2c57 = &nvmeslot_9;
i2c58 = &nvmeslot_10;
i2c59 = &nvmeslot_11;
i2c60 = &nvmeslot_12;
i2c61 = &nvmeslot_13;
i2c62 = &nvmeslot_14;
i2c63 = &nvmeslot_15;
i2c102 = &backplane_2;
i2c64 = &nvmeslot_16;
i2c65 = &nvmeslot_17;
i2c66 = &nvmeslot_18;
i2c67 = &nvmeslot_19;
i2c68 = &nvmeslot_20;
i2c69 = &nvmeslot_21;
i2c70 = &nvmeslot_22;
i2c71 = &nvmeslot_23;
i2c80 = &nvme_m2_0;
i2c81 = &nvme_m2_1;
};
chosen {
@ -497,6 +533,11 @@
&i2c8 {
status = "okay";
temperature-sensor@48 {
compatible = "ti,tmp112";
reg = <0x48>;
};
gpio@77 {
compatible = "nxp,pca9539";
reg = <0x77>;
@ -516,6 +557,237 @@
&i2c9 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
backplane_1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
nvmeslot_8: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvmeslot_9: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
nvmeslot_10: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
nvmeslot_11: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
nvmeslot_12: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_13: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
nvmeslot_14: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
nvmeslot_15: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
tmp432@4c {
compatible = "ti,tmp75";
reg = <0x4c>;
};
};
backplane_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
nvmeslot_16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvmeslot_17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
nvmeslot_18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
nvmeslot_19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
nvmeslot_20: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_21: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
nvmeslot_22: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
nvmeslot_23: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
tmp432@4c {
compatible = "ti,tmp75";
reg = <0x4c>;
};
};
backplane_0: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
nvmeslot_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvmeslot_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
nvmeslot_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
nvmeslot_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
nvmeslot_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
nvmeslot_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
nvmeslot_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
tmp432@4c {
compatible = "ti,tmp75";
reg = <0x4c>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
i2c-mux@71 {
compatible = "nxp,pca9546";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
nvme_m2_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvme_m2_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
};
};
};
};
&i2c11 {
@ -546,20 +818,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
ref_voltage = <2500>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
&pinctrl_adc10_default &pinctrl_adc11_default
&pinctrl_adc12_default &pinctrl_adc13_default
&pinctrl_adc14_default &pinctrl_adc15_default>;
&pinctrl_adc2_default>;
};
&vhub {
@ -575,16 +834,17 @@
gpio-line-names =
/*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n",
/*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","",
/*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","",
/*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","bmc-debug-mode","",
"irq-n","","vrd-sel","spd-sel",
/*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
"","bmc-ncsi-txen","","",
/*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","",
/*E0-E7*/ "","eth-phy-int-n","clk50m-bmc-ncsi","","","","","",
/*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control",
"cpu-bios-recover","s0-heartbeat","hs-csout-prochot",
"s0-vr-hot-n","s1-vr-hot-n",
/*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","",
/*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","",
/*H0-H7*/ "jtag-program-sel","fpga-program-b","wd-disable-n",
"power-chassis-good","","","","",
/*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
@ -599,17 +859,17 @@
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","identify-button","led-identify",
"s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1",
"s1-ddr-save","spi-nor-access","host0-ready","presence-cpu1",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
"host0-reboot-ack-n","host0-ready","host0-shd-req-n",
"host0-reboot-ack-n","s0-fw-boot-ok","host0-shd-req-n",
"host0-shd-ack-n","s0-overtemp-n",
/*W0-W7*/ "","ocp-main-pwren","ocp-pgood","",
/*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","s1-pcp-pgood",
"bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
/*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok",
"s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n",
"s1-overtemp-n","s1-spi-auth-fail-n",
"s1-overtemp-n","cpld-s1-spi-auth-fail-n",
/*Y0-Y7*/ "","","","","","","","host0-special-boot",
/*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","","";

265
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva-cmc.dts Normal file
View File

@ -0,0 +1,265 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2023 Facebook Inc.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/i2c/i2c.h>
/ {
model = "Facebook Minerva CMC";
compatible = "facebook,minerva-cmc", "aspeed,ast2600";
aliases {
serial5 = &uart5;
};
chosen {
stdout-path = "serial5:57600n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 2>;
};
};
&uart6 {
status = "okay";
};
&wdt1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdtrst1_default>;
aspeed,reset-type = "soc";
aspeed,external-signal;
aspeed,ext-push-pull;
aspeed,ext-active-high;
aspeed,ext-pulse-duration = <256>;
};
&mac3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii4_default>;
use-ncsi;
mlx,multi-host;
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-128.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt-bmc";
spi-max-frequency = <50000000>;
};
};
&rtc {
status = "okay";
};
&sgpiom1 {
status = "okay";
ngpios = <128>;
bus-frequency = <2000000>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
temperature-sensor@4b {
compatible = "ti,tmp75";
reg = <0x4B>;
};
eeprom@51 {
compatible = "atmel,24c128";
reg = <0x51>;
};
};
&i2c2 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9548";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&i2c14 {
status = "okay";
multi-master;
ipmb@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c15 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
};
};
&adc0 {
aspeed,int-vref-microvolt = <2500000>;
status = "okay";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
aspeed,int-vref-microvolt = <2500000>;
status = "okay";
pinctrl-0 = <&pinctrl_adc10_default>;
};
&ehci1 {
status = "okay";
};
&uhci {
status = "okay";
};

8
arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts
View File

@ -34,6 +34,11 @@
#size-cells = <1>;
ranges;
event_log: tcg_event_log@b3d00000 {
no-map;
reg = <0xb3d00000 0x100000>;
};
ramoops@b3e00000 {
compatible = "ramoops";
reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
@ -454,8 +459,9 @@
status = "okay";
tpm@2e {
compatible = "nuvoton,npct75x";
compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c";
reg = <0x2e>;
memory-region = <&event_log>;
};
eeprom@50 {

34
arch/arm/boot/dts/broadcom/bcm-ns.dtsi
View File

@ -14,6 +14,13 @@
#address-cells = <1>;
#size-cells = <1>;
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts =
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
chipcommon-a-bus@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x00001000>;
@ -320,6 +327,29 @@
#address-cells = <1>;
};
mdio-mux@18003000 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x18003000 0x4>;
mux-mask = <0x200>;
mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
usb3_phy: usb3-phy@10 {
compatible = "brcm,ns-ax-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
status = "disabled";
};
};
};
rng: rng@18004000 {
compatible = "brcm,bcm5301x-rng";
reg = <0x18004000 0x14>;
@ -460,6 +490,10 @@
brcm,nand-has-wp;
};
usb3_dmp: syscon@18105000 {
reg = <0x18105000 0x1000>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;

8
arch/arm/boot/dts/broadcom/bcm4708-buffalo-wzr-1166dhp-common.dtsi
View File

@ -181,5 +181,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm4708-luxul-xap-1510.dts
View File

@ -85,5 +85,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm4708-luxul-xwc-1000.dts
View File

@ -88,5 +88,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm4708-netgear-r6250.dts
View File

@ -122,5 +122,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm4708-smartrg-sr400ac.dts
View File

@ -145,6 +145,14 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47081-buffalo-wzr-600dhp2.dts
View File

@ -145,5 +145,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47081-luxul-xap-1410.dts
View File

@ -81,5 +81,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47081-luxul-xwr-1200.dts
View File

@ -148,5 +148,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

11
arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac87u.dts
View File

@ -25,6 +25,12 @@
<0x88000000 0x08000000>;
};
nvram@1c080000 {
et1macaddr: et1macaddr {
#nvmem-cell-cells = <1>;
};
};
leds {
compatible = "gpio-leds";
@ -62,6 +68,11 @@
};
};
&gmac0 {
nvmem-cells = <&et1macaddr 0>;
nvmem-cell-names = "mac-address";
};
&usb3_phy {
status = "okay";
};

38
arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts
View File

@ -47,3 +47,41 @@
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
label = "lan1";
};
port@1 {
label = "lan2";
};
port@2 {
label = "lan3";
};
port@3 {
label = "lan4";
};
port@4 {
label = "wan";
};
port@5 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {
label = "cpu";
};
};
};

18
arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts
View File

@ -227,6 +227,24 @@
label = "wan";
};
port@5 {
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@7 {
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@8 {
label = "cpu";
};

24
arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts
View File

@ -25,6 +25,15 @@
<0x88000000 0x08000000>;
};
nvram@1e3f0000 {
compatible = "brcm,nvram";
reg = <0x1e3f0000 0x10000>;
et2macaddr: et2macaddr {
#nvmem-cell-cells = <1>;
};
};
nand_controller: nand-controller@18028000 {
nand@0 {
partitions {
@ -112,6 +121,11 @@
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};
&gmac0 {
nvmem-cells = <&et2macaddr 0>;
nvmem-cell-names = "mac-address";
};
&spi_nor {
status = "okay";
};
@ -142,6 +156,16 @@
port@4 {
label = "wan";
nvmem-cells = <&et2macaddr 3>;
nvmem-cell-names = "mac-address";
};
port@5 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {

8
arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts
View File

@ -192,6 +192,14 @@
label = "wan";
};
port@5 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {
label = "cpu";
phy-mode = "rgmii";

8
arch/arm/boot/dts/broadcom/bcm47094-luxul-abr-4500.dts
View File

@ -107,5 +107,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts
View File

@ -120,5 +120,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47094-luxul-xbr-4500.dts
View File

@ -107,5 +107,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47094-luxul-xwc-2000.dts
View File

@ -75,5 +75,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3100.dts
View File

@ -147,5 +147,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts
View File

@ -158,5 +158,13 @@
port@5 {
label = "cpu";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts
View File

@ -124,6 +124,14 @@
full-duplex;
};
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

8
arch/arm/boot/dts/broadcom/bcm53016-meraki-mr32.dts
View File

@ -185,6 +185,14 @@
full-duplex;
};
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

34
arch/arm/boot/dts/broadcom/bcm5301x.dtsi
View File

@ -26,13 +26,6 @@
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts =
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
@ -69,33 +62,6 @@
};
};
mdio-mux@18003000 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x18003000 0x4>;
mux-mask = <0x200>;
mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
usb3_phy: usb3-phy@10 {
compatible = "brcm,ns-ax-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
status = "disabled";
};
};
};
usb3_dmp: syscon@18105000 {
reg = <0x18105000 0x1000>;
};
i2c0: i2c@18009000 {
compatible = "brcm,iproc-i2c";
reg = <0x18009000 0x50>;

8
arch/arm/boot/dts/broadcom/bcm953012er.dts
View File

@ -84,6 +84,14 @@
label = "cpu";
ethernet = <&gmac0>;
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
};
};

3
arch/arm/boot/dts/intel/ixp/Makefile
View File

@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp43x-gateworks-gw2358.dtb \
intel-ixp42x-netgear-wg302v1.dtb \
intel-ixp42x-arcom-vulcan.dtb \
intel-ixp42x-gateway-7001.dtb
intel-ixp42x-gateway-7001.dtb \
intel-ixp42x-usrobotics-usr8200.dtb

2
arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
View File

@ -57,7 +57,7 @@
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
};

2
arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
View File

@ -44,7 +44,7 @@
};
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};

2
arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
View File

@ -63,7 +63,7 @@
};
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
};

4
arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
View File

@ -65,7 +65,7 @@
};
button-reset {
wakeup-source;
linux,code = <KEY_ESC>;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
@ -101,6 +101,8 @@
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/*
* 8 MB of Flash in 0x20000 byte blocks
* mapped in at CS0.

2
arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-wrv54g.dts
View File

@ -13,7 +13,7 @@
/ {
model = "Linksys WRV54G / Gemtek GTWX5715";
compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x";
compatible = "linksys,wrv54g", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;

229
arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts Normal file
View File

@ -0,0 +1,229 @@
// SPDX-License-Identifier: ISC
/*
* Device Tree file for the USRobotics USR8200 firewall
* VPN and NAS. Based on know-how from Peter Denison.
*
* This machine is based on IXP422, the USR internal codename
* is "Jeeves".
*/
/dts-v1/;
#include "intel-ixp42x.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "USRobotics USR8200";
compatible = "usr,usr8200", "intel,ixp42x";
#address-cells = <1>;
#size-cells = <1>;
memory@0 {
device_type = "memory";
reg = <0x00000000 0x4000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8";
stdout-path = "uart1:115200n8";
};
aliases {
/* These are switched around */
serial0 = &uart1;
serial1 = &uart0;
};
leds {
compatible = "gpio-leds";
ieee1394_led: led-1394 {
label = "usr8200:green:1394";
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
default-state = "off";
};
usb1_led: led-usb1 {
label = "usr8200:green:usb1";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
usb2_led: led-usb2 {
label = "usr8200:green:usb2";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
wireless_led: led-wireless {
/*
* This LED is mounted inside the case but cannot be
* seen from the outside: probably USR planned at one
* point for the device to have a wireless card, then
* changed their mind and didn't mount it, leaving the
* LED in place.
*/
label = "usr8200:green:wireless";
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
pwr_led: led-pwr {
label = "usr8200:green:pwr";
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
button-reset {
wakeup-source;
linux,code = <KEY_RESTART>;
label = "reset";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
};
soc {
bus@c4000000 {
flash@0,0 {
compatible = "intel,ixp4xx-flash", "cfi-flash";
bank-width = <2>;
/* Enable writes on the expansion bus */
intel,ixp4xx-eb-write-enable = <1>;
/* 16 MB of Flash mapped in at CS0 */
reg = <0 0x00000000 0x1000000>;
partitions {
compatible = "redboot-fis";
/* Eraseblock at 0x0fe0000 */
fis-index-block = <0x7f>;
};
};
rtc@2,0 {
/* EPSON RTC7301 DG DIL-capsule */
compatible = "epson,rtc7301dg";
/*
* These timing settings were found in the boardfile patch:
* IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
* IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
*/
intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
intel,ixp4xx-eb-byte-access-on-halfword = <0>;
intel,ixp4xx-eb-mux-address-and-data = <0>;
intel,ixp4xx-eb-ahb-split-transfers = <0>;
intel,ixp4xx-eb-write-enable = <1>;
intel,ixp4xx-eb-byte-access = <1>;
/* 512 bytes at CS2 */
reg = <2 0x00000000 0x0000200>;
reg-io-width = <1>;
native-endian;
/* FIXME: try to check if there is an IRQ for the RTC? */
};
};
pci@c0000000 {
status = "okay";
/*
* Taken from USR8200 boardfile from OpenWrt
*
* We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
* We assume the same IRQ for all pins on the remaining slots, that
* is what the boardfile was doing.
*/
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map =
/* IDSEL 14 used for "Wireless" in the board file */
<0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
/* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
<0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
/* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
<0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
<0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
<0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
};
gpio@c8004000 {
/* Enable clock out on GPIO 15 */
intel,ixp4xx-gpio15-clkout;
};
/* EthB WAN */
ethernet@c8009000 {
status = "okay";
queue-rx = <&qmgr 3>;
queue-txready = <&qmgr 20>;
phy-mode = "rgmii";
phy-handle = <&phy9>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy9: ethernet-phy@9 {
reg = <9>;
};
/* The switch uses MDIO addresses 16 thru 31 */
switch@16 {
compatible = "marvell,mv88e6060";
reg = <16>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@5 {
/* Port 5 is the CPU port according to the MV88E6060 datasheet */
reg = <5>;
phy-mode = "rgmii-id";
ethernet = <&ethc>;
label = "cpu";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
};
/* EthC LAN connected to the Marvell DSA Switch */
ethc: ethernet@c800a000 {
status = "okay";
queue-rx = <&qmgr 4>;
queue-txready = <&qmgr 21>;
phy-mode = "rgmii";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};

2
arch/arm/boot/dts/mediatek/mt2701-evb.dts
View File

@ -244,7 +244,7 @@
&usb2 {
status = "okay";
usb-role-switch;
connector{
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
type = "micro";
id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>;

58
arch/arm/boot/dts/mediatek/mt6323.dtsi
View File

@ -21,10 +21,10 @@
status = "disabled";
};
mt6323regulator: mt6323regulator{
mt6323regulator: mt6323regulator {
compatible = "mediatek,mt6323-regulator";
mt6323_vproc_reg: buck_vproc{
mt6323_vproc_reg: buck_vproc {
regulator-name = "vproc";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -33,7 +33,7 @@
regulator-boot-on;
};
mt6323_vsys_reg: buck_vsys{
mt6323_vsys_reg: buck_vsys {
regulator-name = "vsys";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <2987500>;
@ -42,13 +42,13 @@
regulator-boot-on;
};
mt6323_vpa_reg: buck_vpa{
mt6323_vpa_reg: buck_vpa {
regulator-name = "vpa";
regulator-min-microvolt = < 500000>;
regulator-max-microvolt = <3650000>;
};
mt6323_vtcxo_reg: ldo_vtcxo{
mt6323_vtcxo_reg: ldo_vtcxo {
regulator-name = "vtcxo";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -57,28 +57,28 @@
regulator-boot-on;
};
mt6323_vcn28_reg: ldo_vcn28{
mt6323_vcn28_reg: ldo_vcn28 {
regulator-name = "vcn28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <185>;
};
mt6323_vcn33_bt_reg: ldo_vcn33_bt{
mt6323_vcn33_bt_reg: ldo_vcn33_bt {
regulator-name = "vcn33_bt";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3600000>;
regulator-enable-ramp-delay = <185>;
};
mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
mt6323_vcn33_wifi_reg: ldo_vcn33_wifi {
regulator-name = "vcn33_wifi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3600000>;
regulator-enable-ramp-delay = <185>;
};
mt6323_va_reg: ldo_va{
mt6323_va_reg: ldo_va {
regulator-name = "va";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -87,14 +87,14 @@
regulator-boot-on;
};
mt6323_vcama_reg: ldo_vcama{
mt6323_vcama_reg: ldo_vcama {
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vio28_reg: ldo_vio28{
mt6323_vio28_reg: ldo_vio28 {
regulator-name = "vio28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -103,7 +103,7 @@
regulator-boot-on;
};
mt6323_vusb_reg: ldo_vusb{
mt6323_vusb_reg: ldo_vusb {
regulator-name = "vusb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -111,7 +111,7 @@
regulator-boot-on;
};
mt6323_vmc_reg: ldo_vmc{
mt6323_vmc_reg: ldo_vmc {
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@ -119,7 +119,7 @@
regulator-boot-on;
};
mt6323_vmch_reg: ldo_vmch{
mt6323_vmch_reg: ldo_vmch {
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -127,7 +127,7 @@
regulator-boot-on;
};
mt6323_vemc3v3_reg: ldo_vemc3v3{
mt6323_vemc3v3_reg: ldo_vemc3v3 {
regulator-name = "vemc3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -135,49 +135,49 @@
regulator-boot-on;
};
mt6323_vgp1_reg: ldo_vgp1{
mt6323_vgp1_reg: ldo_vgp1 {
regulator-name = "vgp1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vgp2_reg: ldo_vgp2{
mt6323_vgp2_reg: ldo_vgp2 {
regulator-name = "vgp2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vgp3_reg: ldo_vgp3{
mt6323_vgp3_reg: ldo_vgp3 {
regulator-name = "vgp3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vcn18_reg: ldo_vcn18{
mt6323_vcn18_reg: ldo_vcn18 {
regulator-name = "vcn18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vsim1_reg: ldo_vsim1{
mt6323_vsim1_reg: ldo_vsim1 {
regulator-name = "vsim1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vsim2_reg: ldo_vsim2{
mt6323_vsim2_reg: ldo_vsim2 {
regulator-name = "vsim2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vrtc_reg: ldo_vrtc{
mt6323_vrtc_reg: ldo_vrtc {
regulator-name = "vrtc";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
@ -185,28 +185,28 @@
regulator-boot-on;
};
mt6323_vcamaf_reg: ldo_vcamaf{
mt6323_vcamaf_reg: ldo_vcamaf {
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vibr_reg: ldo_vibr{
mt6323_vibr_reg: ldo_vibr {
regulator-name = "vibr";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
regulator-enable-ramp-delay = <36>;
};
mt6323_vrf18_reg: ldo_vrf18{
mt6323_vrf18_reg: ldo_vrf18 {
regulator-name = "vrf18";
regulator-min-microvolt = <1825000>;
regulator-max-microvolt = <1825000>;
regulator-enable-ramp-delay = <187>;
};
mt6323_vm_reg: ldo_vm{
mt6323_vm_reg: ldo_vm {
regulator-name = "vm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
@ -215,7 +215,7 @@
regulator-boot-on;
};
mt6323_vio18_reg: ldo_vio18{
mt6323_vio18_reg: ldo_vio18 {
regulator-name = "vio18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -224,14 +224,14 @@
regulator-boot-on;
};
mt6323_vcamd_reg: ldo_vcamd{
mt6323_vcamd_reg: ldo_vcamd {
regulator-name = "vcamd";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-enable-ramp-delay = <216>;
};
mt6323_vcamio_reg: ldo_vcamio{
mt6323_vcamio_reg: ldo_vcamio {
regulator-name = "vcamio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;

4
arch/arm/boot/dts/mediatek/mt7623n.dtsi
View File

@ -116,8 +116,8 @@
"mediatek,mt2701-jpgdec";
reg = <0 0x15004000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;

2
arch/arm/boot/dts/mediatek/mt7629-rfb.dts
View File

@ -168,7 +168,7 @@
i2c_pins: i2c-pins {
mux {
function = "i2c";
groups = "i2c_0";
groups = "i2c_0";
};
conf {

2
arch/arm/boot/dts/microchip/Makefile
View File

@ -4,6 +4,7 @@ DTC_FLAGS_at91-sam9x60_curiosity := -@
DTC_FLAGS_at91-sam9x60ek := -@
DTC_FLAGS_at91-sama5d27_som1_ek := -@
DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
DTC_FLAGS_at91-sama5d29_curiosity := -@
DTC_FLAGS_at91-sama5d2_icp := -@
DTC_FLAGS_at91-sama5d2_ptc_ek := -@
DTC_FLAGS_at91-sama5d2_xplained := -@
@ -64,6 +65,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
at91-sama5d27_wlsom1_ek.dtb \
at91-sama5d29_curiosity.dtb \
at91-sama5d2_icp.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \

4
arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts
View File

@ -439,6 +439,10 @@
status = "okay";
};
&rtt {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
};
&sdmmc0 {
bus-width = <4>;
pinctrl-names = "default";

600
arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts Normal file
View File

@ -0,0 +1,600 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d29_curiosity.dts - Device Tree file for SAMA5D29 Curiosity board
*
* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
*
* Author: Mihai Sain <mihai.sain@microchip.com>
*
*/
/dts-v1/;
#include "sama5d29.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
/ {
model = "Microchip SAMA5D29 Curiosity";
compatible = "microchip,sama5d29-curiosity", "atmel,sama5d29", "atmel,sama5d2", "atmel,sama5";
aliases {
serial0 = &uart0; // debug
serial1 = &uart1; // RPi
serial2 = &uart3; // mikro BUS 2
serial3 = &uart4; // mikro BUS 1
serial4 = &uart6; // flx1 Bluetooth
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
stdout-path = "serial0:115200n8";
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
button-1 {
label = "USER BUTTON";
gpios = <&pioA PIN_PA17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
led-red {
label = "red";
gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
};
led-green {
label = "green";
gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
};
led-blue {
label = "blue";
gpios = <&pioA PIN_PA9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x20000000>;
};
};
&adc {
vddana-supply = <&vdd_3v3>;
vref-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
status = "okay";
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_default>;
status = "okay";
};
&flx1 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart6: serial@200 {
pinctrl-0 = <&pinctrl_flx1_default>;
pinctrl-names = "default";
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
};
&flx4 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "okay";
spi6: spi@400 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rpi_spi>;
status = "okay";
};
};
&i2c0 {
dmas = <0>, <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PB31 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PC0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-sda-hold-time-ns = <350>;
status = "okay";
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
status = "okay";
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddio_ddr: VDD_DDR {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
};
vdd_core: VDD_CORE {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vdd_ddr: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
};
LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&pioA {
pinctrl_adc_default: adc-default {
pinmux = <PIN_PD25__GPIO>,
<PIN_PD26__GPIO>;
bias-disable;
};
pinctrl_adtrg_default: adtrg-default {
pinmux = <PIN_PD31__ADTRG>;
bias-pull-up;
};
pinctrl_can0_default: can0-default {
pinmux = <PIN_PC10__CANTX0>,
<PIN_PC11__CANRX0>;
bias-disable;
};
pinctrl_can1_default: can1-default {
pinmux = <PIN_PC26__CANTX1>,
<PIN_PC27__CANRX1>;
bias-disable;
};
pinctrl_debug_uart: debug-uart {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_flx1_default: flx1-default {
pinmux = <PIN_PA24__FLEXCOM1_IO0>,
<PIN_PA23__FLEXCOM1_IO1>,
<PIN_PA25__FLEXCOM1_IO3>,
<PIN_PA26__FLEXCOM1_IO4>;
bias-disable;
};
pinctrl_i2c0_default: i2c0-default {
pinmux = <PIN_PB31__TWD0>,
<PIN_PC0__TWCK0>;
bias-disable;
};
pinctrl_i2c0_gpio: i2c0-gpio-default {
pinmux = <PIN_PB31__GPIO>,
<PIN_PC0__GPIO>;
bias-disable;
};
pinctrl_i2c1_default: i2c1-default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_i2c1_gpio: i2c1-gpio-default {
pinmux = <PIN_PD4__GPIO>,
<PIN_PD5__GPIO>;
bias-disable;
};
pinctrl_key_gpio_default: key-gpio-default {
pinmux = <PIN_PA17__GPIO>;
bias-pull-up;
};
pinctrl_led_gpio_default: led-gpio-default {
pinmux = <PIN_PA7__GPIO>,
<PIN_PA8__GPIO>,
<PIN_PA9__GPIO>;
bias-pull-up;
};
pinctrl_mikrobus1_pwm: mikrobus1-pwm {
pinmux = <PIN_PA31__PWML0>;
bias-disable;
};
pinctrl_mikrobus2_pwm: mikrobus2-pwm {
pinmux = <PIN_PB0__PWMH1>;
bias-disable;
};
pinctrl_mikrobus1_uart: mikrobus1-uart {
pinmux = <PIN_PB3__URXD4>,
<PIN_PB4__UTXD4>;
bias-disable;
};
pinctrl_mikrobus2_uart: mikrobus2-uart {
pinmux = <PIN_PB11__URXD3>,
<PIN_PB12__UTXD3>;
bias-disable;
};
pinctrl_qspi1_default: qspi1-default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>,
<PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-disable;
};
pinctrl_rpi_spi: rpi-spi {
pinmux = <PIN_PD12__FLEXCOM4_IO0>,
<PIN_PD13__FLEXCOM4_IO1>,
<PIN_PD14__FLEXCOM4_IO2>,
<PIN_PD15__FLEXCOM4_IO3>,
<PIN_PD16__FLEXCOM4_IO4>;
bias-disable;
};
pinctrl_rpi_uart: rpi-uart {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
};
pinctrl_sdmmc0_default: sdmmc0-default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_sdmmc1_default: sdmmc1-default {
pinmux = <PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>,
<PIN_PA22__SDMMC1_CK>,
<PIN_PA28__SDMMC1_CMD>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
};
pinctrl_spi1_default: spi1-default {
pinmux = <PIN_PC1__SPI1_SPCK>,
<PIN_PC2__SPI1_MOSI>,
<PIN_PC3__SPI1_MISO>,
<PIN_PC4__SPI1_NPCS0>,
<PIN_PC5__SPI1_NPCS1>,
<PIN_PC6__SPI1_NPCS2>,
<PIN_PC7__SPI1_NPCS3>;
bias-disable;
};
pinctrl_usb_default: usb-default {
pinmux = <PIN_PA6__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba-vbus {
pinmux = <PIN_PB13__GPIO>;
bias-disable;
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_pwm &pinctrl_mikrobus2_pwm>;
status = "okay";
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
m25p,fast-read;
label = "atmel_qspi1";
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
};
};
&sdmmc0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
disable-wp;
status = "okay";
};
&sdmmc1 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
disable-wp;
status = "okay";
};
&shutdown_controller {
debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {
reg = <0>;
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
status = "okay";
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_debug_uart>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rpi_uart>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus2_uart>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_uart>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&usb0 {
atmel,vbus-gpio = <&pioA PIN_PB13 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PA6 GPIO_ACTIVE_HIGH
0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};
&watchdog {
status = "okay";
};

2
arch/arm/boot/dts/microchip/sama5d4.dtsi
View File

@ -694,7 +694,7 @@
clock-names = "aes_clk";
};
tdes: crpyto@fc04c000 {
tdes: crypto@fc04c000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xfc04c000 0x100>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;

4
arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts
View File

@ -146,7 +146,7 @@
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bmc@0{
bmc@0 {
label = "bmc";
reg = <0x000000 0x2000000>;
};
@ -155,7 +155,7 @@
reg = <0x0000000 0x80000>;
read-only;
};
u-boot-env@100000{
u-boot-env@100000 {
label = "u-boot-env";
reg = <0x00100000 0x40000>;
};

2
arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts
View File

@ -397,7 +397,7 @@
reg = <0x0000000 0xC0000>;
read-only;
};
u-boot-env@100000{
u-boot-env@100000 {
label = "u-boot-env";
reg = <0x00100000 0x40000>;
};

4
arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts
View File

@ -111,7 +111,7 @@
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bmc@0{
bmc@0 {
label = "bmc";
reg = <0x000000 0x2000000>;
};
@ -120,7 +120,7 @@
reg = <0x0000000 0x80000>;
read-only;
};
u-boot-env@100000{
u-boot-env@100000 {
label = "u-boot-env";
reg = <0x00100000 0x40000>;
};

2
arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts
View File

@ -65,7 +65,7 @@
rgb {
status = "okay";
port@0 {
port {
lcd_output: endpoint {
remote-endpoint = <&lvds_encoder_input>;
bus-width = <18>;

2
arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts
View File

@ -66,7 +66,7 @@
rgb {
status = "okay";
port@0 {
port {
lcd_output: endpoint {
remote-endpoint = <&lvds_encoder_input>;
bus-width = <18>;

2
arch/arm/boot/dts/nvidia/tegra30-asus-lvds-display.dtsi
View File

@ -10,7 +10,7 @@
rgb {
status = "okay";
port@0 {
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;

2
arch/arm/boot/dts/nvidia/tegra30-asus-tf700t.dts
View File

@ -15,7 +15,7 @@
rgb {
status = "okay";
port@0 {
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;

3
arch/arm/boot/dts/nxp/imx/Makefile
View File

@ -47,6 +47,8 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-qsb.dtb \
imx53-qsrb.dtb \
imx53-sk-imx53.dtb \
imx53-sk-imx53-atm0700d4-lvds.dtb \
imx53-sk-imx53-atm0700d4-rgb.dtb \
imx53-smd.dtb \
imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \
@ -244,6 +246,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-udoo.dtb \
imx6q-utilite-pro.dtb \
imx6q-var-dt6customboard.dtb \
imx6q-var-mx6customboard.dtb \
imx6q-vicut1.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \

7
arch/arm/boot/dts/nxp/imx/imx25.dtsi
View File

@ -529,7 +529,6 @@
compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
reg = <0x53fdc000 0x4000>;
clocks = <&clks 126>;
clock-names = "";
interrupts = <55>;
};
@ -583,10 +582,9 @@
};
dryice@53ffc000 {
compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
compatible = "fsl,imx25-rtc";
reg = <0x53ffc000 0x4000>;
clocks = <&clks 81>;
clock-names = "ipg";
interrupts = <25 56>;
};
};
@ -594,6 +592,9 @@
iram: sram@78000000 {
compatible = "mmio-sram";
reg = <0x78000000 0x20000>;
ranges = <0 0x78000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
};
emi@80000000 {

2
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi
View File

@ -34,7 +34,7 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
at24@52 {
eeprom@52 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;

2
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi
View File

@ -180,7 +180,7 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
at24@52 {
eeprom@52 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;

4
arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts
View File

@ -119,8 +119,8 @@
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_swi2c>;
gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>, /* sda */
<&gpio3 4 GPIO_ACTIVE_HIGH>; /* scl */
sda-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
scl-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <50>;
status = "okay";

2
arch/arm/boot/dts/nxp/imx/imx51.dtsi
View File

@ -651,7 +651,7 @@
};
sahara: crypto@83ff8000 {
compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
compatible = "fsl,imx53-sahara";
reg = <0x83ff8000 0x4000>;
interrupts = <19 20>;
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,

97
arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-lvds.dts Normal file
View File

@ -0,0 +1,97 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2023 Linaro Ltd.
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "imx53-sk-imx53-atm0700d4.dtsi"
/ {
lvds-decoder {
compatible = "ti,sn65lvds94", "lvds-decoder";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_decoder_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@1 {
reg = <1>;
lvds_decoder_out: endpoint {
remote-endpoint = <&panel_rgb_in>;
};
};
};
};
};
&iomuxc {
pinctrl_lvds0: lvds0grp {
/* LVDS pins only have pin mux configuration */
fsl,pins = <
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
>;
};
pinctrl_spi_gpio: spigrp {
fsl,pins = <
MX53_PAD_EIM_A22__GPIO2_16 0x1f4
MX53_PAD_EIM_A21__GPIO2_17 0x1f4
MX53_PAD_EIM_A16__GPIO2_22 0x1f4
MX53_PAD_EIM_A18__GPIO2_20 0x1f4
>;
};
};
&ldb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0>;
status = "okay";
lvds0: lvds-channel@0 {
reg = <0>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@2 {
reg = <2>;
lvds0_out: endpoint {
remote-endpoint = <&lvds_decoder_in>;
};
};
};
};
&panel_rgb_in {
remote-endpoint = <&lvds_decoder_out>;
};
&spi_ts {
pinctrl-0 = <&pinctrl_spi_gpio>;
pinctrl-names = "default";
sck-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
};
&touchscreen {
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_BOTH>;
pendown-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
};

112
arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4-rgb.dts Normal file
View File

@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2023 Linaro Ltd.
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "imx53-sk-imx53-atm0700d4.dtsi"
/ {
display: disp0 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-0 = <&pinctrl_rgb24>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_rgb_in>;
};
};
};
};
&iomuxc {
pinctrl_rgb24: rgb24grp {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
pinctrl_spi_gpio: spigrp {
fsl,pins = <
MX53_PAD_SD1_DATA1__GPIO1_17 0x1f4
MX53_PAD_GPIO_7__GPIO1_7 0x1f4
MX53_PAD_PATA_DATA3__GPIO2_3 0x1f4
MX53_PAD_PATA_DATA8__GPIO2_8 0x1f4
>;
};
};
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&panel {
enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
};
&panel_rgb_in {
remote-endpoint = <&display_out>;
};
&pwm1 {
status = "disabled";
};
&spi_ts {
pinctrl-0 = <&pinctrl_spi_gpio>;
pinctrl-names = "default";
sck-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
};
&touchscreen {
interrupts-extended = <&gpio2 6 IRQ_TYPE_EDGE_BOTH>;
pendown-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
};

45
arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2023 Linaro Ltd.
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "imx53-sk-imx53.dts"
/ {
panel: panel-rgb {
compatible = "powertip,ph800480t013-idf02";
port {
panel_rgb_in: endpoint {
};
};
};
spi_ts: spi {
compatible = "spi-gpio";
#address-cells = <0x1>;
#size-cells = <0x0>;
num-chipselects = <1>;
touchscreen: touchscreen@0 {
reg = <0>;
compatible = "ti,ads7843";
spi-max-frequency = <300000>;
ti,vref-mv = /bits/ 16 <3300>;
ti,x-plate-ohms = /bits/ 16 <450>;
ti,y-plate-ohms = /bits/ 16 <250>;
ti,debounce-tol = /bits/ 16 <10>;
ti,debounce-rep = /bits/ 16 <0>;
touchscreen-size-x = <4096>;
touchscreen-size-y = <4096>;
touchscreen-swapped-x-y;
touchscreen-max-pressure = <100>;
wakeup-source;
};
};
};

4
arch/arm/boot/dts/nxp/imx/imx53.dtsi
View File

@ -275,7 +275,7 @@
ecspi1: spi@50010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx53-ecspi";
reg = <0x50010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
@ -701,7 +701,7 @@
ecspi2: spi@63fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
compatible = "fsl,imx53-ecspi";
reg = <0x63fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,

4
arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts
View File

@ -98,8 +98,8 @@
};
&usbphy1 {
fsl,tx-cal-45-dn-ohms = <55>;
fsl,tx-cal-45-dp-ohms = <55>;
fsl,tx-cal-45-dn-ohms = <54>;
fsl,tx-cal-45-dp-ohms = <54>;
fsl,tx-d-cal = <100>;
};

4
arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts
View File

@ -637,11 +637,11 @@
};
&usbphy1 {
fsl,tx-d-cal = <0x5>;
fsl,tx-d-cal = <79>;
};
&usbphy2 {
fsl,tx-d-cal = <0x5>;
fsl,tx-d-cal = <79>;
};
&usdhc1 {

247
arch/arm/boot/dts/nxp/imx/imx6q-var-mx6customboard.dts Normal file
View File

@ -0,0 +1,247 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Carrier-board
*
* Copyright 2016 Variscite, Ltd. All Rights Reserved
* Copyright 2022 Bootlin
*/
/dts-v1/;
#include "imx6qdl-var-som.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Variscite i.MX6 QUAD/DUAL VAR-SOM-MX6 Custom Board";
compatible = "variscite,mx6customboard", "variscite,var-som-imx6q", "fsl,imx6q";
panel0: lvds-panel0 {
compatible = "panel-lvds";
backlight = <&backlight_lvds>;
width-mm = <152>;
height-mm = <91>;
label = "etm070001adh6";
data-mapping = "jeida-18";
panel-timing {
clock-frequency = <32000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <39>;
hfront-porch = <39>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <47>;
vsync-len = <2>;
};
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
panel1: lvds-panel1 {
compatible = "panel-lvds";
width-mm = <152>;
height-mm = <91>;
data-mapping = "jeida-18";
panel-timing {
clock-frequency = <38251000>;
hactive = <800>;
vactive = <600>;
hback-porch = <112>;
hfront-porch = <32>;
vback-porch = <3>;
vfront-porch = <17>;
hsync-len = <80>;
vsync-len = <4>;
};
port {
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds1_out>;
};
};
};
backlight_lvds: backlight-lvds {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000 0>;
brightness-levels = <0 4 8 16 32 64 128 248>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
touchscreen@24 {
compatible = "cypress,tt21000";
reg = <0x24>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3p3v>;
touchscreen-size-x = <880>;
touchscreen-size-y = <1280>;
};
touchscreen@38 {
compatible = "edt,edt-ft5306";
reg = <0x38>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
touchscreen-size-x = <1800>;
touchscreen-size-y = <1000>;
};
};
&iomuxc {
pinctrl_camera: cameragrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
>;
};
pinctrl_ipu1: ipu1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
>;
};
pinctrl_usbotg_var: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
port@4 {
reg = <4>;
lvds1_out: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};

46
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi
View File

@ -52,6 +52,11 @@
/ {
/* these are used by bootloader for disabling nodes */
aliases {
ethernet0 = &fec;
ethernet1 = &lan1;
ethernet2 = &lan2;
ethernet3 = &lan3;
ethernet4 = &lan4;
led0 = &led0;
led1 = &led1;
led2 = &led2;
@ -212,28 +217,61 @@
compatible = "marvell,mv88e6085";
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
lan4: port@0 {
reg = <0>;
label = "lan4";
phy-handle = <&sw_phy0>;
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
port@1 {
lan3: port@1 {
reg = <1>;
label = "lan3";
phy-handle = <&sw_phy1>;
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
port@2 {
lan2: port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&sw_phy2>;
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
port@3 {
lan1: port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&sw_phy3>;
phy-mode = "internal";
local-mac-address = [00 00 00 00 00 00];
};
port@5 {

1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi
View File

@ -326,7 +326,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio7>;
interrupts = <13 0>;
interrupt-names = "INT1";
};
};

1
arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi
View File

@ -307,7 +307,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio7>;
interrupts = <13 0>;
interrupt-names = "INT1";
};
};

2
arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi
View File

@ -15,7 +15,7 @@
reg = <0x10000000 0xF0000000>;
};
reg_1p8v: regulator@0 {
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;

569
arch/arm/boot/dts/nxp/imx/imx6qdl-var-som.dtsi Normal file
View File

@ -0,0 +1,569 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite VAR-SOM-MX6 Module
*
* Copyright 2011 Linaro Ltd.
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2014-2016 Variscite, Ltd.
* Author: Donio Ron <ron.d@variscite.com>
* Copyright 2022 Bootlin
*/
/dts-v1/;
#include "imx6q.dtsi"
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ {
model = "Variscite VAR-SOM-MX6 module";
compatible = "variscite,var-som-imx6q", "fsl,imx6q";
chosen {
stdout-path = &uart1;
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbud {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_wl18xx_vmmc: regulator-wl18xx {
compatible = "regulator-fixed";
regulator-name = "vwl1807";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <70000>;
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "var-som-audio";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_codec>;
simple-audio-card,frame-master = <&sound_codec>;
simple-audio-card,widgets = "Headphone", "Headphone Jack",
"Line", "Line In", "Microphone", "Mic Jack";
simple-audio-card,routing = "Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
sound_cpu: simple-audio-card,cpu {
sound-dai = <&ssi2>;
};
sound_codec: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&clks IMX6QDL_CLK_CKO>;
};
};
rfkill {
compatible = "rfkill-gpio";
name = "rfkill";
radio-type = "bluetooth";
shutdown-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
mux-ssi2 {
fsl,audmux-port = <1>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_SYN |
IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(2) |
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(2))
IMX_AUDMUX_V2_PDCR_RXDSEL(2)
>;
};
mux-aud3 {
fsl,audmux-port = <2>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(1)
>;
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-handle = <&rgmii_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
rgmii_phy: ethernet-phy@7 {
reg = <7>;
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3950000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
};
};
tlv320aic3106: audio-codec@1b {
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
#sound-dai-cells = <0>;
DRVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&reg_1p8v>;
ai3x-ocmv = <0>;
reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
ai3x-gpio-func = <
0 /* AIC3X_GPIO1_FUNC_DISABLED */
5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */
>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
/* Audio Clock */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
pinctrl_bt: btgrp {
fsl,pins = <
/* Bluetooth/wifi enable */
MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1
/* Wifi Slow Clock */
MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
pinctrl_enet_irq: enetirqgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* CTW6120 IRQ */
MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0xb0b1
/* SDMMC2 CD/WP */
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
/* PMIC INT */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17069
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10069
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17069
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17069
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17069
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17069
/* WL_EN */
MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x13059
/* WL_IRQ */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x13059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
/* WL_EN */
MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x130B9
/* WL_IRQ */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130B9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
/* WL_EN */
MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x130F9
/* WL_IRQ */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x130F9
>;
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&reg_arm {
vin-supply = <&sw1a_reg>;
};
&reg_pu {
vin-supply = <&sw1c_reg>;
};
&reg_soc {
vin-supply = <&sw1c_reg>;
};
&reg_vdd1p1 {
vin-supply = <&vgen5_reg>;
};
&reg_vdd2p5 {
vin-supply = <&vgen5_reg>;
};
&snvs_poweroff {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_var>;
disable-over-current;
dr_mode = "host";
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <0x5>;
};
&usbphy2 {
fsl,tx-d-cal = <0x5>;
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
non-removable;
keep-power-in-suspend;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_wl18xx_vmmc>;
non-removable;
wakeup-source;
keep-power-in-suspend;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi: wifi@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
ref-clock-frequency = <38400000>;
};
};

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