octeontx2-af: update cpt lf alloc mailbox
The CN10K CPT coprocessor contains a context processor to accelerate updates to the IPsec security association contexts. The context processor contains a context cache. This patch updates CPT LF ALLOC mailbox to config ctx_ilen requested by VFs. CPT_LF_ALLOC:ctx_ilen is the size of initial context fetch. Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1610,6 +1610,8 @@ struct cpt_lf_alloc_req_msg {
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u16 sso_pf_func;
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u16 sso_pf_func;
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u16 eng_grpmsk;
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u16 eng_grpmsk;
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int blkaddr;
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int blkaddr;
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u8 ctx_ilen_valid : 1;
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u8 ctx_ilen : 7;
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};
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};
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#define CPT_INLINE_INBOUND 0
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#define CPT_INLINE_INBOUND 0
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@ -17,7 +17,7 @@
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#define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
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#define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
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/* Length of initial context fetch in 128 byte words */
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/* Length of initial context fetch in 128 byte words */
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#define CPT_CTX_ILEN 2ULL
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#define CPT_CTX_ILEN 1ULL
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#define cpt_get_eng_sts(e_min, e_max, rsp, etype) \
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#define cpt_get_eng_sts(e_min, e_max, rsp, etype) \
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({ \
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({ \
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@ -421,8 +421,12 @@ int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
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/* Set CPT LF group and priority */
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/* Set CPT LF group and priority */
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val = (u64)req->eng_grpmsk << 48 | 1;
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val = (u64)req->eng_grpmsk << 48 | 1;
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if (!is_rvu_otx2(rvu))
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if (!is_rvu_otx2(rvu)) {
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val |= (CPT_CTX_ILEN << 17);
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if (req->ctx_ilen_valid)
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val |= (req->ctx_ilen << 17);
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else
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val |= (CPT_CTX_ILEN << 17);
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}
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rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
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rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
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