arm64: atomics: patch in lse instructions when supported by the CPU
On CPUs which support the LSE atomic instructions introduced in ARMv8.1, it makes sense to use them in preference to ll/sc sequences. This patch introduces runtime patching of atomic_t and atomic64_t routines so that the call-site for the out-of-line ll/sc sequences is patched with an LSE atomic instruction when we detect that the CPU supports it. If binutils is not recent enough to assemble the LSE instructions, then the ll/sc sequences are inlined as though CONFIG_ARM64_LSE_ATOMICS=n. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
c0385b24af
commit
c09d6a04d1
@ -17,7 +17,18 @@ GZFLAGS :=-9
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KBUILD_DEFCONFIG := defconfig
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KBUILD_CFLAGS += -mgeneral-regs-only
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# Check for binutils support for specific extensions
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lseinstr := $(call as-instr,.arch_extension lse,-DCONFIG_AS_LSE=1)
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ifeq ($(CONFIG_ARM64_LSE_ATOMICS), y)
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ifeq ($(lseinstr),)
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$(warning LSE atomics not supported by binutils)
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endif
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endif
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KBUILD_CFLAGS += -mgeneral-regs-only $(lseinstr)
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KBUILD_AFLAGS += $(lseinstr)
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ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)
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KBUILD_CPPFLAGS += -mbig-endian
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AS += -EB
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@ -21,11 +21,11 @@
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#define __ASM_ATOMIC_H
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#include <linux/compiler.h>
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#include <linux/stringify.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#include <asm/lse.h>
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#define ATOMIC_INIT(i) { (i) }
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@ -33,7 +33,7 @@
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#define __ARM64_IN_ATOMIC_IMPL
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#ifdef CONFIG_ARM64_LSE_ATOMICS
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#if defined(CONFIG_ARM64_LSE_ATOMICS) && defined(CONFIG_AS_LSE)
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#include <asm/atomic_lse.h>
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#else
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#include <asm/atomic_ll_sc.h>
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@ -37,18 +37,6 @@
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* (the optimize attribute silently ignores these options).
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*/
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#ifndef __LL_SC_INLINE
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#define __LL_SC_INLINE static inline
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#endif
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#ifndef __LL_SC_PREFIX
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#define __LL_SC_PREFIX(x) x
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#endif
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#ifndef __LL_SC_EXPORT
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#define __LL_SC_EXPORT(x)
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#endif
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#define ATOMIC_OP(op, asm_op) \
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__LL_SC_INLINE void \
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__LL_SC_PREFIX(atomic_##op(int i, atomic_t *v)) \
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@ -25,60 +25,129 @@
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#error "please don't include this file directly"
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#endif
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/* Move the ll/sc atomics out-of-line */
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#define __LL_SC_INLINE
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#define __LL_SC_PREFIX(x) __ll_sc_##x
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#define __LL_SC_EXPORT(x) EXPORT_SYMBOL(__LL_SC_PREFIX(x))
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#define __LL_SC_ATOMIC(op) __LL_SC_CALL(atomic_##op)
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/* Macros for constructing calls to out-of-line ll/sc atomics */
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#define __LL_SC_CALL(op) \
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"bl\t" __stringify(__LL_SC_PREFIX(atomic_##op)) "\n"
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#define __LL_SC_CALL64(op) \
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"bl\t" __stringify(__LL_SC_PREFIX(atomic64_##op)) "\n"
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static inline void atomic_andnot(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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#define ATOMIC_OP(op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile( \
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__LL_SC_CALL(op) \
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: "+r" (w0), "+Q" (v->counter) \
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: "r" (x1) \
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: "x30"); \
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} \
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#define ATOMIC_OP_RETURN(op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile( \
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__LL_SC_CALL(op##_return) \
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: "+r" (w0) \
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: "r" (x1) \
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: "x30", "memory"); \
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\
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return w0; \
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(andnot),
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" stclr %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_OP_RETURN(op, asm_op)
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static inline void atomic_or(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, sub)
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(or),
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" stset %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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ATOMIC_OP(and, and)
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ATOMIC_OP(andnot, bic)
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ATOMIC_OP(or, orr)
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ATOMIC_OP(xor, eor)
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static inline void atomic_xor(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(xor),
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" steor %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic_add(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(add),
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" stadd %w[i], %[v]\n")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(add_return),
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/* LSE atomics */
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" ldaddal %w[i], w30, %[v]\n"
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" add %w[i], %w[i], w30")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30", "memory");
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return w0;
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}
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static inline void atomic_and(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(and),
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/* LSE atomics */
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" mvn %w[i], %w[i]\n"
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" stclr %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(sub),
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/* LSE atomics */
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" neg %w[i], %w[i]\n"
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" stadd %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(sub_return)
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" nop",
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/* LSE atomics */
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" neg %w[i], %w[i]\n"
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" ldaddal %w[i], w30, %[v]\n"
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" add %w[i], %w[i], w30")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30", "memory");
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return w0;
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}
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static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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{
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@ -86,69 +155,164 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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register int w1 asm ("w1") = old;
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register int w2 asm ("w2") = new;
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asm volatile(
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__LL_SC_CALL(cmpxchg)
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: "+r" (x0)
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: "r" (w1), "r" (w2)
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC(cmpxchg)
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" nop",
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/* LSE atomics */
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" mov w30, %w[old]\n"
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" casal w30, %w[new], %[v]\n"
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" mov %w[ret], w30")
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: [ret] "+r" (x0), [v] "+Q" (ptr->counter)
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: [old] "r" (w1), [new] "r" (w2)
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: "x30", "cc", "memory");
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return x0;
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}
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#define ATOMIC64_OP(op, asm_op) \
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static inline void atomic64_##op(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile( \
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__LL_SC_CALL64(op) \
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: "+r" (x0), "+Q" (v->counter) \
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: "r" (x1) \
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: "x30"); \
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} \
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#undef __LL_SC_ATOMIC
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#define ATOMIC64_OP_RETURN(op, asm_op) \
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static inline long atomic64_##op##_return(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile( \
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__LL_SC_CALL64(op##_return) \
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: "+r" (x0) \
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: "r" (x1) \
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: "x30", "memory"); \
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\
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return x0; \
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#define __LL_SC_ATOMIC64(op) __LL_SC_CALL(atomic64_##op)
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static inline void atomic64_andnot(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(andnot),
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" stclr %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_OP_RETURN(op, asm_op)
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static inline void atomic64_or(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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ATOMIC64_OPS(add, add)
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ATOMIC64_OPS(sub, sub)
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(or),
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" stset %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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ATOMIC64_OP(and, and)
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ATOMIC64_OP(andnot, bic)
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ATOMIC64_OP(or, orr)
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ATOMIC64_OP(xor, eor)
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static inline void atomic64_xor(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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#undef ATOMIC64_OPS
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(xor),
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" steor %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic64_add(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(add),
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" stadd %[i], %[v]\n")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline long atomic64_add_return(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(add_return),
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/* LSE atomics */
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" ldaddal %[i], x30, %[v]\n"
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" add %[i], %[i], x30")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30", "memory");
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return x0;
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}
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static inline void atomic64_and(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(and),
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/* LSE atomics */
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" mvn %[i], %[i]\n"
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" stclr %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline void atomic64_sub(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(sub),
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/* LSE atomics */
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" neg %[i], %[i]\n"
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" stadd %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30");
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}
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static inline long atomic64_sub_return(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" nop\n"
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__LL_SC_ATOMIC64(sub_return)
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" nop",
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/* LSE atomics */
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" neg %[i], %[i]\n"
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" ldaddal %[i], x30, %[v]\n"
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" add %[i], %[i], x30")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: "x30", "memory");
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return x0;
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}
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static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
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{
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register unsigned long x0 asm ("x0") = (unsigned long)ptr;
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register long x1 asm ("x1") = old;
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register long x2 asm ("x2") = new;
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asm volatile(
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__LL_SC_CALL64(cmpxchg)
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: "+r" (x0)
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||||
: "r" (x1), "r" (x2)
|
||||
asm volatile(ARM64_LSE_ATOMIC_INSN(
|
||||
/* LL/SC */
|
||||
" nop\n"
|
||||
__LL_SC_ATOMIC64(cmpxchg)
|
||||
" nop",
|
||||
/* LSE atomics */
|
||||
" mov x30, %[old]\n"
|
||||
" casal x30, %[new], %[v]\n"
|
||||
" mov %[ret], x30")
|
||||
: [ret] "+r" (x0), [v] "+Q" (ptr->counter)
|
||||
: [old] "r" (x1), [new] "r" (x2)
|
||||
: "x30", "cc", "memory");
|
||||
|
||||
return x0;
|
||||
@ -156,15 +320,33 @@ static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
|
||||
|
||||
static inline long atomic64_dec_if_positive(atomic64_t *v)
|
||||
{
|
||||
register unsigned long x0 asm ("x0") = (unsigned long)v;
|
||||
register long x0 asm ("x0") = (long)v;
|
||||
|
||||
asm volatile(
|
||||
__LL_SC_CALL64(dec_if_positive)
|
||||
: "+r" (x0)
|
||||
asm volatile(ARM64_LSE_ATOMIC_INSN(
|
||||
/* LL/SC */
|
||||
" nop\n"
|
||||
__LL_SC_ATOMIC64(dec_if_positive)
|
||||
" nop\n"
|
||||
" nop\n"
|
||||
" nop\n"
|
||||
" nop\n"
|
||||
" nop",
|
||||
/* LSE atomics */
|
||||
"1: ldr x30, %[v]\n"
|
||||
" subs %[ret], x30, #1\n"
|
||||
" b.mi 2f\n"
|
||||
" casal x30, %[ret], %[v]\n"
|
||||
" sub x30, x30, #1\n"
|
||||
" sub x30, x30, %[ret]\n"
|
||||
" cbnz x30, 1b\n"
|
||||
"2:")
|
||||
: [ret] "+&r" (x0), [v] "+Q" (v->counter)
|
||||
:
|
||||
: "x30", "cc", "memory");
|
||||
|
||||
return x0;
|
||||
}
|
||||
|
||||
#undef __LL_SC_ATOMIC64
|
||||
|
||||
#endif /* __ASM_ATOMIC_LSE_H */
|
||||
|
||||
34
arch/arm64/include/asm/lse.h
Normal file
34
arch/arm64/include/asm/lse.h
Normal file
@ -0,0 +1,34 @@
|
||||
#ifndef __ASM_LSE_H
|
||||
#define __ASM_LSE_H
|
||||
|
||||
#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include <asm/alternative.h>
|
||||
#include <asm/cpufeature.h>
|
||||
|
||||
__asm__(".arch_extension lse");
|
||||
|
||||
/* Move the ll/sc atomics out-of-line */
|
||||
#define __LL_SC_INLINE
|
||||
#define __LL_SC_PREFIX(x) __ll_sc_##x
|
||||
#define __LL_SC_EXPORT(x) EXPORT_SYMBOL(__LL_SC_PREFIX(x))
|
||||
|
||||
/* Macro for constructing calls to out-of-line ll/sc atomics */
|
||||
#define __LL_SC_CALL(op) "bl\t" __stringify(__LL_SC_PREFIX(op)) "\n"
|
||||
|
||||
/* In-line patching at runtime */
|
||||
#define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
|
||||
ALTERNATIVE(llsc, lse, ARM64_CPU_FEAT_LSE_ATOMICS)
|
||||
|
||||
#else
|
||||
|
||||
#define __LL_SC_INLINE static inline
|
||||
#define __LL_SC_PREFIX(x) x
|
||||
#define __LL_SC_EXPORT(x)
|
||||
|
||||
#define ARM64_LSE_ATOMIC_INSN(llsc, lse) llsc
|
||||
|
||||
#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
|
||||
#endif /* __ASM_LSE_H */
|
||||
@ -285,6 +285,9 @@ static void __init setup_processor(void)
|
||||
case 2:
|
||||
elf_hwcap |= HWCAP_ATOMICS;
|
||||
cpus_set_cap(ARM64_CPU_FEAT_LSE_ATOMICS);
|
||||
if (IS_ENABLED(CONFIG_AS_LSE) &&
|
||||
IS_ENABLED(CONFIG_ARM64_LSE_ATOMICS))
|
||||
pr_info("LSE atomics supported\n");
|
||||
case 1:
|
||||
/* RESERVED */
|
||||
case 0:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user