Revert "drm/i915/tgl: Add extra hdc flush workaround"
This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4. The commit takes care Wa_1604544889 which was fixed on a0 stepping based on a0 replan. So no SW workaround is required on any stepping now. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add extra hdc flush workaround") Link: https://patchwork.freedesktop.org/patch/msgid/1c751032ce79c80c5485cae315f1a9904ce07cac.1583359940.git.caz.yokoyama@intel.com (cherry picked from commit 175c4d9b3b9a60b4ea0b8cd034011808c6a03b05) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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@ -4000,26 +4000,6 @@ static int gen12_emit_flush_render(struct i915_request *request,
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*cs++ = preparser_disable(false);
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intel_ring_advance(request, cs);
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/*
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* Wa_1604544889:tgl
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*/
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if (IS_TGL_REVID(request->i915, TGL_REVID_A0, TGL_REVID_A0)) {
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flags = 0;
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flags |= PIPE_CONTROL_CS_STALL;
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flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
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flags |= PIPE_CONTROL_STORE_DATA_INDEX;
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flags |= PIPE_CONTROL_QW_WRITE;
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cs = intel_ring_begin(request, 6);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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cs = gen8_emit_pipe_control(cs, flags,
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LRC_PPHWSP_SCRATCH_ADDR);
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intel_ring_advance(request, cs);
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}
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}
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return 0;
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