iio: adc: mt6370: Add MediaTek MT6370 support
MediaTek MT6370 is a SubPMIC consisting of a single cell battery charger with ADC monitoring, RGB LEDs, dual channel flashlight, WLED backlight driver, display bias voltage supply, one general purpose LDO, and the USB Type-C & PD controller complies with the latest USB Type-C and PD standards. Add support for the MT6370 ADC driver for system monitoring, including charger current, voltage, and temperature. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: ChiaEn Wu <chiaen_wu@richtek.com> Link: https://lore.kernel.org/r/81ec58ae89030e48508d6810396de2679c40d26c.1665488982.git.chiaen_wu@richtek.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
ChiaEn Wu
Jonathan Cameron
parent
8d2caf8b98
commit
c1404d1b65
@ -765,6 +765,18 @@ config MEDIATEK_MT6360_ADC
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is used in smartphones and tablets and supports a 11 channel
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general purpose ADC.
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config MEDIATEK_MT6370_ADC
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tristate "MediaTek MT6370 ADC driver"
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depends on MFD_MT6370
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help
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Say yes here to enable MediaTek MT6370 ADC support.
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This ADC driver provides 9 channels for system monitoring (charger
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current, voltage, and temperature).
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This driver can also be built as a module. If so, the module
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will be called "mt6370-adc".
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config MEDIATEK_MT6577_AUXADC
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tristate "MediaTek AUXADC driver"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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@ -70,6 +70,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o
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obj-$(CONFIG_MCP3422) += mcp3422.o
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obj-$(CONFIG_MCP3911) += mcp3911.o
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obj-$(CONFIG_MEDIATEK_MT6360_ADC) += mt6360-adc.o
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obj-$(CONFIG_MEDIATEK_MT6370_ADC) += mt6370-adc.o
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obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
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obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o
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obj-$(CONFIG_MESON_SARADC) += meson_saradc.o
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305
drivers/iio/adc/mt6370-adc.c
Normal file
305
drivers/iio/adc/mt6370-adc.c
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@ -0,0 +1,305 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2022 Richtek Technology Corp.
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*
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* Author: ChiaEn Wu <chiaen_wu@richtek.com>
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*/
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/iio/iio.h>
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#include <linux/kernel.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/sysfs.h>
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#include <linux/units.h>
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#include <dt-bindings/iio/adc/mediatek,mt6370_adc.h>
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#define MT6370_REG_CHG_CTRL3 0x113
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#define MT6370_REG_CHG_CTRL7 0x117
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#define MT6370_REG_CHG_ADC 0x121
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#define MT6370_REG_ADC_DATA_H 0x14C
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#define MT6370_ADC_START_MASK BIT(0)
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#define MT6370_ADC_IN_SEL_MASK GENMASK(7, 4)
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#define MT6370_AICR_ICHG_MASK GENMASK(7, 2)
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#define MT6370_AICR_100_mA 0x0
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#define MT6370_AICR_150_mA 0x1
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#define MT6370_AICR_200_mA 0x2
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#define MT6370_AICR_250_mA 0x3
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#define MT6370_AICR_300_mA 0x4
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#define MT6370_AICR_350_mA 0x5
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#define MT6370_ICHG_100_mA 0x0
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#define MT6370_ICHG_200_mA 0x1
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#define MT6370_ICHG_300_mA 0x2
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#define MT6370_ICHG_400_mA 0x3
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#define MT6370_ICHG_500_mA 0x4
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#define MT6370_ICHG_600_mA 0x5
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#define MT6370_ICHG_700_mA 0x6
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#define MT6370_ICHG_800_mA 0x7
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#define ADC_CONV_TIME_MS 35
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#define ADC_CONV_POLLING_TIME_US 1000
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struct mt6370_adc_data {
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struct device *dev;
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struct regmap *regmap;
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/*
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* This mutex lock is for preventing the different ADC channels
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* from being read at the same time.
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*/
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struct mutex adc_lock;
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};
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static int mt6370_adc_read_channel(struct mt6370_adc_data *priv, int chan,
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unsigned long addr, int *val)
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{
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unsigned int reg_val;
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__be16 be_val;
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int ret;
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mutex_lock(&priv->adc_lock);
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reg_val = MT6370_ADC_START_MASK |
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FIELD_PREP(MT6370_ADC_IN_SEL_MASK, addr);
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ret = regmap_write(priv->regmap, MT6370_REG_CHG_ADC, reg_val);
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if (ret)
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goto adc_unlock;
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msleep(ADC_CONV_TIME_MS);
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ret = regmap_read_poll_timeout(priv->regmap,
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MT6370_REG_CHG_ADC, reg_val,
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!(reg_val & MT6370_ADC_START_MASK),
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ADC_CONV_POLLING_TIME_US,
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ADC_CONV_TIME_MS * MILLI * 3);
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if (ret) {
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dev_err(priv->dev, "Failed to read ADC register (%d)\n", ret);
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goto adc_unlock;
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}
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ret = regmap_raw_read(priv->regmap, MT6370_REG_ADC_DATA_H,
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&be_val, sizeof(be_val));
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if (ret)
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goto adc_unlock;
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*val = be16_to_cpu(be_val);
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ret = IIO_VAL_INT;
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adc_unlock:
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mutex_unlock(&priv->adc_lock);
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return ret;
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}
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static int mt6370_adc_read_scale(struct mt6370_adc_data *priv,
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int chan, int *val1, int *val2)
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{
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unsigned int reg_val;
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int ret;
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switch (chan) {
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case MT6370_CHAN_VBAT:
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case MT6370_CHAN_VSYS:
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case MT6370_CHAN_CHG_VDDP:
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*val1 = 5;
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return IIO_VAL_INT;
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case MT6370_CHAN_IBUS:
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ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL3, ®_val);
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if (ret)
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return ret;
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reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val);
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switch (reg_val) {
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case MT6370_AICR_100_mA:
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case MT6370_AICR_150_mA:
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case MT6370_AICR_200_mA:
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case MT6370_AICR_250_mA:
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case MT6370_AICR_300_mA:
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case MT6370_AICR_350_mA:
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*val1 = 3350;
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break;
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default:
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*val1 = 5000;
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break;
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}
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*val2 = 100;
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return IIO_VAL_FRACTIONAL;
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case MT6370_CHAN_IBAT:
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ret = regmap_read(priv->regmap, MT6370_REG_CHG_CTRL7, ®_val);
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if (ret)
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return ret;
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reg_val = FIELD_GET(MT6370_AICR_ICHG_MASK, reg_val);
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switch (reg_val) {
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case MT6370_ICHG_100_mA:
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case MT6370_ICHG_200_mA:
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case MT6370_ICHG_300_mA:
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case MT6370_ICHG_400_mA:
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*val1 = 2375;
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break;
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case MT6370_ICHG_500_mA:
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case MT6370_ICHG_600_mA:
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case MT6370_ICHG_700_mA:
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case MT6370_ICHG_800_mA:
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*val1 = 2680;
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break;
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default:
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*val1 = 5000;
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break;
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}
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*val2 = 100;
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return IIO_VAL_FRACTIONAL;
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case MT6370_CHAN_VBUSDIV5:
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*val1 = 25;
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return IIO_VAL_INT;
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case MT6370_CHAN_VBUSDIV2:
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*val1 = 10;
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return IIO_VAL_INT;
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case MT6370_CHAN_TS_BAT:
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*val1 = 25;
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*val2 = 10000;
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return IIO_VAL_FRACTIONAL;
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case MT6370_CHAN_TEMP_JC:
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*val1 = 2000;
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int mt6370_adc_read_offset(struct mt6370_adc_data *priv,
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int chan, int *val)
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{
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*val = -20;
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return IIO_VAL_INT;
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}
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static int mt6370_adc_read_raw(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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int *val, int *val2, long mask)
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{
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struct mt6370_adc_data *priv = iio_priv(iio_dev);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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return mt6370_adc_read_channel(priv, chan->channel,
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chan->address, val);
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case IIO_CHAN_INFO_SCALE:
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return mt6370_adc_read_scale(priv, chan->channel, val, val2);
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case IIO_CHAN_INFO_OFFSET:
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return mt6370_adc_read_offset(priv, chan->channel, val);
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default:
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return -EINVAL;
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}
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}
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static const char * const mt6370_channel_labels[MT6370_CHAN_MAX] = {
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[MT6370_CHAN_VBUSDIV5] = "vbusdiv5",
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[MT6370_CHAN_VBUSDIV2] = "vbusdiv2",
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[MT6370_CHAN_VSYS] = "vsys",
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[MT6370_CHAN_VBAT] = "vbat",
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[MT6370_CHAN_TS_BAT] = "ts_bat",
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[MT6370_CHAN_IBUS] = "ibus",
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[MT6370_CHAN_IBAT] = "ibat",
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[MT6370_CHAN_CHG_VDDP] = "chg_vddp",
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[MT6370_CHAN_TEMP_JC] = "temp_jc",
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};
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static int mt6370_adc_read_label(struct iio_dev *iio_dev,
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struct iio_chan_spec const *chan, char *label)
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{
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return sysfs_emit(label, "%s\n", mt6370_channel_labels[chan->channel]);
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}
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static const struct iio_info mt6370_adc_iio_info = {
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.read_raw = mt6370_adc_read_raw,
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.read_label = mt6370_adc_read_label,
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};
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#define MT6370_ADC_CHAN(_idx, _type, _addr, _extra_info) { \
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.type = _type, \
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.channel = MT6370_CHAN_##_idx, \
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.address = _addr, \
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.scan_index = MT6370_CHAN_##_idx, \
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.indexed = 1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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_extra_info, \
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}
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static const struct iio_chan_spec mt6370_adc_channels[] = {
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MT6370_ADC_CHAN(VBUSDIV5, IIO_VOLTAGE, 1, 0),
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MT6370_ADC_CHAN(VBUSDIV2, IIO_VOLTAGE, 2, 0),
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MT6370_ADC_CHAN(VSYS, IIO_VOLTAGE, 3, 0),
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MT6370_ADC_CHAN(VBAT, IIO_VOLTAGE, 4, 0),
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MT6370_ADC_CHAN(TS_BAT, IIO_VOLTAGE, 6, 0),
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MT6370_ADC_CHAN(IBUS, IIO_CURRENT, 8, 0),
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MT6370_ADC_CHAN(IBAT, IIO_CURRENT, 9, 0),
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MT6370_ADC_CHAN(CHG_VDDP, IIO_VOLTAGE, 11, 0),
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MT6370_ADC_CHAN(TEMP_JC, IIO_TEMP, 12, BIT(IIO_CHAN_INFO_OFFSET)),
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};
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static int mt6370_adc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mt6370_adc_data *priv;
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struct iio_dev *indio_dev;
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struct regmap *regmap;
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int ret;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!regmap)
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return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n");
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indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
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if (!indio_dev)
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return -ENOMEM;
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priv = iio_priv(indio_dev);
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priv->dev = dev;
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priv->regmap = regmap;
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mutex_init(&priv->adc_lock);
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ret = regmap_write(priv->regmap, MT6370_REG_CHG_ADC, 0);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to reset ADC\n");
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indio_dev->name = "mt6370-adc";
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indio_dev->info = &mt6370_adc_iio_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->channels = mt6370_adc_channels;
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indio_dev->num_channels = ARRAY_SIZE(mt6370_adc_channels);
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return devm_iio_device_register(dev, indio_dev);
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}
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static const struct of_device_id mt6370_adc_of_id[] = {
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{ .compatible = "mediatek,mt6370-adc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, mt6370_adc_of_id);
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static struct platform_driver mt6370_adc_driver = {
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.driver = {
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.name = "mt6370-adc",
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.of_match_table = mt6370_adc_of_id,
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},
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.probe = mt6370_adc_probe,
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};
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module_platform_driver(mt6370_adc_driver);
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MODULE_AUTHOR("ChiaEn Wu <chiaen_wu@richtek.com>");
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MODULE_DESCRIPTION("MT6370 ADC Driver");
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MODULE_LICENSE("GPL v2");
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