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drm/amd/display: Drop unnecessary DCN guards

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[Why & How]
DC is littered with many DCN guards that are not needed.
Drop them.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2023-02-13 17:58:22 -05:00 committed by Alex Deucher
parent bf77fda024
commit c186c13e65
15 changed files with 16 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
View File

@ -47,9 +47,7 @@ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_c
*/
memcpy(&dc->vm_pa_config, pa_config, sizeof(struct dc_phy_addr_space_config));
dc->vm_pa_config.valid = true;
#if defined(CONFIG_DRM_AMD_DC_DCN)
dc_z10_save_init(dc);
#endif
}
return num_vmids;

2
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@ -421,7 +421,6 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi
}
}
#ifdef CONFIG_DRM_AMD_DC_DCN
/**
* populate_subvp_cmd_drr_info - Helper to populate DRR pipe info for the DMCUB subvp command
*
@ -776,7 +775,6 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
}
#endif
bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv, struct dmub_diagnostic_data *diag_data)
{

27
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@ -930,7 +930,13 @@ static bool dce112_program_pix_clk(
REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
/* Enable DTO */
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1,
PIPE0_DTO_SRC_SEL, 1);
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
return true;
}
/* First disable SS
@ -995,7 +1001,6 @@ static bool dcn31_program_pix_clk(
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Enable DTO */
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
if (encoding == DP_128b_132b_ENCODING)
@ -1009,9 +1014,6 @@ static bool dcn31_program_pix_clk(
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
#else
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
#endif
} else {
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
@ -1023,7 +1025,6 @@ static bool dcn31_program_pix_clk(
REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
/* Enable DTO */
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1,
@ -1031,17 +1032,12 @@ static bool dcn31_program_pix_clk(
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
#else
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
#endif
return true;
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE(PIXEL_RATE_CNTL[inst],
PIPE0_DTO_SRC_SEL, 0);
#endif
/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
bp_pc_params.controller_id = pix_clk_params->controller_id;
@ -1274,7 +1270,14 @@ static bool dcn3_program_pix_clk(
REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
}
REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
/* Enable DTO */
if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL)
REG_UPDATE_2(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1,
PIPE0_DTO_SRC_SEL, 1);
else
REG_UPDATE(PIXEL_RATE_CNTL[inst],
DP_DTO0_ENABLE, 1);
} else
// For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings);

6
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
View File

@ -204,23 +204,17 @@
type DP_DTO0_MODULO; \
type DP_DTO0_ENABLE;
#if defined(CONFIG_DRM_AMD_DC_DCN)
#define CS_REG_FIELD_LIST_DCN32(type) \
type PIPE0_DTO_SRC_SEL;
#endif
struct dce110_clk_src_shift {
CS_REG_FIELD_LIST(uint8_t)
#if defined(CONFIG_DRM_AMD_DC_DCN)
CS_REG_FIELD_LIST_DCN32(uint8_t)
#endif
};
struct dce110_clk_src_mask{
CS_REG_FIELD_LIST(uint32_t)
#if defined(CONFIG_DRM_AMD_DC_DCN)
CS_REG_FIELD_LIST_DCN32(uint32_t)
#endif
};
struct dce110_clk_src_regs {

5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
View File

@ -23,8 +23,6 @@
*
*/
#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "reg_helper.h"
#include "resource.h"
#include "dwb.h"
@ -129,6 +127,3 @@ void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
dwbc10->dwbc_shift = dwbc_shift;
dwbc10->dwbc_mask = dwbc_mask;
}
#endif

4
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
View File

@ -24,8 +24,6 @@
#ifndef __DC_DWBC_DCN10_H__
#define __DC_DWBC_DCN10_H__
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* DCN */
#define BASE_INNER(seg) \
DCE_BASE__INST0_SEG ## seg
@ -267,5 +265,3 @@ void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
int inst);
#endif
#endif

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
View File

@ -1470,10 +1470,9 @@ void enc1_se_hdmi_audio_setup(
void enc1_se_hdmi_audio_disable(
struct stream_encoder *enc)
{
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
enc->afmt->funcs->afmt_powerdown(enc->afmt);
#endif
enc1_se_enable_audio_clock(enc, false);
}

2
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
View File

@ -1163,7 +1163,6 @@ static bool dcn303_resource_construct(
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
#if defined(CONFIG_DRM_AMD_DC_DCN)
dc->caps.mall_size_per_mem_channel = 4;
/* total size = mall per channel * num channels * 1024 * 1024 */
dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
@ -1171,7 +1170,6 @@ static bool dcn303_resource_construct(
1024 * 1024;
dc->caps.cursor_cache_size =
dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
#endif
dc->caps.max_slave_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;

2
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
View File

@ -23,7 +23,6 @@
*
*/
#ifdef CONFIG_DRM_AMD_DC_DCN
#include "dc.h"
#include "../display_mode_lib.h"
#include "display_mode_vba_30.h"
@ -6634,4 +6633,3 @@ static noinline_for_stack void UseMinimumDCFCLK(
}
}
#endif /* CONFIG_DRM_AMD_DC_DCN */

3
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c
View File

@ -23,8 +23,6 @@
*
*/
#ifdef CONFIG_DRM_AMD_DC_DCN
#include "../display_mode_lib.h"
#include "../display_mode_vba.h"
#include "../dml_inline_defs.h"
@ -1792,4 +1790,3 @@ void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
}
#endif

6
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
View File

@ -53,9 +53,7 @@ enum dwb_source {
/* DCN1.x, DCN2.x support 2 pipes */
enum dwb_pipe {
dwb_pipe0 = 0,
#if defined(CONFIG_DRM_AMD_DC_DCN)
dwb_pipe1,
#endif
dwb_pipe_max_num,
};
@ -72,14 +70,11 @@ enum wbscl_coef_filter_type_sel {
};
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dwb_boundary_mode {
DWBSCL_BOUNDARY_MODE_EDGE = 0,
DWBSCL_BOUNDARY_MODE_BLACK = 1
};
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN)
enum dwb_output_csc_mode {
DWB_OUTPUT_CSC_DISABLE = 0,
DWB_OUTPUT_CSC_COEF_A = 1,
@ -132,7 +127,6 @@ struct dwb_efc_display_settings {
unsigned int dwbOutputBlack; // 0 - Normal, 1 - Output Black
};
#endif
struct dwb_warmup_params {
bool warmup_en; /* false: normal mode, true: enable pattern generator */
bool warmup_mode; /* false: 420, true: 444 */

2
drivers/gpu/drm/amd/display/dc/link/link_validation.c
View File

@ -261,13 +261,11 @@ uint32_t link_timing_bandwidth_kbps(
uint32_t bits_per_channel = 0;
uint32_t kbps;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (timing->flags.DSC)
return dc_dsc_stream_bandwidth_in_kbps(timing,
timing->dsc_cfg.bits_per_pixel,
timing->dsc_cfg.num_slices_h,
timing->dsc_cfg.is_dp);
#endif /* CONFIG_DRM_AMD_DC_DCN */
switch (timing->display_color_depth) {
case COLOR_DEPTH_666:

2
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
View File

@ -723,12 +723,10 @@ void override_training_settings(
if (link->preferred_training_settings.fec_enable != NULL)
lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
#if defined(CONFIG_DRM_AMD_DC_DCN)
/* Check DP tunnel LTTPR mode debug option. */
if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)
lt_settings->lttpr_mode = LTTPR_MODE_NON_LTTPR;
#endif
dp_get_lttpr_mode_override(link, &lt_settings->lttpr_mode);
}

5
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
View File

@ -695,7 +695,6 @@ bool edp_setup_psr(struct dc_link *link,
psr_context->psr_level.u32all = 0;
/*skip power down the single pipe since it blocks the cstate*/
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
switch (link->ctx->asic_id.chip_family) {
case FAMILY_YELLOW_CARP:
@ -709,10 +708,6 @@ bool edp_setup_psr(struct dc_link *link,
break;
}
}
#else
if (link->ctx->asic_id.chip_family >= FAMILY_RV)
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
#endif
/* SMU will perform additional powerdown sequence.
* For unsupported ASICs, set psr_level flag to skip PSR

7
drivers/gpu/drm/amd/display/modules/power/power_helpers.c
View File

@ -678,13 +678,8 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
bool result = false;
uint32_t i, j = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL)
return false;
#else
if (res_pool->abm == NULL)
return false;
#endif
memset(&ram_table, 0, sizeof(ram_table));
memset(&config, 0, sizeof(config));
@ -737,12 +732,10 @@ bool dmub_init_abm_config(struct resource_pool *res_pool,
config.min_abm_backlight = ram_table.min_abm_backlight;
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (res_pool->multiple_abms[inst]) {
result = res_pool->multiple_abms[inst]->funcs->init_abm_config(
res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst);
} else
#endif
result = res_pool->abm->funcs->init_abm_config(
res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0);