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Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next

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* clk-of:
  clk: add missing of_node_put() in "assigned-clocks" property parsing

* clk-samsung:
  clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical
  clk: samsung: Convert to platform remove callback returning void
  clk: samsung: exynos5433: Extract PM support to common ARM64 layer
  clk: samsung: Extract parent clock enabling to common function
  clk: samsung: Extract clocks registration to common function
  clk: samsung: exynos850: Add AUD and HSI main gate clocks
  clk: samsung: exynos850: Implement CMU_G3D domain
  clk: samsung: clk-pll: Implement pll0818x PLL type
  clk: samsung: Set dev in samsung_clk_init()
  clk: samsung: Don't pass reg_base to samsung_clk_register_pll()
  clk: samsung: Remove np argument from samsung_clk_init()
  dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
  dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D

* clk-rockchip:
  clk: rockchip: rk3588: make gate linked clocks critical
  clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent

* clk-qcom: (57 commits)
  clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
  clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
  clk: qcom: add the GPUCC driver for sa8775p
  dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
  clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
  clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
  clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
  dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
  clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  dt-bindings: clock: Add ipq9574 clock and reset definitions
  clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value
  clk: qcom: gcc-sm6115: Mark RCGs shared where applicable
  clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset
  dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset
  clk: qcom: apss-ipq-pll: add support for IPQ5332
  dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
  clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types
  dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match
  dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks
  ...
This commit is contained in:
Stephen Boyd 2023-04-25 11:52:25 -07:00
commit c19c6c7b44
84 changed files with 20477 additions and 1629 deletions
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49
Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
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@ -1,49 +0,0 @@
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of:
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the first element specifies the base address and size of
the register region. An optional second element specifies
the base address and size of the alias register region.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the pll parents.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "pll8_vote", "pxo".
- clock-output-names:
Usage: optional
Value type: <string>
Definition: Name of the output clock. Typically acpuX_aux where X is a
CPU number starting at 0.
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
};

44
Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
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@ -1,44 +0,0 @@
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of the following. The generic compatible
"qcom,kpss-gcc" should also be included.
"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: base address and size of the register region
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the pll parents.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "pll8_vote", "pxo".
- clock-output-names:
Usage: required
Value type: <string>
Definition: Name of the output clock. Typically acpu_l2_aux indicating
an L2 cache auxiliary clock.
Example:
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};

1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
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@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,msm8916-a53pll

53
Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ4019
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Robert Marko <robert.markoo@sartura.hr>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ4019.
See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq4019
clocks:
items:
- description: board XO clock
- description: sleep clock
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq4019";
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
};
...

13
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
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@ -4,20 +4,25 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8909
title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8909.
domains on MSM8909, MSM8917 or QM215.
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8909.h
include/dt-bindings/clock/qcom,gcc-msm8917.h
properties:
compatible:
const: qcom,gcc-msm8909
enum:
- qcom,gcc-msm8909
- qcom,gcc-msm8917
- qcom,gcc-qm215
clocks:
items:

2
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
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@ -15,7 +15,6 @@ description: |
domains.
See also::
include/dt-bindings/clock/qcom,gcc-ipq4019.h
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
@ -29,7 +28,6 @@ allOf:
properties:
compatible:
enum:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8953

2
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
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@ -15,6 +15,7 @@ description: |
See also::
include/dt-bindings/clock/qcom,gpucc-sdm845.h
include/dt-bindings/clock/qcom,gpucc-sa8775p.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h
include/dt-bindings/clock/qcom,gpucc-sc7280.h
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
@ -27,6 +28,7 @@ properties:
compatible:
enum:
- qcom,sdm845-gpucc
- qcom,sa8775p-gpucc
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc

53
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5332
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5332.
See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,ipq5332-gcc
clocks:
items:
- description: Board XO clock source
- description: Sleep clock source
- description: PCIE 2lane PHY pipe clock source
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
- description: USB PCIE wrapper pipe clock source
required:
- compatible
- clocks
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq5332-gcc";
reg = <0x01800000 0x80000>;
clocks = <&xo_board>,
<&sleep_clk>,
<&pcie_2lane_phy_pipe_clk>,
<&pcie_2lane_phy_pipe_clk_x1>,
<&usb_pcie_wrapper_pipe_clk>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

61
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml Normal file
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ9574
maintainers:
- Anusha Rao <quic_anusha@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ9574
See also::
include/dt-bindings/clock/qcom,ipq9574-gcc.h
include/dt-bindings/reset/qcom,ipq9574-gcc.h
properties:
compatible:
const: qcom,ipq9574-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Bias PLL ubi clock source
- description: PCIE30 PHY0 pipe clock source
- description: PCIE30 PHY1 pipe clock source
- description: PCIE30 PHY2 pipe clock source
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq9574-gcc";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&bias_pll_ubi_nc_clk>,
<&pcie30_phy0_pipe_clk>,
<&pcie30_phy1_pipe_clk>,
<&pcie30_phy2_pipe_clk>,
<&pcie30_phy3_pipe_clk>,
<&usb3phy_0_cc_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

72
Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml Normal file
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@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
description:
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region. ACC v1 is currently used as a
clock-controller for enabling the cpu and hanling the aux clocks.
properties:
compatible:
const: qcom,kpss-acc-v1
reg:
items:
- description: Base address and size of the register region
- description: Optional base address and size of the alias register region
minItems: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pll8_vote
- const: pxo
clock-output-names:
description: Name of the aux clock. Krait can have at most 4 cpu.
enum:
- acpu0_aux
- acpu1_aux
- acpu2_aux
- acpu3_aux
'#clock-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- clock-output-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
...

88
Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml Normal file
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@ -0,0 +1,88 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
description:
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
to control L2 mux (in the current implementation) and provide access
to the kpss-gcc registers.
properties:
compatible:
items:
- enum:
- qcom,kpss-gcc-ipq8064
- qcom,kpss-gcc-apq8064
- qcom,kpss-gcc-msm8974
- qcom,kpss-gcc-msm8960
- qcom,kpss-gcc-msm8660
- qcom,kpss-gcc-mdm9615
- const: qcom,kpss-gcc
- const: syscon
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pll8_vote
- const: pxo
'#clock-cells':
const: 0
required:
- compatible
- reg
if:
properties:
compatible:
contains:
enum:
- qcom,kpss-gcc-ipq8064
- qcom,kpss-gcc-apq8064
- qcom,kpss-gcc-msm8974
- qcom,kpss-gcc-msm8960
then:
required:
- clocks
- clock-names
- '#clock-cells'
else:
properties:
clock: false
clock-names: false
'#clock-cells': false
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
clock-controller@2011000 {
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
#clock-cells = <0>;
};
- |
clock-controller@2011000 {
compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
reg = <0x02011000 0x1000>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
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@ -31,6 +31,7 @@ properties:
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
@ -107,6 +108,7 @@ allOf:
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974

7
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
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@ -41,6 +41,12 @@ properties:
- const: qdsp6ss
- const: top_cc
qcom,adsp-pil-mode:
description:
Indicates if the LPASS would be brought out of reset using
remoteproc peripheral loader.
type: boolean
required:
- compatible
- reg
@ -60,6 +66,7 @@ examples:
reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
qcom,adsp-pil-mode;
#clock-cells = <1>;
};
...

58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml Normal file
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@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6115
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
domains on Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
properties:
compatible:
enum:
- qcom,sm6115-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 main div source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
clock-controller@5990000 {
compatible = "qcom,sm6115-gpucc";
reg = <0x05990000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml Normal file
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@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6125
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks and power domains on
Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
properties:
compatible:
enum:
- qcom,sm6125-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
clock-controller@5990000 {
compatible = "qcom,sm6125-gpucc";
reg = <0x05990000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
};
...

60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml Normal file
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@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
domains on Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
properties:
compatible:
enum:
- qcom,sm6375-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 div branch source
- description: SNoC DVM GFX source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@5990000 {
compatible = "qcom,sm6375-gpucc";
reg = <0 0x05990000 0 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

52
Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml Normal file
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM7150
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <davidwronek@gmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM7150
See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h
properties:
compatible:
const: qcom,sm7150-gcc
clocks:
items:
- description: Board XO source
- description: Board XO Active-Only source
- description: Sleep clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm7150-gcc";
reg = <0x00100000 0x001f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

19
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
View File

@ -37,6 +37,7 @@ properties:
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-g3d
- samsung,exynos850-cmu-hsi
- samsung,exynos850-cmu-is
- samsung,exynos850-cmu-mfcmscl
@ -169,6 +170,24 @@ allOf:
- const: oscclk
- const: dout_dpu
- if:
properties:
compatible:
contains:
const: samsung,exynos850-cmu-g3d
then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: G3D clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: dout_g3d_switch
- if:
properties:
compatible:

9
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
View File

@ -91,20 +91,21 @@ allOf:
- if:
properties:
compatible:
enum:
- qcom,sdx55-apcs-gcc
contains:
enum:
- qcom,sdx55-apcs-gcc
then:
properties:
clocks:
items:
- description: reference clock
- description: primary pll parent of the clock driver
- description: auxiliary parent
- description: reference clock
clock-names:
items:
- const: ref
- const: pll
- const: aux
- const: ref
- if:
properties:
compatible:

42
Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml Normal file
View File

@ -0,0 +1,42 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/qcom,kpss-acc-v2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v2
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
description:
The KPSS ACC provides clock, power manager, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region. ACC v2 is currently used as a
power-manager for enabling the cpu.
properties:
compatible:
const: qcom,kpss-acc-v2
reg:
items:
- description: Base address and size of the register region
- description: Optional base address and size of the alias register region
minItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
power-manager@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>,
<0xf9008000 0x1000>;
};
...

12
drivers/clk/clk-conf.c
View File

@ -33,9 +33,12 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
else
return rc;
}
if (clkspec.np == node && !clk_supplier)
if (clkspec.np == node && !clk_supplier) {
of_node_put(clkspec.np);
return 0;
}
pclk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(pclk)) {
if (PTR_ERR(pclk) != -EPROBE_DEFER)
pr_warn("clk: couldn't get parent clock %d for %pOF\n",
@ -48,10 +51,12 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
if (rc < 0)
goto err;
if (clkspec.np == node && !clk_supplier) {
of_node_put(clkspec.np);
rc = 0;
goto err;
}
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
@ -93,10 +98,13 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)
else
return rc;
}
if (clkspec.np == node && !clk_supplier)
if (clkspec.np == node && !clk_supplier) {
of_node_put(clkspec.np);
return 0;
}
clk = of_clk_get_from_provider(&clkspec);
of_node_put(clkspec.np);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
pr_warn("clk: couldn't get clock %d for %pOF\n",

70
drivers/clk/qcom/Kconfig
View File

@ -141,6 +141,14 @@ config IPQ_GCC_4019
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
config IPQ_GCC_5332
tristate "IPQ5332 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
help
Support for the global clock controller on ipq5332 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
config IPQ_GCC_6018
tristate "IPQ6018 Global Clock Controller"
help
@ -173,6 +181,14 @@ config IPQ_GCC_8074
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq8074.
config IPQ_GCC_9574
tristate "IPQ9574 Global Clock Controller"
help
Support for global clock controller on ipq9574 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq9574.
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
help
@ -196,6 +212,16 @@ config MSM_GCC_8916
Say Y if you want to use devices such as UART, SPI i2c, USB,
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8917
tristate "MSM8917/QM215 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on msm8917 and qm215
devices.
Say Y if you want to use devices such as UART, SPI i2c, USB,
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8939
tristate "MSM8939 Global Clock Controller"
select QCOM_GDSC
@ -419,6 +445,15 @@ config SA_GCC_8775P
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
config SA_GPUCC_8775P
tristate "SA8775P Graphics clock controller"
select QCOM_GDSC
select SA_GCC_8775P
help
Support for the graphics clock controller on SA8775P devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SC_GCC_7180
tristate "SC7180 Global Clock Controller"
select QCOM_GDSC
@ -759,6 +794,14 @@ config SM_GCC_6375
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS etc.
config SM_GCC_7150
tristate "SM7150 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SM7150 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help
@ -798,6 +841,33 @@ config SM_GCC_8550
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_6115
tristate "SM6115 Graphics Clock Controller"
select SM_GCC_6115
depends on ARM64 || COMPILE_TEST
help
Support for the graphics clock controller on SM6115 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_GPUCC_6125
tristate "SM6125 Graphics Clock Controller"
select SM_GCC_6125
depends on ARM64 || COMPILE_TEST
help
Support for the graphics clock controller on SM6125 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_GPUCC_6375
tristate "SM6375 Graphics Clock Controller"
select SM_GCC_6375
depends on ARM64 || COMPILE_TEST
help
Support for the graphics clock controller on SM6375 devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config SM_GPUCC_6350
tristate "SM6350 Graphics Clock Controller"
select SM_GCC_6350

8
drivers/clk/qcom/Makefile
View File

@ -24,9 +24,11 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
@ -34,6 +36,7 @@ obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o
obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
obj-$(CONFIG_MSM_GCC_8917) += gcc-msm8917.o
obj-$(CONFIG_MSM_GCC_8939) += gcc-msm8939.o
obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
@ -69,6 +72,7 @@ obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o
obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
@ -107,12 +111,16 @@ obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
obj-$(CONFIG_SM_GCC_6350) += gcc-sm6350.o
obj-$(CONFIG_SM_GCC_6375) += gcc-sm6375.o
obj-$(CONFIG_SM_GCC_7150) += gcc-sm7150.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o
obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o

6
drivers/clk/qcom/apcs-msm8916.c
View File

@ -119,18 +119,16 @@ err:
return ret;
}
static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
static void qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
{
struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
return 0;
}
static struct platform_driver qcom_apcs_msm8916_clk_driver = {
.probe = qcom_apcs_msm8916_clk_probe,
.remove = qcom_apcs_msm8916_clk_remove,
.remove_new = qcom_apcs_msm8916_clk_remove,
.driver = {
.name = "qcom-apcs-msm8916-clk",
},

6
drivers/clk/qcom/apcs-sdx55.c
View File

@ -120,20 +120,18 @@ err:
return ret;
}
static int qcom_apcs_sdx55_clk_remove(struct platform_device *pdev)
static void qcom_apcs_sdx55_clk_remove(struct platform_device *pdev)
{
struct device *cpu_dev = get_cpu_device(0);
struct clk_regmap_mux_div *a7cc = platform_get_drvdata(pdev);
clk_notifier_unregister(a7cc->pclk, &a7cc->clk_nb);
dev_pm_domain_detach(cpu_dev, true);
return 0;
}
static struct platform_driver qcom_apcs_sdx55_clk_driver = {
.probe = qcom_apcs_sdx55_clk_probe,
.remove = qcom_apcs_sdx55_clk_remove,
.remove_new = qcom_apcs_sdx55_clk_remove,
.driver = {
.name = "qcom-sdx55-acps-clk",
},

116
drivers/clk/qcom/apss-ipq-pll.c
View File

@ -8,20 +8,38 @@
#include "clk-alpha-pll.h"
static const u8 ipq_pll_offsets[] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
/*
* Even though APSS PLL type is of existing one (like Huayra), its offsets
* are different from the one mentioned in the clk-alpha-pll.c, since the
* PLL is specific to APSS, so lets the define the same.
*/
static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = {
[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_STATUS] = 0x28,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
},
};
static struct clk_alpha_pll ipq_pll = {
static struct clk_alpha_pll ipq_pll_huayra = {
.offset = 0x0,
.regs = ipq_pll_offsets,
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
@ -37,6 +55,38 @@ static struct clk_alpha_pll ipq_pll = {
},
};
static struct clk_alpha_pll ipq_pll_stromer_plus = {
.offset = 0x0,
.regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.enable_reg = 0x0,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "a53pll",
.parent_data = &(const struct clk_parent_data) {
.fw_name = "xo",
},
.num_parents = 1,
.ops = &clk_alpha_pll_stromer_ops,
},
},
};
static const struct alpha_pll_config ipq5332_pll_config = {
.l = 0x3e,
.config_ctl_val = 0x4001075b,
.config_ctl_hi_val = 0x304,
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.early_output_mask = BIT(3),
.alpha_en_mask = BIT(24),
.status_val = 0x3,
.status_mask = GENMASK(10, 8),
.lock_det = BIT(2),
.test_ctl_hi_val = 0x00400003,
};
static const struct alpha_pll_config ipq6018_pll_config = {
.l = 0x37,
.config_ctl_val = 0x240d4828,
@ -61,6 +111,30 @@ static const struct alpha_pll_config ipq8074_pll_config = {
.test_ctl_hi_val = 0x4000,
};
struct apss_pll_data {
int pll_type;
struct clk_alpha_pll *pll;
const struct alpha_pll_config *pll_config;
};
static struct apss_pll_data ipq5332_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
.pll = &ipq_pll_stromer_plus,
.pll_config = &ipq5332_pll_config,
};
static struct apss_pll_data ipq8074_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq8074_pll_config,
};
static struct apss_pll_data ipq6018_pll_data = {
.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
.pll = &ipq_pll_huayra,
.pll_config = &ipq6018_pll_config,
};
static const struct regmap_config ipq_pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@ -71,7 +145,7 @@ static const struct regmap_config ipq_pll_regmap_config = {
static int apss_ipq_pll_probe(struct platform_device *pdev)
{
const struct alpha_pll_config *ipq_pll_config;
const struct apss_pll_data *data;
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
@ -85,23 +159,27 @@ static int apss_ipq_pll_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
ipq_pll_config = of_device_get_match_data(&pdev->dev);
if (!ipq_pll_config)
data = of_device_get_match_data(&pdev->dev);
if (!data)
return -ENODEV;
clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA)
clk_alpha_pll_configure(data->pll, regmap, data->pll_config);
else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS)
clk_stromer_pll_configure(data->pll, regmap, data->pll_config);
ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
ret = devm_clk_register_regmap(dev, &data->pll->clkr);
if (ret)
return ret;
return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
&ipq_pll.clkr.hw);
&data->pll->clkr.hw);
}
static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

139
drivers/clk/qcom/clk-alpha-pll.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
@ -204,6 +204,29 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_CONFIG_CTL] = 0x1C,
[PLL_OFF_STATUS] = 0x20,
},
[CLK_ALPHA_PLL_TYPE_STROMER] = {
[PLL_OFF_L_VAL] = 0x08,
[PLL_OFF_ALPHA_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL_U] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0xff,
[PLL_OFF_TEST_CTL] = 0x30,
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
},
[CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_USER_CTL] = 0x08,
[PLL_OFF_USER_CTL_U] = 0x0c,
[PLL_OFF_CONFIG_CTL] = 0x10,
[PLL_OFF_TEST_CTL] = 0x14,
[PLL_OFF_TEST_CTL_U] = 0x18,
[PLL_OFF_STATUS] = 0x1c,
[PLL_OFF_ALPHA_VAL] = 0x24,
[PLL_OFF_ALPHA_VAL_U] = 0x28,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@ -215,6 +238,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define ALPHA_BITWIDTH 32U
#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
#define ALPHA_PLL_STATUS_REG_SHIFT 8
#define PLL_HUAYRA_M_WIDTH 8
#define PLL_HUAYRA_M_SHIFT 8
#define PLL_HUAYRA_M_MASK 0xff
@ -2329,3 +2354,115 @@ const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
.round_rate = clk_rivian_evo_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, val_u, mask, mask_u;
regmap_write(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
if (pll_has_64bit_config(pll))
regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
config->config_ctl_hi_val);
if (pll_alpha_width(pll) > 32)
regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
val = config->main_output_mask;
val |= config->aux_output_mask;
val |= config->aux2_output_mask;
val |= config->early_output_mask;
val |= config->pre_div_val;
val |= config->post_div_val;
val |= config->vco_val;
val |= config->alpha_en_mask;
val |= config->alpha_mode_mask;
mask = config->main_output_mask;
mask |= config->aux_output_mask;
mask |= config->aux2_output_mask;
mask |= config->early_output_mask;
mask |= config->pre_div_mask;
mask |= config->post_div_mask;
mask |= config->vco_mask;
mask |= config->alpha_en_mask;
mask |= config->alpha_mode_mask;
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
/* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
val_u |= config->lock_det;
mask_u = config->status_mask;
mask_u |= config->lock_det;
regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
if (pll->flags & SUPPORTS_FSM_MODE)
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
}
EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
u32 l;
u64 a;
req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
&l, &a, ALPHA_REG_BITWIDTH);
return 0;
}
static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
int ret;
u32 l;
u64 a;
rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
a >> ALPHA_BITWIDTH);
regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
PLL_ALPHA_EN, PLL_ALPHA_EN);
if (!clk_hw_is_enabled(hw))
return 0;
/*
* Stromer PLL supports Dynamic programming.
* It allows the PLL frequency to be changed on-the-fly without first
* execution of a shutdown procedure followed by a bring up procedure.
*/
regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
PLL_UPDATE);
ret = wait_for_pll_update(pll);
if (ret)
return ret;
return wait_for_pll_enable_lock(pll);
}
const struct clk_ops clk_alpha_pll_stromer_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.is_enabled = clk_alpha_pll_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.determine_rate = clk_alpha_pll_stromer_determine_rate,
.set_rate = clk_alpha_pll_stromer_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);

14
drivers/clk/qcom/clk-alpha-pll.h
View File

@ -1,5 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
/*
* Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __QCOM_CLK_ALPHA_PLL_H__
#define __QCOM_CLK_ALPHA_PLL_H__
@ -22,6 +26,8 @@ enum {
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_STROMER,
CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
CLK_ALPHA_PLL_TYPE_MAX,
};
@ -131,6 +137,9 @@ struct alpha_pll_config {
u32 post_div_mask;
u32 vco_val;
u32 vco_mask;
u32 status_val;
u32 status_mask;
u32 lock_det;
};
extern const struct clk_ops clk_alpha_pll_ops;
@ -139,6 +148,7 @@ extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
extern const struct clk_ops clk_alpha_pll_huayra_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
extern const struct clk_ops clk_alpha_pll_stromer_ops;
extern const struct clk_ops clk_alpha_pll_fabia_ops;
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
@ -188,5 +198,7 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
const struct alpha_pll_config *config);
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
#endif

15
drivers/clk/qcom/clk-branch.c
View File

@ -39,27 +39,22 @@ static bool clk_branch_check_halt(const struct clk_branch *br, bool enabling)
return !!val == !enabling;
}
#define BRANCH_CLK_OFF BIT(31)
#define BRANCH_NOC_FSM_STATUS_SHIFT 28
#define BRANCH_NOC_FSM_STATUS_MASK 0x7
#define BRANCH_NOC_FSM_STATUS_ON (0x2 << BRANCH_NOC_FSM_STATUS_SHIFT)
static bool clk_branch2_check_halt(const struct clk_branch *br, bool enabling)
{
u32 val;
u32 mask;
mask = BRANCH_NOC_FSM_STATUS_MASK << BRANCH_NOC_FSM_STATUS_SHIFT;
mask |= BRANCH_CLK_OFF;
mask = CBCR_NOC_FSM_STATUS;
mask |= CBCR_CLK_OFF;
regmap_read(br->clkr.regmap, br->halt_reg, &val);
if (enabling) {
val &= mask;
return (val & BRANCH_CLK_OFF) == 0 ||
val == BRANCH_NOC_FSM_STATUS_ON;
return (val & CBCR_CLK_OFF) == 0 ||
FIELD_GET(CBCR_NOC_FSM_STATUS, val) == FSM_STATUS_ON;
} else {
return val & BRANCH_CLK_OFF;
return val & CBCR_CLK_OFF;
}
}

44
drivers/clk/qcom/clk-branch.h
View File

@ -4,6 +4,7 @@
#ifndef __QCOM_CLK_BRANCH_H__
#define __QCOM_CLK_BRANCH_H__
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include "clk-regmap.h"
@ -37,6 +38,49 @@ struct clk_branch {
struct clk_regmap clkr;
};
/* Branch clock common bits for HLOS-owned clocks */
#define CBCR_CLK_OFF BIT(31)
#define CBCR_NOC_FSM_STATUS GENMASK(30, 28)
#define FSM_STATUS_ON BIT(1)
#define CBCR_FORCE_MEM_CORE_ON BIT(14)
#define CBCR_FORCE_MEM_PERIPH_ON BIT(13)
#define CBCR_FORCE_MEM_PERIPH_OFF BIT(12)
#define CBCR_WAKEUP GENMASK(11, 8)
#define CBCR_SLEEP GENMASK(7, 4)
static inline void qcom_branch_set_force_mem_core(struct regmap *regmap,
struct clk_branch clk, bool on)
{
regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_CORE_ON,
on ? CBCR_FORCE_MEM_CORE_ON : 0);
}
static inline void qcom_branch_set_force_periph_on(struct regmap *regmap,
struct clk_branch clk, bool on)
{
regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_ON,
on ? CBCR_FORCE_MEM_PERIPH_ON : 0);
}
static inline void qcom_branch_set_force_periph_off(struct regmap *regmap,
struct clk_branch clk, bool on)
{
regmap_update_bits(regmap, clk.halt_reg, CBCR_FORCE_MEM_PERIPH_OFF,
on ? CBCR_FORCE_MEM_PERIPH_OFF : 0);
}
static inline void qcom_branch_set_wakeup(struct regmap *regmap, struct clk_branch clk, u32 val)
{
regmap_update_bits(regmap, clk.halt_reg, CBCR_WAKEUP,
FIELD_PREP(CBCR_WAKEUP, val));
}
static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branch clk, u32 val)
{
regmap_update_bits(regmap, clk.halt_reg, CBCR_SLEEP,
FIELD_PREP(CBCR_SLEEP, val));
}
extern const struct clk_ops clk_branch_ops;
extern const struct clk_ops clk_branch2_ops;
extern const struct clk_ops clk_branch_simple_ops;

14
drivers/clk/qcom/clk-hfpll.c
View File

@ -128,20 +128,20 @@ static void clk_hfpll_disable(struct clk_hw *hw)
spin_unlock_irqrestore(&h->lock, flags);
}
static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int clk_hfpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct clk_hfpll *h = to_clk_hfpll(hw);
struct hfpll_data const *hd = h->d;
unsigned long rrate;
rate = clamp(rate, hd->min_rate, hd->max_rate);
req->rate = clamp(req->rate, hd->min_rate, hd->max_rate);
rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate;
if (rrate > hd->max_rate)
rrate -= *parent_rate;
rrate -= req->best_parent_rate;
return rrate;
req->rate = rrate;
return 0;
}
/*
@ -241,7 +241,7 @@ const struct clk_ops clk_ops_hfpll = {
.enable = clk_hfpll_enable,
.disable = clk_hfpll_disable,
.is_enabled = hfpll_is_enabled,
.round_rate = clk_hfpll_round_rate,
.determine_rate = clk_hfpll_determine_rate,
.set_rate = clk_hfpll_set_rate,
.recalc_rate = clk_hfpll_recalc_rate,
.init = clk_hfpll_init,

10
drivers/clk/qcom/clk-krait.c
View File

@ -97,11 +97,11 @@ const struct clk_ops krait_mux_clk_ops = {
EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
static int krait_div2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
return DIV_ROUND_UP(*parent_rate, 2);
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2);
req->rate = DIV_ROUND_UP(req->best_parent_rate, 2);
return 0;
}
static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
@ -142,7 +142,7 @@ krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
}
const struct clk_ops krait_div2_clk_ops = {
.round_rate = krait_div2_round_rate,
.determine_rate = krait_div2_determine_rate,
.set_rate = krait_div2_set_rate,
.recalc_rate = krait_div2_recalc_rate,
};

11
drivers/clk/qcom/clk-rpm.c
View File

@ -580,8 +580,8 @@ static int rpm_clk_probe(struct platform_device *pdev)
goto err;
}
ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get,
rcc);
ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_rpm_clk_hw_get,
rcc);
if (ret)
goto err;
@ -591,19 +591,12 @@ err:
return ret;
}
static int rpm_clk_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
return 0;
}
static struct platform_driver rpm_clk_driver = {
.driver = {
.name = "qcom-clk-rpm",
.of_match_table = rpm_clk_match_table,
},
.probe = rpm_clk_probe,
.remove = rpm_clk_remove,
};
static int __init rpm_clk_init(void)

37
drivers/clk/qcom/clk-smd-rpm.c
View File

@ -573,6 +573,40 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
.num_clks = ARRAY_SIZE(msm8916_clks),
};
static struct clk_smd_rpm *msm8917_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
[RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk,
[RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk,
[RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk,
[RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk,
[RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk,
[RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk,
[RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk,
[RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk,
[RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk,
[RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1,
[RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a,
[RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2,
[RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a,
[RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2,
[RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a,
[RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2,
[RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a,
[RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin,
[RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin,
[RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin,
[RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin,
};
static const struct rpm_smd_clk_desc rpm_clk_msm8917 = {
.clks = msm8917_clks,
.num_clks = ARRAY_SIZE(msm8917_clks),
};
static struct clk_smd_rpm *msm8936_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
@ -610,6 +644,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
};
static struct clk_smd_rpm *msm8974_clks[] = {
[RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo,
[RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a,
[RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk,
[RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk,
[RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk,
@ -1228,6 +1264,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
{ .compatible = "qcom,rpmcc-msm8909", .data = &rpm_clk_msm8909 },
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
{ .compatible = "qcom,rpmcc-msm8917", .data = &rpm_clk_msm8917 },
{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
{ .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },

10
drivers/clk/qcom/dispcc-qcm2290.c
View File

@ -20,13 +20,13 @@
#include "clk-regmap-divider.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
P_BI_TCXO,
P_DISP_CC_PLL0_OUT_MAIN,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_DSI1_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
P_SLEEP_CLK,
};
@ -106,13 +106,11 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
static const struct parent_map disp_cc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
};
static const struct clk_parent_data disp_cc_parent_data_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "dsi0_phy_pll_out_dsiclk" },
{ .fw_name = "dsi1_phy_pll_out_dsiclk" },
};
static const struct parent_map disp_cc_parent_map_5[] = {
@ -445,6 +443,10 @@ static struct clk_branch disp_cc_sleep_clk = {
},
};
static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
};
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
@ -494,6 +496,8 @@ static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
.num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks),
.gdscs = disp_cc_qcm2290_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
.resets = disp_cc_qcm2290_resets,
.num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets),
};
static const struct of_device_id disp_cc_qcm2290_match_table[] = {

2265
drivers/clk/qcom/gcc-ipq4019.c
View File

File diff suppressed because it is too large Load Diff

3824
drivers/clk/qcom/gcc-ipq5332.c Normal file
View File

File diff suppressed because it is too large Load Diff

4248
drivers/clk/qcom/gcc-ipq9574.c Normal file
View File

File diff suppressed because it is too large Load Diff

3303
drivers/clk/qcom/gcc-msm8917.c Normal file
View File

File diff suppressed because it is too large Load Diff

6
drivers/clk/qcom/gcc-msm8960.c
View File

@ -3754,19 +3754,17 @@ static int gcc_msm8960_probe(struct platform_device *pdev)
return 0;
}
static int gcc_msm8960_remove(struct platform_device *pdev)
static void gcc_msm8960_remove(struct platform_device *pdev)
{
struct platform_device *tsens = platform_get_drvdata(pdev);
if (tsens)
platform_device_unregister(tsens);
return 0;
}
static struct platform_driver gcc_msm8960_driver = {
.probe = gcc_msm8960_probe,
.remove = gcc_msm8960_remove,
.remove_new = gcc_msm8960_remove,
.driver = {
.name = "gcc-msm8960",
.of_match_table = gcc_msm8960_match_table,

3
drivers/clk/qcom/gcc-msm8996.c
View File

@ -3455,7 +3455,8 @@ static struct gdsc usb30_gdsc = {
.pd = {
.name = "usb30",
},
.pwrsts = PWRSTS_OFF_ON,
/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc pcie0_gdsc = {

3
drivers/clk/qcom/gcc-msm8998.c
View File

@ -2898,7 +2898,8 @@ static struct gdsc usb_30_gdsc = {
.pd = {
.name = "usb_30_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
.pwrsts = PWRSTS_RET_ON,
.flags = VOTABLE,
};

3
drivers/clk/qcom/gcc-qcm2290.c
View File

@ -1243,7 +1243,8 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_12,
.num_parents = ARRAY_SIZE(gcc_parents_12),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_floor_ops,
.flags = CLK_OPS_PARENT_ENABLE,
},
};

18
drivers/clk/qcom/gcc-sc8280xp.c
View File

@ -6873,6 +6873,22 @@ static struct gdsc usb30_sec_gdsc = {
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc emac_0_gdsc = {
.gdscr = 0xaa004,
.pd = {
.name = "emac_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct gdsc emac_1_gdsc = {
.gdscr = 0xba004,
.pd = {
.name = "emac_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
};
static struct clk_regmap *gcc_sc8280xp_clocks[] = {
[GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie0_tunnel_axi_clk.clkr,
[GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] = &gcc_aggre_noc_pcie1_tunnel_axi_clk.clkr,
@ -7351,6 +7367,8 @@ static struct gdsc *gcc_sc8280xp_gdscs[] = {
[USB30_MP_GDSC] = &usb30_mp_gdsc,
[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
[USB30_SEC_GDSC] = &usb30_sec_gdsc,
[EMAC_0_GDSC] = &emac_0_gdsc,
[EMAC_1_GDSC] = &emac_1_gdsc,
};
static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {

50
drivers/clk/qcom/gcc-sm6115.c
View File

@ -694,7 +694,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = {
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -715,7 +715,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = {
.parent_data = gcc_parents_9,
.num_parents = ARRAY_SIZE(gcc_parents_9),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -738,7 +738,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -753,7 +753,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -768,7 +768,7 @@ static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
.parent_data = gcc_parents_4,
.num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -790,7 +790,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -805,7 +805,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -820,7 +820,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -835,7 +835,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
.parent_data = gcc_parents_3,
.num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -857,7 +857,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = {
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -881,7 +881,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = {
.parent_data = gcc_parents_8,
.num_parents = ARRAY_SIZE(gcc_parents_8),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -916,7 +916,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = {
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -941,7 +941,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = {
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -956,7 +956,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = {
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -971,7 +971,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = {
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -986,7 +986,7 @@ static struct clk_rcg2 gcc_camss_tfe_2_clk_src = {
.parent_data = gcc_parents_5,
.num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1001,7 +1001,7 @@ static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = {
.parent_data = gcc_parents_6,
.num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1024,7 +1024,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = {
.parent_data = gcc_parents_10,
.num_parents = ARRAY_SIZE(gcc_parents_10),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1046,7 +1046,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = {
.parent_data = gcc_parents_7,
.num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1116,7 +1116,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1329,7 +1329,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1351,7 +1351,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1392,7 +1392,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1414,7 +1414,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0,
.num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};
@ -1483,7 +1483,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = {
.parent_data = gcc_parents_13,
.num_parents = ARRAY_SIZE(gcc_parents_13),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_shared_ops,
},
};

3
drivers/clk/qcom/gcc-sm6375.c
View File

@ -3534,7 +3534,8 @@ static struct gdsc usb30_prim_gdsc = {
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
/* TODO: Change to OFF_ON when USB drivers get proper suspend support */
.pwrsts = PWRSTS_RET_ON,
};
static struct gdsc ufs_phy_gdsc = {

3048
drivers/clk/qcom/gcc-sm7150.c Normal file
View File

File diff suppressed because it is too large Load Diff

47
drivers/clk/qcom/gcc-sm8350.c
View File

@ -17,6 +17,7 @@
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
@ -158,26 +159,6 @@ static const struct clk_parent_data gcc_parent_data_3[] = {
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_PCIE_0_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .fw_name = "pcie_0_pipe_clk", },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_PCIE_1_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .fw_name = "pcie_1_pipe_clk" },
{ .fw_name = "bi_tcxo" },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
@ -274,32 +255,30 @@ static const struct clk_parent_data gcc_parent_data_14[] = {
{ .fw_name = "bi_tcxo" },
};
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b054,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_4,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_0_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0x8d054,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_5,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.ops = &clk_regmap_mux_closest_ops,
.parent_data = &(const struct clk_parent_data){
.fw_name = "pcie_1_pipe_clk",
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};

625
drivers/clk/qcom/gpucc-sa8775p.c Normal file
View File

@ -0,0 +1,625 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "common.h"
#include "reset.h"
#include "gdsc.h"
/* Need to match the order of clocks in DT binding */
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_MAIN,
};
static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
static const struct pll_vco lucid_evo_vco[] = {
{ 249600000, 2020000000, 0 },
};
/* 810MHz configuration */
static struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x2a,
.alpha = 0x3000,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00400805,
};
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
/* 1000MHz configuration */
static struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x34,
.alpha = 0x1555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00182261,
.config_ctl_hi1_val = 0x32aa299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00400805,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x1000,
.vco_table = lucid_evo_vco,
.num_vco = ARRAY_SIZE(lucid_evo_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
.clkr = {
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &parent_data_tcxo,
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_evo_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gpu_cc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_ff_clk_src = {
.cmd_rcgr = 0x9474,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_ff_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x9318,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_hub_clk_src = {
.cmd_rcgr = 0x93ec,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_2,
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_xo_clk_src = {
.cmd_rcgr = 0x9010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_3,
.freq_tbl = ftbl_gpu_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_xo_clk_src",
.parent_data = gpu_cc_parent_data_3,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
.reg = 0x9054,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_demet_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
.reg = 0x9430,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_ahb_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
.reg = 0x942c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gpu_cc_hub_cx_int_div_clk_src",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x911c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x911c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cb_clk = {
.halt_reg = 0x93a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x9120,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9120,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_ff_clk = {
.halt_reg = 0x914c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x914c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_ff_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x913c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x913c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x9130,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x9004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x9144,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9144,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_demet_clk = {
.halt_reg = 0x900c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x900c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_demet_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_demet_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x7000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hub_aon_clk = {
.halt_reg = 0x93e8,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x93e8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_aon_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_hub_cx_int_clk = {
.halt_reg = 0x9148,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9148,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hub_cx_int_clk",
.parent_hws = (const struct clk_hw*[]){
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.halt_reg = 0x9150,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x9150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_memnoc_gfx_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x9134,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x9134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
[GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
[GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
};
static struct gdsc cx_gdsc = {
.gdscr = 0x9108,
.gds_hw_ctrl = 0x953c,
.pd = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON,
};
static struct gdsc gx_gdsc = {
.gdscr = 0x905c,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
},
.pwrsts = PWRSTS_OFF_ON,
.flags = AON_RESET | RETAIN_FF_ENABLE,
};
static struct gdsc *gpu_cc_sa8775p_gdscs[] = {
[GPU_CC_CX_GDSC] = &cx_gdsc,
[GPU_CC_GX_GDSC] = &gx_gdsc,
};
static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = {
[GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
[GPUCC_GPU_CC_CB_BCR] = { 0x93a0 },
[GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
[GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
[GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
[GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
[GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
};
static const struct regmap_config gpu_cc_sa8775p_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9988,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
.config = &gpu_cc_sa8775p_regmap_config,
.clks = gpu_cc_sa8775p_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks),
.resets = gpu_cc_sa8775p_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets),
.gdscs = gpu_cc_sa8775p_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs),
};
static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
{ .compatible = "qcom,sa8775p-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table);
static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap);
}
static struct platform_driver gpu_cc_sa8775p_driver = {
.probe = gpu_cc_sa8775p_probe,
.driver = {
.name = "gpu_cc-sa8775p",
.of_match_table = gpu_cc_sa8775p_match_table,
},
};
static int __init gpu_cc_sa8775p_init(void)
{
return platform_driver_register(&gpu_cc_sa8775p_driver);
}
subsys_initcall(gpu_cc_sa8775p_init);
static void __exit gpu_cc_sa8775p_exit(void)
{
platform_driver_unregister(&gpu_cc_sa8775p_driver);
}
module_exit(gpu_cc_sa8775p_exit);
MODULE_DESCRIPTION("SA8775P GPUCC driver");
MODULE_LICENSE("GPL");

503
drivers/clk/qcom/gpucc-sm6115.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPLL0_OUT_MAIN_DIV,
P_GPU_CC_PLL0_OUT_AUX2,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL1_OUT_AUX,
P_GPU_CC_PLL1_OUT_MAIN,
};
static struct pll_vco default_vco[] = {
{ 1000000000, 2000000000, 0 },
};
static struct pll_vco pll1_vco[] = {
{ 500000000, 1000000000, 2 },
};
static const struct alpha_pll_config gpu_cc_pll0_config = {
.l = 0x3e,
.alpha = 0,
.alpha_hi = 0x80,
.vco_val = 0x0 << 20,
.vco_mask = GENMASK(21, 20),
.alpha_en_mask = BIT(24),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.aux2_output_mask = BIT(2),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
};
/* 1200MHz configuration */
static struct clk_alpha_pll gpu_cc_pll0 = {
.offset = 0x0,
.vco_table = default_vco,
.num_vco = ARRAY_SIZE(default_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = {
.offset = 0x0,
.post_div_shift = 8,
.post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0_out_aux2",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_pll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
/* 640MHz configuration */
static const struct alpha_pll_config gpu_cc_pll1_config = {
.l = 0x21,
.alpha = 0x55555555,
.alpha_hi = 0x55,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.aux_output_mask = BIT(1),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
};
static struct clk_alpha_pll gpu_cc_pll1 = {
.offset = 0x100,
.vco_table = pll1_vco,
.num_vco = ARRAY_SIZE(pll1_vco),
.flags = SUPPORTS_DYNAMIC_UPDATE,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = {
{ 0x0, 1 },
{ }
};
static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = {
.offset = 0x100,
.post_div_shift = 15,
.post_div_table = post_div_table_gpu_cc_pll1_out_aux,
.num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux),
.width = 3,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1_out_aux",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_pll1.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_alpha_pll_postdiv_ops,
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
{ P_GPLL0_OUT_MAIN_DIV, 6 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
{ P_GPU_CC_PLL1_OUT_AUX, 3 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
{ .hw = &gpu_cc_pll1_out_aux.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0),
F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_cxo_clk = {
.halt_reg = 0x1060,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_cxo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR },
.reset_count = 1,
.pd = {
.name = "gpu_gx_gdsc",
},
.parent = &gpu_cx_gdsc.pd,
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | SW_RESET | VOTABLE,
};
static struct clk_regmap *gpu_cc_sm6115_clocks[] = {
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
[GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};
static const struct qcom_reset_map gpu_cc_sm6115_resets[] = {
[GPU_GX_BCR] = { 0x1008 },
};
static struct gdsc *gpu_cc_sm6115_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm6115_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm6115_desc = {
.config = &gpu_cc_sm6115_regmap_config,
.clks = gpu_cc_sm6115_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks),
.resets = gpu_cc_sm6115_resets,
.num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets),
.gdscs = gpu_cc_sm6115_gdscs,
.num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs),
};
static const struct of_device_id gpu_cc_sm6115_match_table[] = {
{ .compatible = "qcom,sm6115-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table);
static int gpu_cc_sm6115_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap);
}
static struct platform_driver gpu_cc_sm6115_driver = {
.probe = gpu_cc_sm6115_probe,
.driver = {
.name = "sm6115-gpucc",
.of_match_table = gpu_cc_sm6115_match_table,
},
};
module_platform_driver(gpu_cc_sm6115_driver);
MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6125-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
};
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
P_GPU_CC_PLL0_2X_CLK,
P_GPU_CC_PLL0_OUT_AUX2,
P_GPU_CC_PLL1_OUT_AUX,
P_GPU_CC_PLL1_OUT_AUX2,
};
static struct pll_vco gpu_cc_pll_vco[] = {
{ 1000000000, 2000000000, 0 },
{ 500000000, 1000000000, 2 },
};
/* 1020MHz configuration */
static const struct alpha_pll_config gpu_pll0_config = {
.l = 0x35,
.config_ctl_val = 0x4001055b,
.alpha_hi = 0x20,
.alpha = 0x00,
.alpha_en_mask = BIT(24),
.vco_val = 0x0 << 20,
.vco_mask = 0x3 << 20,
.aux2_output_mask = BIT(2),
};
/* 930MHz configuration */
static const struct alpha_pll_config gpu_pll1_config = {
.l = 0x30,
.config_ctl_val = 0x4001055b,
.alpha_hi = 0x70,
.alpha = 0x00,
.alpha_en_mask = BIT(24),
.vco_val = 0x2 << 20,
.vco_mask = 0x3 << 20,
.aux2_output_mask = BIT(2),
};
static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = {
.offset = 0x0,
.vco_table = gpu_cc_pll_vco,
.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0_out_aux2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = {
.offset = 0x100,
.vco_table = gpu_cc_pll_vco,
.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.flags = SUPPORTS_DYNAMIC_UPDATE,
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1_out_aux2",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
},
};
static const struct parent_map gpu_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
{ P_GPU_CC_PLL1_OUT_AUX2, 4 },
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gpu_cc_pll0_out_aux2.clkr.hw },
{ .hw = &gpu_cc_pll1_out_aux2.clkr.hw },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_0,
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gmu_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0),
F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpu_cc_parent_map_1,
.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk_src",
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpu_cc_crc_ahb_clk = {
.halt_reg = 0x107c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x107c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_crc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_apb_clk = {
.halt_reg = 0x1088,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1088,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_apb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gx_gfx3d_clk.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.halt_reg = 0x5000,
.halt_check = BRANCH_VOTED,
.clkr = {
.enable_reg = 0x5000,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.pd = {
.name = "gpu_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct clk_regmap *gpu_cc_sm6125_clocks[] = {
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
[GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr,
[GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr,
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
};
static struct gdsc *gpucc_sm6125_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpu_cc_sm6125_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpu_cc_sm6125_desc = {
.config = &gpu_cc_sm6125_regmap_config,
.clks = gpu_cc_sm6125_clocks,
.num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks),
.gdscs = gpucc_sm6125_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs),
};
static const struct of_device_id gpu_cc_sm6125_match_table[] = {
{ .compatible = "qcom,sm6125-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table);
static int gpu_cc_sm6125_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config);
clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config);
/* Set recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
qcom_branch_set_wakeup(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_sleep(regmap, gpu_cc_cx_gmu_clk, 0xf);
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
}
static struct platform_driver gpu_cc_sm6125_driver = {
.probe = gpu_cc_sm6125_probe,
.driver = {
.name = "gpucc-sm6125",
.of_match_table = gpu_cc_sm6125_match_table,
},
};
module_platform_driver(gpu_cc_sm6125_driver);
MODULE_DESCRIPTION("QTI GPUCC SM6125 Driver");
MODULE_LICENSE("GPL");

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm6375-gpucc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_GCC_GPU_GPLL0_CLK_SRC,
DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
DT_GCC_GPU_SNOC_DVM_GFX_CLK,
};
enum {
P_BI_TCXO,
P_GCC_GPU_GPLL0_CLK_SRC,
P_GCC_GPU_GPLL0_DIV_CLK_SRC,
P_GPU_CC_PLL0_OUT_EVEN,
P_GPU_CC_PLL0_OUT_MAIN,
P_GPU_CC_PLL0_OUT_ODD,
P_GPU_CC_PLL1_OUT_EVEN,
P_GPU_CC_PLL1_OUT_MAIN,
P_GPU_CC_PLL1_OUT_ODD,
};
static struct pll_vco lucid_vco[] = {
{ 249600000, 2000000000, 0 },
};
/* 532MHz Configuration */
static const struct alpha_pll_config gpucc_pll0_config = {
.l = 0x1b,
.alpha = 0xb555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpucc_pll0 = {
.offset = 0x0,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpucc_pll0",
.parent_data = &(const struct clk_parent_data){
.index = P_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
/* 514MHz Configuration */
static const struct alpha_pll_config gpucc_pll1_config = {
.l = 0x1a,
.alpha = 0xc555,
.config_ctl_val = 0x20485699,
.config_ctl_hi_val = 0x00002261,
.config_ctl_hi1_val = 0x329a299c,
.user_ctl_val = 0x00000001,
.user_ctl_hi_val = 0x00000805,
.user_ctl_hi1_val = 0x00000000,
};
static struct clk_alpha_pll gpucc_pll1 = {
.offset = 0x100,
.vco_table = lucid_vco,
.num_vco = ARRAY_SIZE(lucid_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpucc_pll1",
.parent_data = &(const struct clk_parent_data){
.index = P_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_lucid_ops,
},
},
};
static const struct parent_map gpucc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
{ P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 },
};
static const struct clk_parent_data gpucc_parent_data_0[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpucc_pll0.clkr.hw },
{ .hw = &gpucc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
{ .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
};
static const struct parent_map gpucc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GPU_CC_PLL0_OUT_EVEN, 1 },
{ P_GPU_CC_PLL0_OUT_ODD, 2 },
{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
{ P_GPU_CC_PLL1_OUT_ODD, 4 },
{ P_GCC_GPU_GPLL0_CLK_SRC, 5 },
};
static const struct clk_parent_data gpucc_parent_data_1[] = {
{ .index = P_BI_TCXO },
{ .hw = &gpucc_pll0.clkr.hw },
{ .hw = &gpucc_pll0.clkr.hw },
{ .hw = &gpucc_pll1.clkr.hw },
{ .hw = &gpucc_pll1.clkr.hw },
{ .index = DT_GCC_GPU_GPLL0_CLK_SRC },
};
static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = {
F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0),
{ }
};
static struct clk_rcg2 gpucc_gmu_clk_src = {
.cmd_rcgr = 0x1120,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_0,
.freq_tbl = ftbl_gpucc_gmu_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpucc_gmu_clk_src",
.parent_data = gpucc_parent_data_0,
.num_parents = ARRAY_SIZE(gpucc_parent_data_0),
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = {
F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = {
.cmd_rcgr = 0x101c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gpucc_parent_map_1,
.freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_gfx3d_clk_src",
.parent_data = gpucc_parent_data_1,
.num_parents = ARRAY_SIZE(gpucc_parent_data_1),
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gpucc_ahb_clk = {
.halt_reg = 0x1078,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1078,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_ahb_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_gfx3d_clk = {
.halt_reg = 0x10a4,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a4,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_gfx3d_slv_clk = {
.halt_reg = 0x10a8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x10a8,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_gfx3d_slv_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_gmu_clk = {
.halt_reg = 0x1098,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1098,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cx_snoc_dvm_clk = {
.halt_reg = 0x108c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x108c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cx_snoc_dvm_clk",
.parent_data = &(const struct clk_parent_data){
.index = DT_GCC_GPU_SNOC_DVM_GFX_CLK,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cxo_aon_clk = {
.halt_reg = 0x1004,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1004,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_aon_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_cxo_clk = {
.halt_reg = 0x109c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x109c,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_cxo_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_gx_cxo_clk = {
.halt_reg = 0x1060,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1060,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_cxo_clk",
.flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_gx_gfx3d_clk = {
.halt_reg = 0x1054,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x1054,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_gfx3d_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gx_gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_gx_gmu_clk = {
.halt_reg = 0x1064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x1064,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_gx_gmu_clk",
.parent_hws = (const struct clk_hw*[]) {
&gpucc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gpucc_sleep_clk = {
.halt_reg = 0x1090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x1090,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpucc_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gpu_cx_gdsc = {
.gdscr = 0x106c,
.gds_hw_ctrl = 0x1540,
.clk_dis_wait_val = 8,
.pd = {
.name = "gpu_cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = VOTABLE,
};
static struct gdsc gpu_gx_gdsc = {
.gdscr = 0x100c,
.clamp_io_ctrl = 0x1508,
.resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR },
.reset_count = 3,
.pd = {
.name = "gpu_gx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = CLAMP_IO | SW_RESET | AON_RESET,
};
static struct clk_regmap *gpucc_sm6375_clocks[] = {
[GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr,
[GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr,
[GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr,
[GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr,
[GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr,
[GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr,
[GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr,
[GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr,
[GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr,
[GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr,
[GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr,
[GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr,
[GPU_CC_PLL0] = &gpucc_pll0.clkr,
[GPU_CC_PLL1] = &gpucc_pll1.clkr,
[GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr,
};
static const struct qcom_reset_map gpucc_sm6375_resets[] = {
[GPU_GX_BCR] = { 0x1008 },
[GPU_ACD_BCR] = { 0x1160 },
[GPU_GX_ACD_MISC_BCR] = { 0x8004 },
};
static struct gdsc *gpucc_sm6375_gdscs[] = {
[GPU_CX_GDSC] = &gpu_cx_gdsc,
[GPU_GX_GDSC] = &gpu_gx_gdsc,
};
static const struct regmap_config gpucc_sm6375_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x9000,
.fast_io = true,
};
static const struct qcom_cc_desc gpucc_sm6375_desc = {
.config = &gpucc_sm6375_regmap_config,
.clks = gpucc_sm6375_clocks,
.num_clks = ARRAY_SIZE(gpucc_sm6375_clocks),
.resets = gpucc_sm6375_resets,
.num_resets = ARRAY_SIZE(gpucc_sm6375_resets),
.gdscs = gpucc_sm6375_gdscs,
.num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs),
};
static const struct of_device_id gpucc_sm6375_match_table[] = {
{ .compatible = "qcom,sm6375-gpucc" },
{ }
};
MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table);
static int gpucc_sm6375_probe(struct platform_device *pdev)
{
struct regmap *regmap;
regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
}
static struct platform_driver gpucc_sm6375_driver = {
.probe = gpucc_sm6375_probe,
.driver = {
.name = "gpucc-sm6375",
.of_match_table = gpucc_sm6375_match_table,
},
};
module_platform_driver(gpucc_sm6375_driver);
MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver");
MODULE_LICENSE("GPL");

2
drivers/clk/qcom/lpassaudiocc-sc7280.c
View File

@ -696,6 +696,8 @@ static const struct qcom_cc_desc lpass_cc_sc7280_desc = {
.config = &lpass_audio_cc_sc7280_regmap_config,
.clks = lpass_cc_sc7280_clocks,
.num_clks = ARRAY_SIZE(lpass_cc_sc7280_clocks),
.gdscs = lpass_aon_cc_sc7280_gdscs,
.num_gdscs = ARRAY_SIZE(lpass_aon_cc_sc7280_gdscs),
};
static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {

14
drivers/clk/qcom/lpasscc-sc7280.c
View File

@ -121,14 +121,18 @@ static int lpass_cc_sc7280_probe(struct platform_device *pdev)
goto destroy_pm_clk;
}
lpass_regmap_config.name = "qdsp6ss";
desc = &lpass_qdsp6ss_sc7280_desc;
if (!of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
lpass_regmap_config.name = "qdsp6ss";
lpass_regmap_config.max_register = 0x3f;
desc = &lpass_qdsp6ss_sc7280_desc;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
goto destroy_pm_clk;
ret = qcom_cc_probe_by_index(pdev, 0, desc);
if (ret)
goto destroy_pm_clk;
}
lpass_regmap_config.name = "top_cc";
lpass_regmap_config.max_register = 0x4;
desc = &lpass_cc_top_sc7280_desc;
ret = qcom_cc_probe_by_index(pdev, 1, desc);

2
drivers/clk/rockchip/clk-rk3399.c
View File

@ -1263,7 +1263,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
RK3399_CLKGATE_CON(10), 7, GFLAGS),
COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
/* gic */

42
drivers/clk/rockchip/clk-rk3588.c
View File

@ -13,15 +13,25 @@
#include "clk.h"
/*
* GATE with additional linked clock. Downstream enables the linked clock
* (via runtime PM) whenever the gate is enabled. The downstream implementation
* does this via separate clock nodes for each of the linked gate clocks,
* which leaks parts of the clock tree into DT. It is unclear why this is
* actually needed and things work without it for simple use cases. Thus
* the linked clock is ignored for now.
* Recent Rockchip SoCs have a new hardware block called Native Interface
* Unit (NIU), which gates clocks to devices behind them. These effectively
* need two parent clocks.
*
* Downstream enables the linked clock via runtime PM whenever the gate is
* enabled. This implementation uses separate clock nodes for each of the
* linked gate clocks, which leaks parts of the clock tree into DT.
*
* The GATE_LINK macro instead takes the second parent via 'linkname', but
* ignores the information. Once the clock framework is ready to handle it, the
* information should be passed on here. But since these clocks are required to
* access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
* clocks critical until a better solution is available. This will waste some
* power, but avoids leaking implementation details into DT or hanging the
* system.
*/
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
GATE(_id, cname, pname, f, o, b, gf)
#define RK3588_LINKED_CLK CLK_IS_CRITICAL
#define RK3588_GRF_SOC_STATUS0 0x600
@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
RK3588_CLKGATE_CON(31), 0, GFLAGS),
COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(31), 1, GFLAGS),
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(42), 9, GFLAGS),
/* vdpu */
COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(44), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
RK3588_CLKGATE_CON(44), 2, GFLAGS),
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
RK3588_CLKGATE_CON(47), 1, GFLAGS),
GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 4, GFLAGS),
GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
RK3588_CLKGATE_CON(47), 5, GFLAGS),
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
RK3588_CLKGATE_CON(48), 6, GFLAGS),
/* vi */
COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(49), 0, GFLAGS),
COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(49), 1, GFLAGS),
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 0, GFLAGS),
COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 1, GFLAGS),
COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 2, GFLAGS),
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),

227
drivers/clk/samsung/clk-exynos-arm64.c
View File

@ -10,6 +10,9 @@
*/
#include <linux/clk.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include "clk-exynos-arm64.h"
@ -21,6 +24,19 @@
#define GATE_OFF_START 0x2000
#define GATE_OFF_END 0x2fff
struct exynos_arm64_cmu_data {
struct samsung_clk_reg_dump *clk_save;
unsigned int nr_clk_save;
const struct samsung_clk_reg_dump *clk_suspend;
unsigned int nr_clk_suspend;
struct clk *clk;
struct clk **pclks;
int nr_pclks;
struct samsung_clk_provider *ctx;
};
/**
* exynos_arm64_init_clocks - Set clocks initial configuration
* @np: CMU device tree node with "reg" property (CMU addr)
@ -56,6 +72,83 @@ static void __init exynos_arm64_init_clocks(struct device_node *np,
iounmap(reg_base);
}
/**
* exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
*
* @dev: Device object; may be NULL if this function is not being
* called from platform driver probe function
* @np: CMU device tree node
* @cmu: CMU data
*
* Keep CMU parent clock running (needed for CMU registers access).
*
* Return: 0 on success or a negative error code on failure.
*/
static int __init exynos_arm64_enable_bus_clk(struct device *dev,
struct device_node *np, const struct samsung_cmu_info *cmu)
{
struct clk *parent_clk;
if (!cmu->clk_name)
return 0;
if (dev) {
struct exynos_arm64_cmu_data *data;
parent_clk = clk_get(dev, cmu->clk_name);
data = dev_get_drvdata(dev);
if (data)
data->clk = parent_clk;
} else {
parent_clk = of_clk_get_by_name(np, cmu->clk_name);
}
if (IS_ERR(parent_clk))
return PTR_ERR(parent_clk);
return clk_prepare_enable(parent_clk);
}
static int __init exynos_arm64_cmu_prepare_pm(struct device *dev,
const struct samsung_cmu_info *cmu)
{
struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
int i;
data->clk_save = samsung_clk_alloc_reg_dump(cmu->clk_regs,
cmu->nr_clk_regs);
if (!data->clk_save)
return -ENOMEM;
data->nr_clk_save = cmu->nr_clk_regs;
data->clk_suspend = cmu->suspend_regs;
data->nr_clk_suspend = cmu->nr_suspend_regs;
data->nr_pclks = of_clk_get_parent_count(dev->of_node);
if (!data->nr_pclks)
return 0;
data->pclks = devm_kcalloc(dev, sizeof(struct clk *), data->nr_pclks,
GFP_KERNEL);
if (!data->pclks) {
kfree(data->clk_save);
return -ENOMEM;
}
for (i = 0; i < data->nr_pclks; i++) {
struct clk *clk = of_clk_get(dev->of_node, i);
if (IS_ERR(clk)) {
kfree(data->clk_save);
while (--i >= 0)
clk_put(data->pclks[i]);
return PTR_ERR(clk);
}
data->pclks[i] = clk;
}
return 0;
}
/**
* exynos_arm64_register_cmu - Register specified Exynos CMU domain
* @dev: Device object; may be NULL if this function is not being
@ -72,23 +165,127 @@ static void __init exynos_arm64_init_clocks(struct device_node *np,
void __init exynos_arm64_register_cmu(struct device *dev,
struct device_node *np, const struct samsung_cmu_info *cmu)
{
/* Keep CMU parent clock running (needed for CMU registers access) */
if (cmu->clk_name) {
struct clk *parent_clk;
int err;
if (dev)
parent_clk = clk_get(dev, cmu->clk_name);
else
parent_clk = of_clk_get_by_name(np, cmu->clk_name);
if (IS_ERR(parent_clk)) {
pr_err("%s: could not find bus clock %s; err = %ld\n",
__func__, cmu->clk_name, PTR_ERR(parent_clk));
} else {
clk_prepare_enable(parent_clk);
}
}
/*
* Try to boot even if the parent clock enablement fails, as it might be
* already enabled by bootloader.
*/
err = exynos_arm64_enable_bus_clk(dev, np, cmu);
if (err)
pr_err("%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, err);
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
samsung_cmu_register_one(np, cmu);
}
/**
* exynos_arm64_register_cmu_pm - Register Exynos CMU domain with PM support
*
* @pdev: Platform device object
* @set_manual: If true, set gate clocks to manual mode
*
* It's a version of exynos_arm64_register_cmu() with PM support. Should be
* called from probe function of platform driver.
*
* Return: 0 on success, or negative error code on error.
*/
int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
bool set_manual)
{
const struct samsung_cmu_info *cmu;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct exynos_arm64_cmu_data *data;
void __iomem *reg_base;
int ret;
cmu = of_device_get_match_data(dev);
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
platform_set_drvdata(pdev, data);
ret = exynos_arm64_cmu_prepare_pm(dev, cmu);
if (ret)
return ret;
/*
* Try to boot even if the parent clock enablement fails, as it might be
* already enabled by bootloader.
*/
ret = exynos_arm64_enable_bus_clk(dev, NULL, cmu);
if (ret)
dev_err(dev, "%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, ret);
if (set_manual)
exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
data->ctx = samsung_clk_init(dev, reg_base, cmu->nr_clk_ids);
/*
* Enable runtime PM here to allow the clock core using runtime PM
* for the registered clocks. Additionally, we increase the runtime
* PM usage count before registering the clocks, to prevent the
* clock core from runtime suspending the device.
*/
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
samsung_cmu_register_clocks(data->ctx, cmu);
samsung_clk_of_add_provider(dev->of_node, data->ctx);
pm_runtime_put_sync(dev);
return 0;
}
int exynos_arm64_cmu_suspend(struct device *dev)
{
struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
int i;
samsung_clk_save(data->ctx->reg_base, data->clk_save,
data->nr_clk_save);
for (i = 0; i < data->nr_pclks; i++)
clk_prepare_enable(data->pclks[i]);
/* For suspend some registers have to be set to certain values */
samsung_clk_restore(data->ctx->reg_base, data->clk_suspend,
data->nr_clk_suspend);
for (i = 0; i < data->nr_pclks; i++)
clk_disable_unprepare(data->pclks[i]);
clk_disable_unprepare(data->clk);
return 0;
}
int exynos_arm64_cmu_resume(struct device *dev)
{
struct exynos_arm64_cmu_data *data = dev_get_drvdata(dev);
int i;
clk_prepare_enable(data->clk);
for (i = 0; i < data->nr_pclks; i++)
clk_prepare_enable(data->pclks[i]);
samsung_clk_restore(data->ctx->reg_base, data->clk_save,
data->nr_clk_save);
for (i = 0; i < data->nr_pclks; i++)
clk_disable_unprepare(data->pclks[i]);
return 0;
}

3
drivers/clk/samsung/clk-exynos-arm64.h
View File

@ -16,5 +16,8 @@
void exynos_arm64_register_cmu(struct device *dev,
struct device_node *np, const struct samsung_cmu_info *cmu);
int exynos_arm64_register_cmu_pm(struct platform_device *pdev, bool set_manual);
int exynos_arm64_cmu_suspend(struct device *dev);
int exynos_arm64_cmu_resume(struct device *dev);
#endif /* __CLK_EXYNOS_ARM64_H */

6
drivers/clk/samsung/clk-exynos-audss.c
View File

@ -268,7 +268,7 @@ unregister:
return ret;
}
static int exynos_audss_clk_remove(struct platform_device *pdev)
static void exynos_audss_clk_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
@ -277,8 +277,6 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
if (!IS_ERR(epll))
clk_disable_unprepare(epll);
return 0;
}
static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
@ -295,7 +293,7 @@ static struct platform_driver exynos_audss_clk_driver = {
.pm = &exynos_audss_clk_pm_ops,
},
.probe = exynos_audss_clk_probe,
.remove = exynos_audss_clk_remove,
.remove_new = exynos_audss_clk_remove,
};
module_platform_driver(exynos_audss_clk_driver);

6
drivers/clk/samsung/clk-exynos-clkout.c
View File

@ -196,15 +196,13 @@ clks_put:
return ret;
}
static int exynos_clkout_remove(struct platform_device *pdev)
static void exynos_clkout_remove(struct platform_device *pdev)
{
struct exynos_clkout *clkout = platform_get_drvdata(pdev);
of_clk_del_provider(clkout->np);
clk_hw_unregister(clkout->data.hws[0]);
iounmap(clkout->reg);
return 0;
}
static int __maybe_unused exynos_clkout_suspend(struct device *dev)
@ -235,7 +233,7 @@ static struct platform_driver exynos_clkout_driver = {
.pm = &exynos_clkout_pm_ops,
},
.probe = exynos_clkout_probe,
.remove = exynos_clkout_remove,
.remove_new = exynos_clkout_remove,
};
module_platform_driver(exynos_clkout_driver);

6
drivers/clk/samsung/clk-exynos4.c
View File

@ -1251,7 +1251,7 @@ static void __init exynos4_clk_init(struct device_node *np,
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
@ -1276,7 +1276,7 @@ static void __init exynos4_clk_init(struct device_node *np,
exynos4210_vpll_rates;
samsung_clk_register_pll(ctx, exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
ARRAY_SIZE(exynos4210_plls));
} else {
if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) {
exynos4x12_plls[apll].rate_table =
@ -1288,7 +1288,7 @@ static void __init exynos4_clk_init(struct device_node *np,
}
samsung_clk_register_pll(ctx, exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);
ARRAY_SIZE(exynos4x12_plls));
}
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,

3
drivers/clk/samsung/clk-exynos4412-isp.c
View File

@ -121,8 +121,7 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
if (!exynos4x12_save_isp)
return -ENOMEM;
ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS);
ctx->dev = dev;
ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS);
platform_set_drvdata(pdev, ctx);

5
drivers/clk/samsung/clk-exynos5250.c
View File

@ -797,7 +797,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
panic("%s: unable to determine soc\n", __func__);
}
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
@ -815,8 +815,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
samsung_clk_register_pll(ctx, exynos5250_plls,
ARRAY_SIZE(exynos5250_plls),
reg_base);
ARRAY_SIZE(exynos5250_plls));
samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
ARRAY_SIZE(exynos5250_fixed_rate_clks));
samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,

5
drivers/clk/samsung/clk-exynos5420.c
View File

@ -1587,7 +1587,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_soc = soc;
ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
@ -1606,8 +1606,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
else
exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
reg_base);
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls));
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
ARRAY_SIZE(exynos5x_fixed_rate_clks));
samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,

157
drivers/clk/samsung/clk-exynos5433.c
View File

@ -10,7 +10,6 @@
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
@ -19,6 +18,7 @@
#include "clk.h"
#include "clk-cpu.h"
#include "clk-exynos-arm64.h"
#include "clk-pll.h"
/*
@ -5478,160 +5478,9 @@ static const struct samsung_cmu_info imem_cmu_info __initconst = {
.clk_name = "aclk_imem_200",
};
struct exynos5433_cmu_data {
struct samsung_clk_reg_dump *clk_save;
unsigned int nr_clk_save;
const struct samsung_clk_reg_dump *clk_suspend;
unsigned int nr_clk_suspend;
struct clk *clk;
struct clk **pclks;
int nr_pclks;
/* must be the last entry */
struct samsung_clk_provider ctx;
};
static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
{
struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
int i;
samsung_clk_save(data->ctx.reg_base, data->clk_save,
data->nr_clk_save);
for (i = 0; i < data->nr_pclks; i++)
clk_prepare_enable(data->pclks[i]);
/* for suspend some registers have to be set to certain values */
samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
data->nr_clk_suspend);
for (i = 0; i < data->nr_pclks; i++)
clk_disable_unprepare(data->pclks[i]);
clk_disable_unprepare(data->clk);
return 0;
}
static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
{
struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
int i;
clk_prepare_enable(data->clk);
for (i = 0; i < data->nr_pclks; i++)
clk_prepare_enable(data->pclks[i]);
samsung_clk_restore(data->ctx.reg_base, data->clk_save,
data->nr_clk_save);
for (i = 0; i < data->nr_pclks; i++)
clk_disable_unprepare(data->pclks[i]);
return 0;
}
static int __init exynos5433_cmu_probe(struct platform_device *pdev)
{
const struct samsung_cmu_info *info;
struct exynos5433_cmu_data *data;
struct samsung_clk_provider *ctx;
struct device *dev = &pdev->dev;
void __iomem *reg_base;
int i;
info = of_device_get_match_data(dev);
data = devm_kzalloc(dev,
struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
GFP_KERNEL);
if (!data)
return -ENOMEM;
ctx = &data->ctx;
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
return PTR_ERR(reg_base);
for (i = 0; i < info->nr_clk_ids; ++i)
ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
ctx->clk_data.num = info->nr_clk_ids;
ctx->reg_base = reg_base;
ctx->dev = dev;
spin_lock_init(&ctx->lock);
data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
info->nr_clk_regs);
if (!data->clk_save)
return -ENOMEM;
data->nr_clk_save = info->nr_clk_regs;
data->clk_suspend = info->suspend_regs;
data->nr_clk_suspend = info->nr_suspend_regs;
data->nr_pclks = of_clk_get_parent_count(dev->of_node);
if (data->nr_pclks > 0) {
data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
data->nr_pclks, GFP_KERNEL);
if (!data->pclks) {
kfree(data->clk_save);
return -ENOMEM;
}
for (i = 0; i < data->nr_pclks; i++) {
struct clk *clk = of_clk_get(dev->of_node, i);
if (IS_ERR(clk)) {
kfree(data->clk_save);
while (--i >= 0)
clk_put(data->pclks[i]);
return PTR_ERR(clk);
}
data->pclks[i] = clk;
}
}
if (info->clk_name)
data->clk = clk_get(dev, info->clk_name);
clk_prepare_enable(data->clk);
platform_set_drvdata(pdev, data);
/*
* Enable runtime PM here to allow the clock core using runtime PM
* for the registered clocks. Additionally, we increase the runtime
* PM usage count before registering the clocks, to prevent the
* clock core from runtime suspending the device.
*/
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
if (info->pll_clks)
samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
reg_base);
if (info->mux_clks)
samsung_clk_register_mux(ctx, info->mux_clks,
info->nr_mux_clks);
if (info->div_clks)
samsung_clk_register_div(ctx, info->div_clks,
info->nr_div_clks);
if (info->gate_clks)
samsung_clk_register_gate(ctx, info->gate_clks,
info->nr_gate_clks);
if (info->fixed_clks)
samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
info->nr_fixed_clks);
if (info->fixed_factor_clks)
samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
info->nr_fixed_factor_clks);
samsung_clk_of_add_provider(dev->of_node, ctx);
pm_runtime_put_sync(dev);
return 0;
return exynos_arm64_register_cmu_pm(pdev, false);
}
static const struct of_device_id exynos5433_cmu_of_match[] = {
@ -5679,7 +5528,7 @@ static const struct of_device_id exynos5433_cmu_of_match[] = {
};
static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
SET_RUNTIME_PM_OPS(exynos_arm64_cmu_suspend, exynos_arm64_cmu_resume,
NULL)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)

141
drivers/clk/samsung/clk-exynos850.c
View File

@ -36,6 +36,7 @@
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
@ -57,6 +58,7 @@
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
@ -84,6 +86,7 @@
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
CLK_CON_MUX_MUX_CLKCMU_DPU,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
CLK_CON_DIV_CLKCMU_CORE_SSS,
CLK_CON_DIV_CLKCMU_DPU,
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
CLK_CON_DIV_CLKCMU_HSI_BUS,
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
CLK_CON_GAT_GATE_CLKCMU_DPU,
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
"oscclk", "oscclk" };
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */
PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
/* G3D */
MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
/* HSI */
MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1),
@ -357,6 +370,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
/* G3D */
DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch",
CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
/* HSI */
DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus",
CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4),
@ -417,6 +434,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
/* G3D */
GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch",
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0),
/* HSI */
GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0),
@ -591,7 +612,7 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
0),
GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
};
@ -653,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020
#define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
@ -708,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK,
CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
@ -827,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = {
};
static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk",
"dout_aud_busd",
CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
@ -992,6 +1018,102 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
.clk_name = "gout_clkcmu_cmgp_bus",
};
/* ---- CMU_G3D ------------------------------------------------------------- */
/* Register Offset definitions for CMU_G3D (0x11400000) */
#define PLL_LOCKTIME_PLL_G3D 0x0000
#define PLL_CON0_PLL_G3D 0x0100
#define PLL_CON3_PLL_G3D 0x010c
#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600
#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000
#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804
#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000
#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004
#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c
#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010
#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024
#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028
#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c
static const unsigned long g3d_clk_regs[] __initconst = {
PLL_LOCKTIME_PLL_G3D,
PLL_CON0_PLL_G3D,
PLL_CON3_PLL_G3D,
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER,
CLK_CON_MUX_MUX_CLK_G3D_BUSD,
CLK_CON_DIV_DIV_CLK_G3D_BUSP,
CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK,
CLK_CON_GAT_CLK_G3D_GPU_CLK,
CLK_CON_GAT_GOUT_G3D_TZPC_PCLK,
CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK,
CLK_CON_GAT_GOUT_G3D_BUSD_CLK,
CLK_CON_GAT_GOUT_G3D_BUSP_CLK,
CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK,
};
/* List of parent clocks for Muxes in CMU_G3D */
PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" };
PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" };
PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" };
/*
* Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set
* for that PLL by default, so set_rate operation would fail.
*/
static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
};
static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
PLL_CON0_PLL_G3D, 4, 1),
MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user",
mout_g3d_switch_user_p,
PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1),
MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p,
CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1),
};
static const struct samsung_div_clock g3d_div_clks[] __initconst = {
DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd",
CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3),
};
static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk",
"dout_g3d_busp",
CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd",
CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp",
CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk",
"mout_g3d_busd",
CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd",
CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp",
CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0),
GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp",
CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0),
};
static const struct samsung_cmu_info g3d_cmu_info __initconst = {
.pll_clks = g3d_pll_clks,
.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
.mux_clks = g3d_mux_clks,
.nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
.div_clks = g3d_div_clks,
.nr_div_clks = ARRAY_SIZE(g3d_div_clks),
.gate_clks = g3d_gate_clks,
.nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
.nr_clk_ids = G3D_NR_CLK,
.clk_regs = g3d_clk_regs,
.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
.clk_name = "dout_g3d_switch",
};
/* ---- CMU_HSI ------------------------------------------------------------- */
/* Register Offset definitions for CMU_HSI (0x13400000) */
@ -999,12 +1121,15 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
#define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610
#define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620
#define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000
#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000
#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008
#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c
#define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010
#define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018
#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024
#define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028
#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c
#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030
#define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038
#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c
#define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040
@ -1014,12 +1139,15 @@ static const unsigned long hsi_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER,
PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER,
CLK_CON_MUX_MUX_CLK_HSI_RTC,
CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK,
CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV,
CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50,
CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26,
CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK,
CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK,
CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN,
CLK_CON_GAT_GOUT_HSI_PPMU_ACLK,
CLK_CON_GAT_GOUT_HSI_PPMU_PCLK,
CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK,
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20,
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
@ -1045,6 +1173,10 @@ static const struct samsung_mux_clock hsi_mux_clks[] __initconst = {
};
static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
/* TODO: Should be enabled in corresponding driver */
GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk",
"mout_hsi_bus_user",
CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc",
CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0),
GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user",
@ -1059,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = {
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
"mout_hsi_mmc_card_user",
CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0),
GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0),
GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0),
GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
"mout_hsi_bus_user",
CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0),
@ -1700,6 +1836,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
}, {
.compatible = "samsung,exynos850-cmu-cmgp",
.data = &cmgp_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-g3d",
.data = &g3d_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-hsi",
.data = &hsi_cmu_info,

12
drivers/clk/samsung/clk-pll.c
View File

@ -1259,8 +1259,7 @@ static const struct clk_ops samsung_pll2650xx_clk_min_ops = {
};
static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
const struct samsung_pll_clock *pll_clk,
void __iomem *base)
const struct samsung_pll_clock *pll_clk)
{
struct samsung_clk_pll *pll;
struct clk_init_data init;
@ -1315,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
init.ops = &samsung_pll35xx_clk_ops;
break;
case pll_1417x:
case pll_0818x:
case pll_0822x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
@ -1395,8 +1395,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
pll->hw.init = &init;
pll->type = pll_clk->type;
pll->lock_reg = base + pll_clk->lock_offset;
pll->con_reg = base + pll_clk->con_offset;
pll->lock_reg = ctx->reg_base + pll_clk->lock_offset;
pll->con_reg = ctx->reg_base + pll_clk->con_offset;
ret = clk_hw_register(ctx->dev, &pll->hw);
if (ret) {
@ -1412,10 +1412,10 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
const struct samsung_pll_clock *pll_list,
unsigned int nr_pll, void __iomem *base)
unsigned int nr_pll)
{
int cnt;
for (cnt = 0; cnt < nr_pll; cnt++)
_samsung_clk_register_pll(ctx, &pll_list[cnt], base);
_samsung_clk_register_pll(ctx, &pll_list[cnt]);
}

1
drivers/clk/samsung/clk-pll.h
View File

@ -34,6 +34,7 @@ enum samsung_pll_type {
pll_1451x,
pll_1452x,
pll_1460x,
pll_0818x,
pll_0822x,
pll_0831x,
pll_142xx,

4
drivers/clk/samsung/clk-s3c64xx.c
View File

@ -405,7 +405,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
panic("%s: failed to map registers\n", __func__);
}
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
ctx = samsung_clk_init(NULL, reg_base, NR_CLKS);
hws = ctx->clk_data.hws;
/* Register external clocks. */
@ -414,7 +414,7 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
/* Register PLLs. */
samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
ARRAY_SIZE(s3c64xx_pll_clks), reg_base);
ARRAY_SIZE(s3c64xx_pll_clks));
/* Register common internal clocks. */
samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,

6
drivers/clk/samsung/clk-s5pv210.c
View File

@ -743,7 +743,7 @@ static void __init __s5pv210_clk_init(struct device_node *np,
struct samsung_clk_provider *ctx;
struct clk_hw **hws;
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
ctx = samsung_clk_init(NULL, reg_base, NR_CLKS);
hws = ctx->clk_data.hws;
samsung_clk_register_mux(ctx, early_mux_clks,
@ -753,7 +753,7 @@ static void __init __s5pv210_clk_init(struct device_node *np,
samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks,
ARRAY_SIZE(s5p6442_frate_clks));
samsung_clk_register_pll(ctx, s5p6442_pll_clks,
ARRAY_SIZE(s5p6442_pll_clks), reg_base);
ARRAY_SIZE(s5p6442_pll_clks));
samsung_clk_register_mux(ctx, s5p6442_mux_clks,
ARRAY_SIZE(s5p6442_mux_clks));
samsung_clk_register_div(ctx, s5p6442_div_clks,
@ -764,7 +764,7 @@ static void __init __s5pv210_clk_init(struct device_node *np,
samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks,
ARRAY_SIZE(s5pv210_frate_clks));
samsung_clk_register_pll(ctx, s5pv210_pll_clks,
ARRAY_SIZE(s5pv210_pll_clks), reg_base);
ARRAY_SIZE(s5pv210_pll_clks));
samsung_clk_register_mux(ctx, s5pv210_mux_clks,
ARRAY_SIZE(s5pv210_mux_clks));
samsung_clk_register_div(ctx, s5pv210_div_clks,

64
drivers/clk/samsung/clk.c
View File

@ -53,8 +53,18 @@ struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
return rd;
}
/* setup the essentials required to support clock lookup using ccf */
struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
/**
* samsung_clk_init() - Create and initialize a clock provider object
* @dev: CMU device to enable runtime PM, or NULL if RPM is not needed
* @base: Start address (mapped) of CMU registers
* @nr_clks: Total clock count to allocate in clock provider object
*
* Setup the essentials required to support clock lookup using Common Clock
* Framework.
*
* Return: Allocated and initialized clock provider object.
*/
struct samsung_clk_provider * __init samsung_clk_init(struct device *dev,
void __iomem *base, unsigned long nr_clks)
{
struct samsung_clk_provider *ctx;
@ -67,6 +77,7 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
for (i = 0; i < nr_clks; ++i)
ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
ctx->dev = dev;
ctx->reg_base = base;
ctx->clk_data.num = nr_clks;
spin_lock_init(&ctx->lock);
@ -324,6 +335,33 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base,
}
#endif
/**
* samsung_cmu_register_clocks() - Register all clocks provided in CMU object
* @ctx: Clock provider object
* @cmu: CMU object with clocks to register
*/
void __init samsung_cmu_register_clocks(struct samsung_clk_provider *ctx,
const struct samsung_cmu_info *cmu)
{
if (cmu->pll_clks)
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks);
if (cmu->mux_clks)
samsung_clk_register_mux(ctx, cmu->mux_clks, cmu->nr_mux_clks);
if (cmu->div_clks)
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
if (cmu->gate_clks)
samsung_clk_register_gate(ctx, cmu->gate_clks,
cmu->nr_gate_clks);
if (cmu->fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
cmu->nr_fixed_clks);
if (cmu->fixed_factor_clks)
samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
cmu->nr_fixed_factor_clks);
if (cmu->cpu_clks)
samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);
}
/*
* Common function which registers plls, muxes, dividers and gates
* for each CMU. It also add CMU register list to register cache.
@ -341,31 +379,13 @@ struct samsung_clk_provider * __init samsung_cmu_register_one(
return NULL;
}
ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
ctx = samsung_clk_init(NULL, reg_base, cmu->nr_clk_ids);
samsung_cmu_register_clocks(ctx, cmu);
if (cmu->pll_clks)
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
reg_base);
if (cmu->mux_clks)
samsung_clk_register_mux(ctx, cmu->mux_clks,
cmu->nr_mux_clks);
if (cmu->div_clks)
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
if (cmu->gate_clks)
samsung_clk_register_gate(ctx, cmu->gate_clks,
cmu->nr_gate_clks);
if (cmu->fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
cmu->nr_fixed_clks);
if (cmu->fixed_factor_clks)
samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
cmu->nr_fixed_factor_clks);
if (cmu->clk_regs)
samsung_clk_extended_sleep_init(reg_base,
cmu->clk_regs, cmu->nr_clk_regs,
cmu->suspend_regs, cmu->nr_suspend_regs);
if (cmu->cpu_clks)
samsung_clk_register_cpu(ctx, cmu->cpu_clks, cmu->nr_cpu_clks);
samsung_clk_of_add_provider(np, ctx);

10
drivers/clk/samsung/clk.h
View File

@ -16,6 +16,7 @@
/**
* struct samsung_clk_provider: information about clock provider
* @reg_base: virtual address for the register base.
* @dev: clock provider device needed for runtime PM.
* @lock: maintains exclusion between callbacks for a given clock-provider.
* @clk_data: holds clock related data like clk_hw* and number of clocks.
*/
@ -337,9 +338,8 @@ struct samsung_cmu_info {
const char *clk_name;
};
struct samsung_clk_provider * samsung_clk_init(
struct device_node *np, void __iomem *base,
unsigned long nr_clks);
struct samsung_clk_provider *samsung_clk_init(struct device *dev,
void __iomem *base, unsigned long nr_clks);
void samsung_clk_of_add_provider(struct device_node *np,
struct samsung_clk_provider *ctx);
void samsung_clk_of_register_fixed_ext(
@ -373,10 +373,12 @@ void samsung_clk_register_gate(struct samsung_clk_provider *ctx,
unsigned int nr_clk);
void samsung_clk_register_pll(struct samsung_clk_provider *ctx,
const struct samsung_pll_clock *pll_list,
unsigned int nr_clk, void __iomem *base);
unsigned int nr_clk);
void samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
const struct samsung_cpu_clock *list, unsigned int nr_clk);
void samsung_cmu_register_clocks(struct samsung_clk_provider *ctx,
const struct samsung_cmu_info *cmu);
struct samsung_clk_provider *samsung_cmu_register_one(
struct device_node *,
const struct samsung_cmu_info *);

28
include/dt-bindings/clock/exynos850.h
View File

@ -85,7 +85,10 @@
#define CLK_DOUT_MFCMSCL_M2M 73
#define CLK_DOUT_MFCMSCL_MCSC 74
#define CLK_DOUT_MFCMSCL_JPEG 75
#define TOP_NR_CLK 76
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
#define TOP_NR_CLK 79
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@ -175,7 +178,8 @@
#define IOCLK_AUDIOCDCLK5 58
#define IOCLK_AUDIOCDCLK6 59
#define TICK_USB 60
#define AUD_NR_CLK 61
#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
#define AUD_NR_CLK 62
/* CMU_CMGP */
#define CLK_RCO_CMGP 1
@ -195,6 +199,21 @@
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
#define CMGP_NR_CLK 16
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_G3D_PLL 2
#define CLK_MOUT_G3D_SWITCH_USER 3
#define CLK_MOUT_G3D_BUSD 4
#define CLK_DOUT_G3D_BUSP 5
#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
#define CLK_GOUT_G3D_GPU_CLK 7
#define CLK_GOUT_G3D_TZPC_PCLK 8
#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
#define CLK_GOUT_G3D_BUSD_CLK 10
#define CLK_GOUT_G3D_BUSP_CLK 11
#define CLK_GOUT_G3D_SYSREG_PCLK 12
#define G3D_NR_CLK 13
/* CMU_HSI */
#define CLK_MOUT_HSI_BUS_USER 1
#define CLK_MOUT_HSI_MMC_CARD_USER 2
@ -209,7 +228,10 @@
#define CLK_GOUT_MMC_CARD_ACLK 11
#define CLK_GOUT_MMC_CARD_SDCLKIN 12
#define CLK_GOUT_SYSREG_HSI_PCLK 13
#define HSI_NR_CLK 14
#define CLK_GOUT_HSI_PPMU_ACLK 14
#define CLK_GOUT_HSI_PPMU_PCLK 15
#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
#define HSI_NR_CLK 17
/* CMU_IS */
#define CLK_MOUT_IS_BUS_USER 1

4
include/dt-bindings/clock/qcom,dispcc-qcm2290.h
View File

@ -29,6 +29,10 @@
#define DISP_CC_XO_CLK 19
#define DISP_CC_XO_CLK_SRC 20
/* GDSCs */
#define MDSS_GDSC 0
/* Resets */
#define DISP_CC_MDSS_CORE_BCR 0
#endif

190
include/dt-bindings/clock/qcom,gcc-msm8917.h Normal file
View File

@ -0,0 +1,190 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8917_H
#define _DT_BINDINGS_CLK_MSM_GCC_8917_H
/* Clocks */
#define APSS_AHB_CLK_SRC 0
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 1
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 2
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 3
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 4
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 5
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 6
#define BLSP1_UART1_APPS_CLK_SRC 7
#define BLSP1_UART2_APPS_CLK_SRC 8
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 9
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 10
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 11
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 12
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 13
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 14
#define BLSP2_UART1_APPS_CLK_SRC 15
#define BLSP2_UART2_APPS_CLK_SRC 16
#define BYTE0_CLK_SRC 17
#define CAMSS_GP0_CLK_SRC 18
#define CAMSS_GP1_CLK_SRC 19
#define CAMSS_TOP_AHB_CLK_SRC 20
#define CCI_CLK_SRC 21
#define CPP_CLK_SRC 22
#define CRYPTO_CLK_SRC 23
#define CSI0PHYTIMER_CLK_SRC 24
#define CSI0_CLK_SRC 25
#define CSI1PHYTIMER_CLK_SRC 26
#define CSI1_CLK_SRC 27
#define CSI2_CLK_SRC 28
#define ESC0_CLK_SRC 29
#define GCC_APSS_TCU_CLK 30
#define GCC_BIMC_GFX_CLK 31
#define GCC_BIMC_GPU_CLK 32
#define GCC_BLSP1_AHB_CLK 33
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 34
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 35
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 36
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 37
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 38
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 39
#define GCC_BLSP1_UART1_APPS_CLK 40
#define GCC_BLSP1_UART2_APPS_CLK 41
#define GCC_BLSP2_AHB_CLK 42
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 43
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 44
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 45
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 46
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 47
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 48
#define GCC_BLSP2_UART1_APPS_CLK 49
#define GCC_BLSP2_UART2_APPS_CLK 50
#define GCC_BOOT_ROM_AHB_CLK 51
#define GCC_CAMSS_AHB_CLK 52
#define GCC_CAMSS_CCI_AHB_CLK 53
#define GCC_CAMSS_CCI_CLK 54
#define GCC_CAMSS_CPP_AHB_CLK 55
#define GCC_CAMSS_CPP_CLK 56
#define GCC_CAMSS_CSI0PHYTIMER_CLK 57
#define GCC_CAMSS_CSI0PHY_CLK 58
#define GCC_CAMSS_CSI0PIX_CLK 59
#define GCC_CAMSS_CSI0RDI_CLK 60
#define GCC_CAMSS_CSI0_AHB_CLK 61
#define GCC_CAMSS_CSI0_CLK 62
#define GCC_CAMSS_CSI1PHYTIMER_CLK 63
#define GCC_CAMSS_CSI1PHY_CLK 64
#define GCC_CAMSS_CSI1PIX_CLK 65
#define GCC_CAMSS_CSI1RDI_CLK 66
#define GCC_CAMSS_CSI1_AHB_CLK 67
#define GCC_CAMSS_CSI1_CLK 68
#define GCC_CAMSS_CSI2PHY_CLK 69
#define GCC_CAMSS_CSI2PIX_CLK 70
#define GCC_CAMSS_CSI2RDI_CLK 71
#define GCC_CAMSS_CSI2_AHB_CLK 72
#define GCC_CAMSS_CSI2_CLK 73
#define GCC_CAMSS_CSI_VFE0_CLK 74
#define GCC_CAMSS_CSI_VFE1_CLK 75
#define GCC_CAMSS_GP0_CLK 76
#define GCC_CAMSS_GP1_CLK 77
#define GCC_CAMSS_ISPIF_AHB_CLK 78
#define GCC_CAMSS_JPEG0_CLK 79
#define GCC_CAMSS_JPEG_AHB_CLK 80
#define GCC_CAMSS_JPEG_AXI_CLK 81
#define GCC_CAMSS_MCLK0_CLK 82
#define GCC_CAMSS_MCLK1_CLK 83
#define GCC_CAMSS_MCLK2_CLK 84
#define GCC_CAMSS_MICRO_AHB_CLK 85
#define GCC_CAMSS_TOP_AHB_CLK 86
#define GCC_CAMSS_VFE0_AHB_CLK 87
#define GCC_CAMSS_VFE0_AXI_CLK 88
#define GCC_CAMSS_VFE0_CLK 89
#define GCC_CAMSS_VFE1_AHB_CLK 90
#define GCC_CAMSS_VFE1_AXI_CLK 91
#define GCC_CAMSS_VFE1_CLK 92
#define GCC_CPP_TBU_CLK 93
#define GCC_CRYPTO_AHB_CLK 94
#define GCC_CRYPTO_AXI_CLK 95
#define GCC_CRYPTO_CLK 96
#define GCC_DCC_CLK 97
#define GCC_GFX_TBU_CLK 98
#define GCC_GFX_TCU_CLK 99
#define GCC_GP1_CLK 100
#define GCC_GP2_CLK 101
#define GCC_GP3_CLK 102
#define GCC_GTCU_AHB_CLK 103
#define GCC_JPEG_TBU_CLK 104
#define GCC_MDP_TBU_CLK 105
#define GCC_MDSS_AHB_CLK 106
#define GCC_MDSS_AXI_CLK 107
#define GCC_MDSS_BYTE0_CLK 108
#define GCC_MDSS_ESC0_CLK 109
#define GCC_MDSS_MDP_CLK 110
#define GCC_MDSS_PCLK0_CLK 111
#define GCC_MDSS_VSYNC_CLK 112
#define GCC_MSS_CFG_AHB_CLK 113
#define GCC_MSS_Q6_BIMC_AXI_CLK 114
#define GCC_OXILI_AHB_CLK 115
#define GCC_OXILI_GFX3D_CLK 116
#define GCC_PDM2_CLK 117
#define GCC_PDM_AHB_CLK 118
#define GCC_PRNG_AHB_CLK 119
#define GCC_QDSS_DAP_CLK 120
#define GCC_SDCC1_AHB_CLK 121
#define GCC_SDCC1_APPS_CLK 122
#define GCC_SDCC1_ICE_CORE_CLK 123
#define GCC_SDCC2_AHB_CLK 124
#define GCC_SDCC2_APPS_CLK 125
#define GCC_SMMU_CFG_CLK 126
#define GCC_USB2A_PHY_SLEEP_CLK 127
#define GCC_USB_HS_AHB_CLK 128
#define GCC_USB_HS_PHY_CFG_AHB_CLK 129
#define GCC_USB_HS_SYSTEM_CLK 130
#define GCC_VENUS0_AHB_CLK 131
#define GCC_VENUS0_AXI_CLK 132
#define GCC_VENUS0_CORE0_VCODEC0_CLK 133
#define GCC_VENUS0_VCODEC0_CLK 134
#define GCC_VENUS_TBU_CLK 135
#define GCC_VFE1_TBU_CLK 136
#define GCC_VFE_TBU_CLK 137
#define GFX3D_CLK_SRC 138
#define GP1_CLK_SRC 139
#define GP2_CLK_SRC 140
#define GP3_CLK_SRC 141
#define GPLL0 142
#define GPLL0_EARLY 143
#define GPLL3 144
#define GPLL3_EARLY 145
#define GPLL4 146
#define GPLL4_EARLY 147
#define GPLL6 148
#define GPLL6_EARLY 149
#define JPEG0_CLK_SRC 150
#define MCLK0_CLK_SRC 151
#define MCLK1_CLK_SRC 152
#define MCLK2_CLK_SRC 153
#define MDP_CLK_SRC 154
#define PCLK0_CLK_SRC 155
#define PDM2_CLK_SRC 156
#define SDCC1_APPS_CLK_SRC 157
#define SDCC1_ICE_CORE_CLK_SRC 158
#define SDCC2_APPS_CLK_SRC 159
#define USB_HS_SYSTEM_CLK_SRC 160
#define VCODEC0_CLK_SRC 161
#define VFE0_CLK_SRC 162
#define VFE1_CLK_SRC 163
#define VSYNC_CLK_SRC 164
/* GCC block resets */
#define GCC_CAMSS_MICRO_BCR 0
#define GCC_MSS_BCR 1
#define GCC_QUSB2_PHY_BCR 2
#define GCC_USB_HS_BCR 3
#define GCC_USB2_HS_PHY_ONLY_BCR 4
/* GDSCs */
#define CPP_GDSC 0
#define JPEG_GDSC 1
#define MDSS_GDSC 2
#define OXILI_GX_GDSC 3
#define VENUS_CORE0_GDSC 4
#define VENUS_GDSC 5
#define VFE0_GDSC 6
#define VFE1_GDSC 7
#endif

2
include/dt-bindings/clock/qcom,gcc-sc8280xp.h
View File

@ -492,5 +492,7 @@
#define USB30_MP_GDSC 9
#define USB30_PRIM_GDSC 10
#define USB30_SEC_GDSC 11
#define EMAC_0_GDSC 12
#define EMAC_1_GDSC 13
#endif

356
include/dt-bindings/clock/qcom,ipq5332-gcc.h Normal file
View File

@ -0,0 +1,356 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
#define GPLL0_MAIN 0
#define GPLL0 1
#define GPLL2_MAIN 2
#define GPLL2 3
#define GPLL4_MAIN 4
#define GPLL4 5
#define GCC_ADSS_PWM_CLK 6
#define GCC_ADSS_PWM_CLK_SRC 7
#define GCC_AHB_CLK 8
#define GCC_APSS_AXI_CLK_SRC 9
#define GCC_BLSP1_AHB_CLK 10
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19
#define GCC_BLSP1_SLEEP_CLK 20
#define GCC_BLSP1_UART1_APPS_CLK 21
#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
#define GCC_BLSP1_UART2_APPS_CLK 23
#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
#define GCC_BLSP1_UART3_APPS_CLK 25
#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
#define GCC_CE_AHB_CLK 27
#define GCC_CE_AXI_CLK 28
#define GCC_CE_PCNOC_AHB_CLK 29
#define GCC_CMN_12GPLL_AHB_CLK 30
#define GCC_CMN_12GPLL_APU_CLK 31
#define GCC_CMN_12GPLL_SYS_CLK 32
#define GCC_GP1_CLK 33
#define GCC_GP1_CLK_SRC 34
#define GCC_GP2_CLK 35
#define GCC_GP2_CLK_SRC 36
#define GCC_LPASS_CORE_AXIM_CLK 37
#define GCC_LPASS_SWAY_CLK 38
#define GCC_LPASS_SWAY_CLK_SRC 39
#define GCC_MDIO_AHB_CLK 40
#define GCC_MDIO_SLAVE_AHB_CLK 41
#define GCC_MEM_NOC_Q6_AXI_CLK 42
#define GCC_MEM_NOC_TS_CLK 43
#define GCC_NSS_TS_CLK 44
#define GCC_NSS_TS_CLK_SRC 45
#define GCC_NSSCC_CLK 46
#define GCC_NSSCFG_CLK 47
#define GCC_NSSNOC_ATB_CLK 48
#define GCC_NSSNOC_NSSCC_CLK 49
#define GCC_NSSNOC_QOSGEN_REF_CLK 50
#define GCC_NSSNOC_SNOC_1_CLK 51
#define GCC_NSSNOC_SNOC_CLK 52
#define GCC_NSSNOC_TIMEOUT_REF_CLK 53
#define GCC_NSSNOC_XO_DCD_CLK 54
#define GCC_PCIE3X1_0_AHB_CLK 55
#define GCC_PCIE3X1_0_AUX_CLK 56
#define GCC_PCIE3X1_0_AXI_CLK_SRC 57
#define GCC_PCIE3X1_0_AXI_M_CLK 58
#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59
#define GCC_PCIE3X1_0_AXI_S_CLK 60
#define GCC_PCIE3X1_0_PIPE_CLK 61
#define GCC_PCIE3X1_0_RCHG_CLK 62
#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63
#define GCC_PCIE3X1_1_AHB_CLK 64
#define GCC_PCIE3X1_1_AUX_CLK 65
#define GCC_PCIE3X1_1_AXI_CLK_SRC 66
#define GCC_PCIE3X1_1_AXI_M_CLK 67
#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68
#define GCC_PCIE3X1_1_AXI_S_CLK 69
#define GCC_PCIE3X1_1_PIPE_CLK 70
#define GCC_PCIE3X1_1_RCHG_CLK 71
#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72
#define GCC_PCIE3X1_PHY_AHB_CLK 73
#define GCC_PCIE3X2_AHB_CLK 74
#define GCC_PCIE3X2_AUX_CLK 75
#define GCC_PCIE3X2_AXI_M_CLK 76
#define GCC_PCIE3X2_AXI_M_CLK_SRC 77
#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78
#define GCC_PCIE3X2_AXI_S_CLK 79
#define GCC_PCIE3X2_AXI_S_CLK_SRC 80
#define GCC_PCIE3X2_PHY_AHB_CLK 81
#define GCC_PCIE3X2_PIPE_CLK 82
#define GCC_PCIE3X2_RCHG_CLK 83
#define GCC_PCIE3X2_RCHG_CLK_SRC 84
#define GCC_PCIE_AUX_CLK_SRC 85
#define GCC_PCNOC_AT_CLK 86
#define GCC_PCNOC_BFDCD_CLK_SRC 87
#define GCC_PCNOC_LPASS_CLK 88
#define GCC_PRNG_AHB_CLK 89
#define GCC_Q6_AHB_CLK 90
#define GCC_Q6_AHB_S_CLK 91
#define GCC_Q6_AXIM_CLK 92
#define GCC_Q6_AXIM_CLK_SRC 93
#define GCC_Q6_AXIS_CLK 94
#define GCC_Q6_TSCTR_1TO2_CLK 95
#define GCC_Q6SS_ATBM_CLK 96
#define GCC_Q6SS_PCLKDBG_CLK 97
#define GCC_Q6SS_TRIG_CLK 98
#define GCC_QDSS_AT_CLK 99
#define GCC_QDSS_AT_CLK_SRC 100
#define GCC_QDSS_CFG_AHB_CLK 101
#define GCC_QDSS_DAP_AHB_CLK 102
#define GCC_QDSS_DAP_CLK 103
#define GCC_QDSS_DAP_DIV_CLK_SRC 104
#define GCC_QDSS_ETR_USB_CLK 105
#define GCC_QDSS_EUD_AT_CLK 106
#define GCC_QDSS_TSCTR_CLK_SRC 107
#define GCC_QPIC_AHB_CLK 108
#define GCC_QPIC_CLK 109
#define GCC_QPIC_IO_MACRO_CLK 110
#define GCC_QPIC_IO_MACRO_CLK_SRC 111
#define GCC_QPIC_SLEEP_CLK 112
#define GCC_SDCC1_AHB_CLK 113
#define GCC_SDCC1_APPS_CLK 114
#define GCC_SDCC1_APPS_CLK_SRC 115
#define GCC_SLEEP_CLK_SRC 116
#define GCC_SNOC_LPASS_CFG_CLK 117
#define GCC_SNOC_NSSNOC_1_CLK 118
#define GCC_SNOC_NSSNOC_CLK 119
#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120
#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121
#define GCC_SNOC_PCIE3_1LANE_M_CLK 122
#define GCC_SNOC_PCIE3_1LANE_S_CLK 123
#define GCC_SNOC_PCIE3_2LANE_M_CLK 124
#define GCC_SNOC_PCIE3_2LANE_S_CLK 125
#define GCC_SNOC_USB_CLK 126
#define GCC_SYS_NOC_AT_CLK 127
#define GCC_SYS_NOC_WCSS_AHB_CLK 128
#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129
#define GCC_UNIPHY0_AHB_CLK 130
#define GCC_UNIPHY0_SYS_CLK 131
#define GCC_UNIPHY1_AHB_CLK 132
#define GCC_UNIPHY1_SYS_CLK 133
#define GCC_UNIPHY_SYS_CLK_SRC 134
#define GCC_USB0_AUX_CLK 135
#define GCC_USB0_AUX_CLK_SRC 136
#define GCC_USB0_EUD_AT_CLK 137
#define GCC_USB0_LFPS_CLK 138
#define GCC_USB0_LFPS_CLK_SRC 139
#define GCC_USB0_MASTER_CLK 140
#define GCC_USB0_MASTER_CLK_SRC 141
#define GCC_USB0_MOCK_UTMI_CLK 142
#define GCC_USB0_MOCK_UTMI_CLK_SRC 143
#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144
#define GCC_USB0_PHY_CFG_AHB_CLK 145
#define GCC_USB0_PIPE_CLK 146
#define GCC_USB0_SLEEP_CLK 147
#define GCC_WCSS_AHB_CLK_SRC 148
#define GCC_WCSS_AXIM_CLK 149
#define GCC_WCSS_AXIS_CLK 150
#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151
#define GCC_WCSS_DBG_IFC_APB_CLK 152
#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153
#define GCC_WCSS_DBG_IFC_ATB_CLK 154
#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155
#define GCC_WCSS_DBG_IFC_NTS_CLK 156
#define GCC_WCSS_ECAHB_CLK 157
#define GCC_WCSS_MST_ASYNC_BDG_CLK 158
#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159
#define GCC_XO_CLK 160
#define GCC_XO_CLK_SRC 161
#define GCC_XO_DIV4_CLK 162
#define GCC_IM_SLEEP_CLK 163
#define GCC_NSSNOC_PCNOC_1_CLK 164
#define GCC_MEM_NOC_AHB_CLK 165
#define GCC_MEM_NOC_APSS_AXI_CLK 166
#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167
#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168
#define GCC_PCIE3X2_PIPE_CLK_SRC 169
#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170
#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171
#define GCC_USB0_PIPE_CLK_SRC 172
#define GCC_ADSS_BCR 0
#define GCC_ADSS_PWM_CLK_ARES 1
#define GCC_AHB_CLK_ARES 2
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4
#define GCC_APSS_AHB_CLK_ARES 5
#define GCC_APSS_AXI_CLK_ARES 6
#define GCC_BLSP1_AHB_CLK_ARES 7
#define GCC_BLSP1_BCR 8
#define GCC_BLSP1_QUP1_BCR 9
#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10
#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11
#define GCC_BLSP1_QUP2_BCR 12
#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13
#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14
#define GCC_BLSP1_QUP3_BCR 15
#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16
#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17
#define GCC_BLSP1_SLEEP_CLK_ARES 18
#define GCC_BLSP1_UART1_APPS_CLK_ARES 19
#define GCC_BLSP1_UART1_BCR 20
#define GCC_BLSP1_UART2_APPS_CLK_ARES 21
#define GCC_BLSP1_UART2_BCR 22
#define GCC_BLSP1_UART3_APPS_CLK_ARES 23
#define GCC_BLSP1_UART3_BCR 24
#define GCC_CE_BCR 25
#define GCC_CMN_BLK_BCR 26
#define GCC_CMN_LDO0_BCR 27
#define GCC_CMN_LDO1_BCR 28
#define GCC_DCC_BCR 29
#define GCC_GP1_CLK_ARES 30
#define GCC_GP2_CLK_ARES 31
#define GCC_LPASS_BCR 32
#define GCC_LPASS_CORE_AXIM_CLK_ARES 33
#define GCC_LPASS_SWAY_CLK_ARES 34
#define GCC_MDIOM_BCR 35
#define GCC_MDIOS_BCR 36
#define GCC_NSS_BCR 37
#define GCC_NSS_TS_CLK_ARES 38
#define GCC_NSSCC_CLK_ARES 39
#define GCC_NSSCFG_CLK_ARES 40
#define GCC_NSSNOC_ATB_CLK_ARES 41
#define GCC_NSSNOC_NSSCC_CLK_ARES 42
#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43
#define GCC_NSSNOC_SNOC_1_CLK_ARES 44
#define GCC_NSSNOC_SNOC_CLK_ARES 45
#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46
#define GCC_NSSNOC_XO_DCD_CLK_ARES 47
#define GCC_PCIE3X1_0_AHB_CLK_ARES 48
#define GCC_PCIE3X1_0_AUX_CLK_ARES 49
#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50
#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51
#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52
#define GCC_PCIE3X1_0_BCR 53
#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54
#define GCC_PCIE3X1_0_PHY_BCR 55
#define GCC_PCIE3X1_0_PHY_PHY_BCR 56
#define GCC_PCIE3X1_1_AHB_CLK_ARES 57
#define GCC_PCIE3X1_1_AUX_CLK_ARES 58
#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59
#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60
#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61
#define GCC_PCIE3X1_1_BCR 62
#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63
#define GCC_PCIE3X1_1_PHY_BCR 64
#define GCC_PCIE3X1_1_PHY_PHY_BCR 65
#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66
#define GCC_PCIE3X2_AHB_CLK_ARES 67
#define GCC_PCIE3X2_AUX_CLK_ARES 68
#define GCC_PCIE3X2_AXI_M_CLK_ARES 69
#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70
#define GCC_PCIE3X2_AXI_S_CLK_ARES 71
#define GCC_PCIE3X2_BCR 72
#define GCC_PCIE3X2_LINK_DOWN_BCR 73
#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74
#define GCC_PCIE3X2_PHY_BCR 75
#define GCC_PCIE3X2PHY_PHY_BCR 76
#define GCC_PCNOC_BCR 77
#define GCC_PCNOC_LPASS_CLK_ARES 78
#define GCC_PRNG_AHB_CLK_ARES 79
#define GCC_PRNG_BCR 80
#define GCC_Q6_AHB_CLK_ARES 81
#define GCC_Q6_AHB_S_CLK_ARES 82
#define GCC_Q6_AXIM_CLK_ARES 83
#define GCC_Q6_AXIS_CLK_ARES 84
#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85
#define GCC_Q6SS_ATBM_CLK_ARES 86
#define GCC_Q6SS_PCLKDBG_CLK_ARES 87
#define GCC_Q6SS_TRIG_CLK_ARES 88
#define GCC_QDSS_APB2JTAG_CLK_ARES 89
#define GCC_QDSS_AT_CLK_ARES 90
#define GCC_QDSS_BCR 91
#define GCC_QDSS_CFG_AHB_CLK_ARES 92
#define GCC_QDSS_DAP_AHB_CLK_ARES 93
#define GCC_QDSS_DAP_CLK_ARES 94
#define GCC_QDSS_ETR_USB_CLK_ARES 95
#define GCC_QDSS_EUD_AT_CLK_ARES 96
#define GCC_QDSS_STM_CLK_ARES 97
#define GCC_QDSS_TRACECLKIN_CLK_ARES 98
#define GCC_QDSS_TS_CLK_ARES 99
#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100
#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101
#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102
#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103
#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104
#define GCC_QPIC_AHB_CLK_ARES 105
#define GCC_QPIC_CLK_ARES 106
#define GCC_QPIC_BCR 107
#define GCC_QPIC_IO_MACRO_CLK_ARES 108
#define GCC_QPIC_SLEEP_CLK_ARES 109
#define GCC_QUSB2_0_PHY_BCR 110
#define GCC_SDCC1_AHB_CLK_ARES 111
#define GCC_SDCC1_APPS_CLK_ARES 112
#define GCC_SDCC_BCR 113
#define GCC_SNOC_BCR 114
#define GCC_SNOC_LPASS_CFG_CLK_ARES 115
#define GCC_SNOC_NSSNOC_1_CLK_ARES 116
#define GCC_SNOC_NSSNOC_CLK_ARES 117
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118
#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119
#define GCC_UNIPHY0_AHB_CLK_ARES 120
#define GCC_UNIPHY0_BCR 121
#define GCC_UNIPHY0_SYS_CLK_ARES 122
#define GCC_UNIPHY1_AHB_CLK_ARES 123
#define GCC_UNIPHY1_BCR 124
#define GCC_UNIPHY1_SYS_CLK_ARES 125
#define GCC_USB0_AUX_CLK_ARES 126
#define GCC_USB0_EUD_AT_CLK_ARES 127
#define GCC_USB0_LFPS_CLK_ARES 128
#define GCC_USB0_MASTER_CLK_ARES 129
#define GCC_USB0_MOCK_UTMI_CLK_ARES 130
#define GCC_USB0_PHY_BCR 131
#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132
#define GCC_USB0_SLEEP_CLK_ARES 133
#define GCC_USB3PHY_0_PHY_BCR 134
#define GCC_USB_BCR 135
#define GCC_WCSS_AXIM_CLK_ARES 136
#define GCC_WCSS_AXIS_CLK_ARES 137
#define GCC_WCSS_BCR 138
#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139
#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140
#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141
#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142
#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143
#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144
#define GCC_WCSS_ECAHB_CLK_ARES 145
#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146
#define GCC_WCSS_Q6_BCR 147
#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148
#define GCC_XO_CLK_ARES 149
#define GCC_XO_DIV4_CLK_ARES 150
#define GCC_Q6SS_DBG_ARES 151
#define GCC_WCSS_DBG_BDG_ARES 152
#define GCC_WCSS_DBG_ARES 153
#define GCC_WCSS_AXI_S_ARES 154
#define GCC_WCSS_AXI_M_ARES 155
#define GCC_WCSSAON_ARES 156
#define GCC_PCIE3X2_PIPE_ARES 157
#define GCC_PCIE3X2_CORE_STICKY_ARES 158
#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159
#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160
#define GCC_PCIE3X1_0_PIPE_ARES 161
#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162
#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163
#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164
#define GCC_PCIE3X1_1_PIPE_ARES 165
#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166
#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167
#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168
#define GCC_IM_SLEEP_CLK_ARES 169
#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170
#define GCC_UNIPHY0_XPCS_ARES 171
#define GCC_UNIPHY1_XPCS_ARES 172
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2023 The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
#define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
#define GPLL0_MAIN 0
#define GPLL0 1
#define GPLL2_MAIN 2
#define GPLL2 3
#define GPLL4_MAIN 4
#define GPLL4 5
#define GCC_SLEEP_CLK_SRC 6
#define APSS_AHB_CLK_SRC 7
#define APSS_AXI_CLK_SRC 8
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 15
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 16
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 17
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 18
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 19
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 20
#define BLSP1_UART1_APPS_CLK_SRC 21
#define BLSP1_UART2_APPS_CLK_SRC 22
#define BLSP1_UART3_APPS_CLK_SRC 23
#define BLSP1_UART4_APPS_CLK_SRC 24
#define BLSP1_UART5_APPS_CLK_SRC 25
#define BLSP1_UART6_APPS_CLK_SRC 26
#define GCC_APSS_AHB_CLK 27
#define GCC_APSS_AXI_CLK 28
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 37
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 38
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 39
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 40
#define GCC_BLSP1_UART1_APPS_CLK 41
#define GCC_BLSP1_UART2_APPS_CLK 42
#define GCC_BLSP1_UART3_APPS_CLK 43
#define GCC_BLSP1_UART4_APPS_CLK 44
#define GCC_BLSP1_UART5_APPS_CLK 45
#define GCC_BLSP1_UART6_APPS_CLK 46
#define PCIE0_AXI_M_CLK_SRC 47
#define GCC_PCIE0_AXI_M_CLK 48
#define PCIE1_AXI_M_CLK_SRC 49
#define GCC_PCIE1_AXI_M_CLK 50
#define PCIE2_AXI_M_CLK_SRC 51
#define GCC_PCIE2_AXI_M_CLK 52
#define PCIE3_AXI_M_CLK_SRC 53
#define GCC_PCIE3_AXI_M_CLK 54
#define PCIE0_AXI_S_CLK_SRC 55
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 56
#define GCC_PCIE0_AXI_S_CLK 57
#define PCIE1_AXI_S_CLK_SRC 58
#define GCC_PCIE1_AXI_S_BRIDGE_CLK 59
#define GCC_PCIE1_AXI_S_CLK 60
#define PCIE2_AXI_S_CLK_SRC 61
#define GCC_PCIE2_AXI_S_BRIDGE_CLK 62
#define GCC_PCIE2_AXI_S_CLK 63
#define PCIE3_AXI_S_CLK_SRC 64
#define GCC_PCIE3_AXI_S_BRIDGE_CLK 65
#define GCC_PCIE3_AXI_S_CLK 66
#define PCIE0_PIPE_CLK_SRC 67
#define PCIE1_PIPE_CLK_SRC 68
#define PCIE2_PIPE_CLK_SRC 69
#define PCIE3_PIPE_CLK_SRC 70
#define PCIE_AUX_CLK_SRC 71
#define GCC_PCIE0_AUX_CLK 72
#define GCC_PCIE1_AUX_CLK 73
#define GCC_PCIE2_AUX_CLK 74
#define GCC_PCIE3_AUX_CLK 75
#define PCIE0_RCHNG_CLK_SRC 76
#define GCC_PCIE0_RCHNG_CLK 77
#define PCIE1_RCHNG_CLK_SRC 78
#define GCC_PCIE1_RCHNG_CLK 79
#define PCIE2_RCHNG_CLK_SRC 80
#define GCC_PCIE2_RCHNG_CLK 81
#define PCIE3_RCHNG_CLK_SRC 82
#define GCC_PCIE3_RCHNG_CLK 83
#define GCC_PCIE0_AHB_CLK 84
#define GCC_PCIE1_AHB_CLK 85
#define GCC_PCIE2_AHB_CLK 86
#define GCC_PCIE3_AHB_CLK 87
#define USB0_AUX_CLK_SRC 88
#define GCC_USB0_AUX_CLK 89
#define USB0_MASTER_CLK_SRC 90
#define GCC_USB0_MASTER_CLK 91
#define GCC_SNOC_USB_CLK 92
#define GCC_ANOC_USB_AXI_CLK 93
#define USB0_MOCK_UTMI_CLK_SRC 94
#define USB0_MOCK_UTMI_DIV_CLK_SRC 95
#define GCC_USB0_MOCK_UTMI_CLK 96
#define USB0_PIPE_CLK_SRC 97
#define GCC_USB0_PHY_CFG_AHB_CLK 98
#define SDCC1_APPS_CLK_SRC 99
#define GCC_SDCC1_APPS_CLK 100
#define SDCC1_ICE_CORE_CLK_SRC 101
#define GCC_SDCC1_ICE_CORE_CLK 102
#define GCC_SDCC1_AHB_CLK 103
#define PCNOC_BFDCD_CLK_SRC 104
#define GCC_NSSCFG_CLK 105
#define GCC_NSSNOC_NSSCC_CLK 106
#define GCC_NSSCC_CLK 107
#define GCC_NSSNOC_PCNOC_1_CLK 108
#define GCC_QDSS_DAP_AHB_CLK 109
#define GCC_QDSS_CFG_AHB_CLK 110
#define GCC_QPIC_AHB_CLK 111
#define GCC_QPIC_CLK 112
#define GCC_BLSP1_AHB_CLK 113
#define GCC_MDIO_AHB_CLK 114
#define GCC_PRNG_AHB_CLK 115
#define GCC_UNIPHY0_AHB_CLK 116
#define GCC_UNIPHY1_AHB_CLK 117
#define GCC_UNIPHY2_AHB_CLK 118
#define GCC_CMN_12GPLL_AHB_CLK 119
#define GCC_CMN_12GPLL_APU_CLK 120
#define SYSTEM_NOC_BFDCD_CLK_SRC 121
#define GCC_NSSNOC_SNOC_CLK 122
#define GCC_NSSNOC_SNOC_1_CLK 123
#define GCC_QDSS_ETR_USB_CLK 124
#define WCSS_AHB_CLK_SRC 125
#define GCC_Q6_AHB_CLK 126
#define GCC_Q6_AHB_S_CLK 127
#define GCC_WCSS_ECAHB_CLK 128
#define GCC_WCSS_ACMT_CLK 129
#define GCC_SYS_NOC_WCSS_AHB_CLK 130
#define WCSS_AXI_M_CLK_SRC 131
#define GCC_ANOC_WCSS_AXI_M_CLK 132
#define QDSS_AT_CLK_SRC 133
#define GCC_Q6SS_ATBM_CLK 134
#define GCC_WCSS_DBG_IFC_ATB_CLK 135
#define GCC_NSSNOC_ATB_CLK 136
#define GCC_QDSS_AT_CLK 137
#define GCC_SYS_NOC_AT_CLK 138
#define GCC_PCNOC_AT_CLK 139
#define GCC_USB0_EUD_AT_CLK 140
#define GCC_QDSS_EUD_AT_CLK 141
#define QDSS_STM_CLK_SRC 142
#define GCC_QDSS_STM_CLK 143
#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144
#define QDSS_TRACECLKIN_CLK_SRC 145
#define GCC_QDSS_TRACECLKIN_CLK 146
#define QDSS_TSCTR_CLK_SRC 147
#define GCC_Q6_TSCTR_1TO2_CLK 148
#define GCC_WCSS_DBG_IFC_NTS_CLK 149
#define GCC_QDSS_TSCTR_DIV2_CLK 150
#define GCC_QDSS_TS_CLK 151
#define GCC_QDSS_TSCTR_DIV4_CLK 152
#define GCC_NSS_TS_CLK 153
#define GCC_QDSS_TSCTR_DIV8_CLK 154
#define GCC_QDSS_TSCTR_DIV16_CLK 155
#define GCC_Q6SS_PCLKDBG_CLK 156
#define GCC_Q6SS_TRIG_CLK 157
#define GCC_WCSS_DBG_IFC_APB_CLK 158
#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159
#define GCC_QDSS_DAP_CLK 160
#define GCC_QDSS_APB2JTAG_CLK 161
#define GCC_QDSS_TSCTR_DIV3_CLK 162
#define QPIC_IO_MACRO_CLK_SRC 163
#define GCC_QPIC_IO_MACRO_CLK 164
#define Q6_AXI_CLK_SRC 165
#define GCC_Q6_AXIM_CLK 166
#define GCC_WCSS_Q6_TBU_CLK 167
#define GCC_MEM_NOC_Q6_AXI_CLK 168
#define Q6_AXIM2_CLK_SRC 169
#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170
#define GCC_NSSNOC_MEMNOC_CLK 171
#define GCC_NSSNOC_MEM_NOC_1_CLK 172
#define GCC_NSS_TBU_CLK 173
#define GCC_MEM_NOC_NSSNOC_CLK 174
#define LPASS_AXIM_CLK_SRC 175
#define LPASS_SWAY_CLK_SRC 176
#define ADSS_PWM_CLK_SRC 177
#define GCC_ADSS_PWM_CLK 178
#define GP1_CLK_SRC 179
#define GP2_CLK_SRC 180
#define GP3_CLK_SRC 181
#define DDRSS_SMS_SLOW_CLK_SRC 182
#define GCC_XO_CLK_SRC 183
#define GCC_XO_CLK 184
#define GCC_NSSNOC_QOSGEN_REF_CLK 185
#define GCC_NSSNOC_TIMEOUT_REF_CLK 186
#define GCC_XO_DIV4_CLK 187
#define GCC_UNIPHY0_SYS_CLK 188
#define GCC_UNIPHY1_SYS_CLK 189
#define GCC_UNIPHY2_SYS_CLK 190
#define GCC_CMN_12GPLL_SYS_CLK 191
#define GCC_NSSNOC_XO_DCD_CLK 192
#define GCC_Q6SS_BOOT_CLK 193
#define UNIPHY_SYS_CLK_SRC 194
#define NSS_TS_CLK_SRC 195
#define GCC_ANOC_PCIE0_1LANE_M_CLK 196
#define GCC_ANOC_PCIE1_1LANE_M_CLK 197
#define GCC_ANOC_PCIE2_2LANE_M_CLK 198
#define GCC_ANOC_PCIE3_2LANE_M_CLK 199
#define GCC_SNOC_PCIE0_1LANE_S_CLK 200
#define GCC_SNOC_PCIE1_1LANE_S_CLK 201
#define GCC_SNOC_PCIE2_2LANE_S_CLK 202
#define GCC_SNOC_PCIE3_2LANE_S_CLK 203
#endif

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include/dt-bindings/clock/qcom,sa8775p-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H
#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL1 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CRC_AHB_CLK 4
#define GPU_CC_CX_FF_CLK 5
#define GPU_CC_CX_GMU_CLK 6
#define GPU_CC_CX_SNOC_DVM_CLK 7
#define GPU_CC_CXO_AON_CLK 8
#define GPU_CC_CXO_CLK 9
#define GPU_CC_DEMET_CLK 10
#define GPU_CC_DEMET_DIV_CLK_SRC 11
#define GPU_CC_FF_CLK_SRC 12
#define GPU_CC_GMU_CLK_SRC 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15
#define GPU_CC_HUB_AON_CLK 16
#define GPU_CC_HUB_CLK_SRC 17
#define GPU_CC_HUB_CX_INT_CLK 18
#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19
#define GPU_CC_MEMNOC_GFX_CLK 20
#define GPU_CC_SLEEP_CLK 21
#define GPU_CC_XO_CLK_SRC 22
/* GPU_CC resets */
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CB_BCR 1
#define GPUCC_GPU_CC_CX_BCR 2
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
#define GPUCC_GPU_CC_FF_BCR 4
#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
#define GPUCC_GPU_CC_GMU_BCR 6
#define GPUCC_GPU_CC_GX_BCR 7
#define GPUCC_GPU_CC_XO_BCR 8
/* GPU_CC power domains */
#define GPU_CC_CX_GDSC 0
#define GPU_CC_GX_GDSC 1
#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */

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include/dt-bindings/clock/qcom,sm6115-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL0_OUT_AUX2 1
#define GPU_CC_PLL1 2
#define GPU_CC_PLL1_OUT_AUX 3
#define GPU_CC_AHB_CLK 4
#define GPU_CC_CRC_AHB_CLK 5
#define GPU_CC_CX_GFX3D_CLK 6
#define GPU_CC_CX_GMU_CLK 7
#define GPU_CC_CX_SNOC_DVM_CLK 8
#define GPU_CC_CXO_AON_CLK 9
#define GPU_CC_CXO_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_CXO_CLK 12
#define GPU_CC_GX_GFX3D_CLK 13
#define GPU_CC_GX_GFX3D_CLK_SRC 14
#define GPU_CC_SLEEP_CLK 15
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
/* Resets */
#define GPU_GX_BCR 0
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif

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include/dt-bindings/clock/qcom,sm6125-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H
/* Clocks */
#define GPU_CC_PLL0_OUT_AUX2 0
#define GPU_CC_PLL1_OUT_AUX2 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_APB_CLK 3
#define GPU_CC_CX_GFX3D_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CX_SNOC_DVM_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_GMU_CLK_SRC 9
#define GPU_CC_SLEEP_CLK 10
#define GPU_CC_GX_GFX3D_CLK 11
#define GPU_CC_GX_GFX3D_CLK_SRC 12
#define GPU_CC_AHB_CLK 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif

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include/dt-bindings/clock/qcom,sm6375-gpucc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H
/* GPU CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL1 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CX_GFX3D_CLK 3
#define GPU_CC_CX_GFX3D_SLV_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CX_SNOC_DVM_CLK 6
#define GPU_CC_CXO_AON_CLK 7
#define GPU_CC_CXO_CLK 8
#define GPU_CC_GMU_CLK_SRC 9
#define GPU_CC_GX_CXO_CLK 10
#define GPU_CC_GX_GFX3D_CLK 11
#define GPU_CC_GX_GFX3D_CLK_SRC 12
#define GPU_CC_GX_GMU_CLK 13
#define GPU_CC_SLEEP_CLK 14
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
/* Resets */
#define GPU_GX_BCR 0
#define GPU_ACD_BCR 1
#define GPU_GX_ACD_MISC_BCR 2
#endif

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include/dt-bindings/clock/qcom,sm7150-gcc.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com>
* Copyright (c) 2023, David Wronek <davidwronek@gmail.com>
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
/* GCC clock registers */
#define GCC_GPLL0_MAIN_DIV_CDIV 0
#define GPLL0 1
#define GPLL0_OUT_EVEN 2
#define GPLL6 3
#define GPLL7 4
#define GCC_AGGRE_NOC_PCIE_TBU_CLK 5
#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 7
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
#define GCC_APC_VS_CLK 9
#define GCC_BOOT_ROM_AHB_CLK 10
#define GCC_CAMERA_HF_AXI_CLK 11
#define GCC_CAMERA_SF_AXI_CLK 12
#define GCC_CE1_AHB_CLK 13
#define GCC_CE1_AXI_CLK 14
#define GCC_CE1_CLK 15
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 16
#define GCC_CPUSS_AHB_CLK 17
#define GCC_CPUSS_AHB_CLK_SRC 18
#define GCC_CPUSS_RBCPR_CLK 19
#define GCC_CPUSS_RBCPR_CLK_SRC 20
#define GCC_DDRSS_GPU_AXI_CLK 21
#define GCC_DISP_GPLL0_CLK_SRC 22
#define GCC_DISP_GPLL0_DIV_CLK_SRC 23
#define GCC_DISP_HF_AXI_CLK 24
#define GCC_DISP_SF_AXI_CLK 25
#define GCC_GP1_CLK 26
#define GCC_GP1_CLK_SRC 27
#define GCC_GP2_CLK 28
#define GCC_GP2_CLK_SRC 29
#define GCC_GP3_CLK 30
#define GCC_GP3_CLK_SRC 31
#define GCC_GPU_GPLL0_CLK_SRC 32
#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
#define GCC_GPU_MEMNOC_GFX_CLK 34
#define GCC_GPU_SNOC_DVM_GFX_CLK 35
#define GCC_GPU_VS_CLK 36
#define GCC_NPU_AXI_CLK 37
#define GCC_NPU_CFG_AHB_CLK 38
#define GCC_NPU_GPLL0_CLK_SRC 39
#define GCC_NPU_GPLL0_DIV_CLK_SRC 40
#define GCC_PCIE_0_AUX_CLK 41
#define GCC_PCIE_0_AUX_CLK_SRC 42
#define GCC_PCIE_0_CFG_AHB_CLK 43
#define GCC_PCIE_0_CLKREF_CLK 44
#define GCC_PCIE_0_MSTR_AXI_CLK 45
#define GCC_PCIE_0_PIPE_CLK 46
#define GCC_PCIE_0_SLV_AXI_CLK 47
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
#define GCC_PCIE_PHY_AUX_CLK 49
#define GCC_PCIE_PHY_REFGEN_CLK 50
#define GCC_PCIE_PHY_REFGEN_CLK_SRC 51
#define GCC_PDM2_CLK 52
#define GCC_PDM2_CLK_SRC 53
#define GCC_PDM_AHB_CLK 54
#define GCC_PDM_XO4_CLK 55
#define GCC_PRNG_AHB_CLK 56
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 57
#define GCC_QUPV3_WRAP0_CORE_CLK 58
#define GCC_QUPV3_WRAP0_S0_CLK 59
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 60
#define GCC_QUPV3_WRAP0_S1_CLK 61
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 62
#define GCC_QUPV3_WRAP0_S2_CLK 63
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 64
#define GCC_QUPV3_WRAP0_S3_CLK 65
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 66
#define GCC_QUPV3_WRAP0_S4_CLK 67
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 68
#define GCC_QUPV3_WRAP0_S5_CLK 69
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 70
#define GCC_QUPV3_WRAP0_S6_CLK 71
#define GCC_QUPV3_WRAP0_S6_CLK_SRC 72
#define GCC_QUPV3_WRAP0_S7_CLK 73
#define GCC_QUPV3_WRAP0_S7_CLK_SRC 74
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 75
#define GCC_QUPV3_WRAP1_CORE_CLK 76
#define GCC_QUPV3_WRAP1_S0_CLK 77
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 78
#define GCC_QUPV3_WRAP1_S1_CLK 79
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 80
#define GCC_QUPV3_WRAP1_S2_CLK 81
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 82
#define GCC_QUPV3_WRAP1_S3_CLK 83
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 84
#define GCC_QUPV3_WRAP1_S4_CLK 85
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 86
#define GCC_QUPV3_WRAP1_S5_CLK 87
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 88
#define GCC_QUPV3_WRAP1_S6_CLK 89
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 90
#define GCC_QUPV3_WRAP1_S7_CLK 91
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 92
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 93
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 94
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 95
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 96
#define GCC_SDCC1_AHB_CLK 97
#define GCC_SDCC1_APPS_CLK 98
#define GCC_SDCC1_APPS_CLK_SRC 99
#define GCC_SDCC1_ICE_CORE_CLK 100
#define GCC_SDCC1_ICE_CORE_CLK_SRC 101
#define GCC_SDCC2_AHB_CLK 102
#define GCC_SDCC2_APPS_CLK 103
#define GCC_SDCC2_APPS_CLK_SRC 104
#define GCC_SDCC4_AHB_CLK 105
#define GCC_SDCC4_APPS_CLK 106
#define GCC_SDCC4_APPS_CLK_SRC 107
#define GCC_SYS_NOC_CPUSS_AHB_CLK 108
#define GCC_TSIF_AHB_CLK 109
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 110
#define GCC_TSIF_REF_CLK 111
#define GCC_TSIF_REF_CLK_SRC 112
#define GCC_UFS_MEM_CLKREF_CLK 113
#define GCC_UFS_PHY_AHB_CLK 114
#define GCC_UFS_PHY_AXI_CLK 115
#define GCC_UFS_PHY_AXI_CLK_SRC 116
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 117
#define GCC_UFS_PHY_ICE_CORE_CLK 118
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 119
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 120
#define GCC_UFS_PHY_PHY_AUX_CLK 121
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 122
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 123
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 128
#define GCC_USB30_PRIM_MASTER_CLK 129
#define GCC_USB30_PRIM_MASTER_CLK_SRC 130
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 131
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 132
#define GCC_USB30_PRIM_SLEEP_CLK 133
#define GCC_USB3_PRIM_CLKREF_CLK 134
#define GCC_USB3_PRIM_PHY_AUX_CLK 135
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137
#define GCC_USB3_PRIM_PHY_PIPE_CLK 138
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 139
#define GCC_VDDA_VS_CLK 140
#define GCC_VDDCX_VS_CLK 141
#define GCC_VDDMX_VS_CLK 142
#define GCC_VIDEO_AXI_CLK 143
#define GCC_VS_CTRL_AHB_CLK 144
#define GCC_VS_CTRL_CLK 145
#define GCC_VS_CTRL_CLK_SRC 146
#define GCC_VSENSOR_CLK_SRC 147
/* GCC Resets */
#define GCC_PCIE_0_BCR 0
#define GCC_PCIE_PHY_BCR 1
#define GCC_PCIE_PHY_COM_BCR 2
#define GCC_UFS_PHY_BCR 3
#define GCC_USB30_PRIM_BCR 4
#define GCC_USB3_DP_PHY_PRIM_BCR 5
#define GCC_USB3_DP_PHY_SEC_BCR 6
#define GCC_USB3_PHY_PRIM_BCR 7
#define GCC_USB3_PHY_SEC_BCR 8
#define GCC_QUSB2PHY_PRIM_BCR 9
#define GCC_VIDEO_AXI_CLK_BCR 10
/* GCC GDSCRs */
#define PCIE_0_GDSC 0
#define UFS_PHY_GDSC 1
#define USB30_PRIM_GDSC 2
#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 3
#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 4
#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 5
#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 6
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 9
#endif

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2018-2023, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H
#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H
#define GCC_ADSS_BCR 0
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1
#define GCC_BLSP1_BCR 2
#define GCC_BLSP1_QUP1_BCR 3
#define GCC_BLSP1_QUP2_BCR 4
#define GCC_BLSP1_QUP3_BCR 5
#define GCC_BLSP1_QUP4_BCR 6
#define GCC_BLSP1_QUP5_BCR 7
#define GCC_BLSP1_QUP6_BCR 8
#define GCC_BLSP1_UART1_BCR 9
#define GCC_BLSP1_UART2_BCR 10
#define GCC_BLSP1_UART3_BCR 11
#define GCC_BLSP1_UART4_BCR 12
#define GCC_BLSP1_UART5_BCR 13
#define GCC_BLSP1_UART6_BCR 14
#define GCC_BOOT_ROM_BCR 15
#define GCC_MDIO_BCR 16
#define GCC_NSS_BCR 17
#define GCC_NSS_TBU_BCR 18
#define GCC_PCIE0_BCR 19
#define GCC_PCIE0_LINK_DOWN_BCR 20
#define GCC_PCIE0_PHY_BCR 21
#define GCC_PCIE0PHY_PHY_BCR 22
#define GCC_PCIE1_BCR 23
#define GCC_PCIE1_LINK_DOWN_BCR 24
#define GCC_PCIE1_PHY_BCR 25
#define GCC_PCIE1PHY_PHY_BCR 26
#define GCC_PCIE2_BCR 27
#define GCC_PCIE2_LINK_DOWN_BCR 28
#define GCC_PCIE2_PHY_BCR 29
#define GCC_PCIE2PHY_PHY_BCR 30
#define GCC_PCIE3_BCR 31
#define GCC_PCIE3_LINK_DOWN_BCR 32
#define GCC_PCIE3_PHY_BCR 33
#define GCC_PCIE3PHY_PHY_BCR 34
#define GCC_PRNG_BCR 35
#define GCC_QUSB2_0_PHY_BCR 36
#define GCC_SDCC_BCR 37
#define GCC_TLMM_BCR 38
#define GCC_UNIPHY0_BCR 39
#define GCC_UNIPHY1_BCR 40
#define GCC_UNIPHY2_BCR 41
#define GCC_USB0_PHY_BCR 42
#define GCC_USB3PHY_0_PHY_BCR 43
#define GCC_USB_BCR 44
#define GCC_ANOC0_TBU_BCR 45
#define GCC_ANOC1_TBU_BCR 46
#define GCC_ANOC_BCR 47
#define GCC_APSS_TCU_BCR 48
#define GCC_CMN_BLK_BCR 49
#define GCC_CMN_BLK_AHB_ARES 50
#define GCC_CMN_BLK_SYS_ARES 51
#define GCC_CMN_BLK_APU_ARES 52
#define GCC_DCC_BCR 53
#define GCC_DDRSS_BCR 54
#define GCC_IMEM_BCR 55
#define GCC_LPASS_BCR 56
#define GCC_MPM_BCR 57
#define GCC_MSG_RAM_BCR 58
#define GCC_NSSNOC_MEMNOC_1_ARES 59
#define GCC_NSSNOC_PCNOC_1_ARES 60
#define GCC_NSSNOC_SNOC_1_ARES 61
#define GCC_NSSNOC_XO_DCD_ARES 62
#define GCC_NSSNOC_TS_ARES 63
#define GCC_NSSCC_ARES 64
#define GCC_NSSNOC_NSSCC_ARES 65
#define GCC_NSSNOC_ATB_ARES 66
#define GCC_NSSNOC_MEMNOC_ARES 67
#define GCC_NSSNOC_QOSGEN_REF_ARES 68
#define GCC_NSSNOC_SNOC_ARES 69
#define GCC_NSSNOC_TIMEOUT_REF_ARES 70
#define GCC_NSS_CFG_ARES 71
#define GCC_UBI0_DBG_ARES 72
#define GCC_PCIE0_AHB_ARES 73
#define GCC_PCIE0_AUX_ARES 74
#define GCC_PCIE0_AXI_M_ARES 75
#define GCC_PCIE0_AXI_M_STICKY_ARES 76
#define GCC_PCIE0_AXI_S_ARES 77
#define GCC_PCIE0_AXI_S_STICKY_ARES 78
#define GCC_PCIE0_CORE_STICKY_ARES 79
#define GCC_PCIE0_PIPE_ARES 80
#define GCC_PCIE1_AHB_ARES 81
#define GCC_PCIE1_AUX_ARES 82
#define GCC_PCIE1_AXI_M_ARES 83
#define GCC_PCIE1_AXI_M_STICKY_ARES 84
#define GCC_PCIE1_AXI_S_ARES 85
#define GCC_PCIE1_AXI_S_STICKY_ARES 86
#define GCC_PCIE1_CORE_STICKY_ARES 87
#define GCC_PCIE1_PIPE_ARES 88
#define GCC_PCIE2_AHB_ARES 89
#define GCC_PCIE2_AUX_ARES 90
#define GCC_PCIE2_AXI_M_ARES 91
#define GCC_PCIE2_AXI_M_STICKY_ARES 92
#define GCC_PCIE2_AXI_S_ARES 93
#define GCC_PCIE2_AXI_S_STICKY_ARES 94
#define GCC_PCIE2_CORE_STICKY_ARES 95
#define GCC_PCIE2_PIPE_ARES 96
#define GCC_PCIE3_AHB_ARES 97
#define GCC_PCIE3_AUX_ARES 98
#define GCC_PCIE3_AXI_M_ARES 99
#define GCC_PCIE3_AXI_M_STICKY_ARES 100
#define GCC_PCIE3_AXI_S_ARES 101
#define GCC_PCIE3_AXI_S_STICKY_ARES 102
#define GCC_PCIE3_CORE_STICKY_ARES 103
#define GCC_PCIE3_PIPE_ARES 104
#define GCC_PCNOC_BCR 105
#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106
#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107
#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108
#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109
#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110
#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111
#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112
#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113
#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114
#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115
#define GCC_PCNOC_TBU_BCR 116
#define GCC_Q6SS_DBG_ARES 117
#define GCC_Q6_AHB_ARES 118
#define GCC_Q6_AHB_S_ARES 119
#define GCC_Q6_AXIM2_ARES 120
#define GCC_Q6_AXIM_ARES 121
#define GCC_QDSS_BCR 122
#define GCC_QPIC_BCR 123
#define GCC_QPIC_AHB_ARES 124
#define GCC_QPIC_ARES 125
#define GCC_RBCPR_BCR 126
#define GCC_RBCPR_MX_BCR 127
#define GCC_SEC_CTRL_BCR 128
#define GCC_SMMU_CFG_BCR 129
#define GCC_SNOC_BCR 130
#define GCC_SPDM_BCR 131
#define GCC_TME_BCR 132
#define GCC_UNIPHY0_SYS_RESET 133
#define GCC_UNIPHY0_AHB_RESET 134
#define GCC_UNIPHY0_XPCS_RESET 135
#define GCC_UNIPHY1_SYS_RESET 136
#define GCC_UNIPHY1_AHB_RESET 137
#define GCC_UNIPHY1_XPCS_RESET 138
#define GCC_UNIPHY2_SYS_RESET 139
#define GCC_UNIPHY2_AHB_RESET 140
#define GCC_UNIPHY2_XPCS_RESET 141
#define GCC_USB_MISC_RESET 142
#define GCC_WCSSAON_RESET 143
#define GCC_WCSS_ACMT_ARES 144
#define GCC_WCSS_AHB_S_ARES 145
#define GCC_WCSS_AXI_M_ARES 146
#define GCC_WCSS_BCR 147
#define GCC_WCSS_DBG_ARES 148
#define GCC_WCSS_DBG_BDG_ARES 149
#define GCC_WCSS_ECAHB_ARES 150
#define GCC_WCSS_Q6_BCR 151
#define GCC_WCSS_Q6_TBU_BCR 152
#define GCC_TCSR_BCR 153
#endif