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clk: zynqmp: Extend driver for versal

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Add Versal compatible string to support Versal
binding.

Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lkml.kernel.org/r/1575527759-26452-3-git-send-email-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Rajan Vaja 2019-12-04 22:35:55 -08:00 committed by Stephen Boyd
parent 352546805a
commit c1e846b8ee
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/zynqmp/clkc.c
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@ -2,7 +2,7 @@
/*
* Zynq UltraScale+ MPSoC clock controller
*
* Copyright (C) 2016-2018 Xilinx
* Copyright (C) 2016-2019 Xilinx
*
* Based on drivers/clk/zynq/clkc.c
*/
@ -749,6 +749,7 @@ static int zynqmp_clock_probe(struct platform_device *pdev)
static const struct of_device_id zynqmp_clock_of_match[] = {
{.compatible = "xlnx,zynqmp-clk"},
{.compatible = "xlnx,versal-clk"},
{},
};
MODULE_DEVICE_TABLE(of, zynqmp_clock_of_match);