perf/x86/intel: Add Tremont Topdown support
Tremont has four L1 Topdown events, TOPDOWN_FE_BOUND.ALL, TOPDOWN_BAD_SPECULATION.ALL, TOPDOWN_BE_BOUND.ALL and TOPDOWN_RETIRING.ALL. They are available on GP counters. Export them to sysfs and facilitate the perf stat tool. $perf stat --topdown -- sleep 1 Performance counter stats for 'sleep 1': retiring bad speculation frontend bound backend bound 24.9% 16.8% 31.7% 26.6% 1.001224610 seconds time elapsed 0.001150000 seconds user 0.000000000 seconds sys Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1607457952-3519-1-git-send-email-kan.liang@linux.intel.com
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@ -1901,6 +1901,19 @@ static __initconst const u64 tnt_hw_cache_extra_regs
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},
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};
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EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
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EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
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EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
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EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
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static struct attribute *tnt_events_attrs[] = {
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EVENT_PTR(td_fe_bound_tnt),
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EVENT_PTR(td_retiring_tnt),
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EVENT_PTR(td_bad_spec_tnt),
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EVENT_PTR(td_be_bound_tnt),
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NULL,
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};
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static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
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/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
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INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
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@ -5174,6 +5187,7 @@ __init int intel_pmu_init(void)
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x86_pmu.lbr_pt_coexist = true;
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x86_pmu.flags |= PMU_FL_HAS_RSP_1;
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x86_pmu.get_event_constraints = tnt_get_event_constraints;
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td_attr = tnt_events_attrs;
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extra_attr = slm_format_attr;
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pr_cont("Tremont events, ");
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name = "Tremont";
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