Merge branch 'net-dsa-mv88e6xxx-add-88e6361-support'
Alexis Lothoré says: ==================== net: dsa: mv88e6xxx: add 88E6361 support This series brings initial support for Marvell 88E6361 switch. MV88E6361 is a 8 ports switch with 5 integrated Gigabit PHYs and 3 2.5Gigabit SerDes interfaces. It is in fact a new variant in the 88E639X/88E6193X/88E6191X family with a subset of existing features: - port 0: MII, RMII, RGMII, 1000BaseX, 2500BaseX - port 3 to 7: triple speed internal phys - port 9 and 10: 1000BaseX, 25000BaseX Since said family is already well supported in mv88e6xxx driver, adding initial support for this new switch mostly consists in finding the ID exposed in its identification register, adding a proper description in switch description tables in mv88e6xxx driver, and enforcing 88E6361 specificities in mv88e6393x_XXX methods. - first 4 commits introduce an internal phy offset field for switches which have internal phys but not starting from port 0 - 5th commit is a fix on existing switches based on first commits - 6th commit is a slight modification to prepare 886361 support - last commit introduces 88E6361 support in 88E6393X family This initial support has been tested with two samples of a custom board with the following hardware configuration: - a main CPU connected to MV88E6361 using port 0 as CPU port - port 9 wired to a SFP cage - port 10 wired to a G.Hn transceiver The following setup was used: PC <-ethernet-> (copper SFP) - Board 1 - (G.hn) <-phone line(RJ11)-> (G.hn) Board 2 The unit 1 has been configured to bridge SFP port and G.hn port together, which allowed to successfully ping Board 2 from PC. ==================== Link: https://lore.kernel.org/r/20230529080246.82953-1-alexis.lothore@bootlin.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
c23515ad4e
@ -20,7 +20,7 @@ which is at a different MDIO base address in different switch families.
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6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
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6341, 6350, 6351, 6352
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- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
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6190, 6190X, 6191, 6290, 6390, 6390X
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6163, 6190, 6190X, 6191, 6290, 6390, 6390X
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- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
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6220, 6250
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@ -463,11 +463,11 @@ restore_link:
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return err;
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}
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static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
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static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
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{
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struct mv88e6xxx_chip *chip = ds->priv;
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return port < chip->info->num_internal_phys;
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return port >= chip->info->internal_phys_offset &&
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port < chip->info->num_internal_phys +
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chip->info->internal_phys_offset;
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}
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static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
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@ -479,7 +479,7 @@ static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
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* report whether the port is internal.
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*/
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if (chip->info->family == MV88E6XXX_FAMILY_6250)
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return port < chip->info->num_internal_phys;
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return mv88e6xxx_phy_is_internal(chip, port);
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
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if (err) {
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@ -584,7 +584,7 @@ static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
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config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
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if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
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if (mv88e6xxx_phy_is_internal(chip, port)) {
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__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
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} else {
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if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
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@ -790,6 +790,8 @@ static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
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unsigned long *supported = config->supported_interfaces;
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bool is_6191x =
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chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
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bool is_6361 =
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chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361;
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mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
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@ -804,13 +806,17 @@ static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
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/* 6191X supports >1G modes only on port 10 */
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if (!is_6191x || port == 10) {
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__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
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__set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
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__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
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config->mac_capabilities |= MAC_2500FD;
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/* 6361 only supports up to 2500BaseX */
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if (!is_6361) {
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__set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
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__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
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config->mac_capabilities |= MAC_5000FD |
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MAC_10000FD;
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}
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/* FIXME: USXGMII is not supported yet */
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/* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
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config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
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MAC_10000FD;
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}
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}
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@ -832,7 +838,7 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
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chip->info->ops->phylink_get_caps(chip, port, config);
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mv88e6xxx_reg_unlock(chip);
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if (mv88e6xxx_phy_is_internal(ds, port)) {
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if (mv88e6xxx_phy_is_internal(chip, port)) {
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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config->supported_interfaces);
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/* Internal ports with no phy-mode need GMII for PHYLIB */
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@ -872,7 +878,7 @@ static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
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mv88e6xxx_reg_lock(chip);
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if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
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if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) {
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err = mv88e6xxx_port_config_interface(chip, port,
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state->interface);
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if (err && err != -EOPNOTSUPP)
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@ -3334,7 +3340,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
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caps = pl_config.mac_capabilities;
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if (chip->info->ops->port_max_speed_mode)
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mode = chip->info->ops->port_max_speed_mode(port);
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mode = chip->info->ops->port_max_speed_mode(chip, port);
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else
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mode = PHY_INTERFACE_MODE_NA;
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@ -6047,7 +6053,8 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
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.name = "Marvell 88E6191X",
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.num_databases = 4096,
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.num_ports = 11, /* 10 + Z80 */
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.num_internal_phys = 9,
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.num_internal_phys = 8,
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.internal_phys_offset = 1,
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.max_vid = 8191,
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.max_sid = 63,
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.port_base_addr = 0x0,
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@ -6070,7 +6077,8 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
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.name = "Marvell 88E6193X",
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.num_databases = 4096,
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.num_ports = 11, /* 10 + Z80 */
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.num_internal_phys = 9,
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.num_internal_phys = 8,
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.internal_phys_offset = 1,
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.max_vid = 8191,
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.max_sid = 63,
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.port_base_addr = 0x0,
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@ -6332,6 +6340,32 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
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.ptp_support = true,
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.ops = &mv88e6352_ops,
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},
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[MV88E6361] = {
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.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361,
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.family = MV88E6XXX_FAMILY_6393,
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.name = "Marvell 88E6361",
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.num_databases = 4096,
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.num_macs = 16384,
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.num_ports = 11,
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/* Ports 1, 2 and 8 are not routed */
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.invalid_port_mask = BIT(1) | BIT(2) | BIT(8),
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.num_internal_phys = 5,
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.internal_phys_offset = 3,
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.max_vid = 4095,
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.max_sid = 63,
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.port_base_addr = 0x0,
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.phy_base_addr = 0x0,
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.global1_addr = 0x1b,
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.global2_addr = 0x1c,
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.age_time_coeff = 3750,
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.g1_irqs = 10,
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.g2_irqs = 14,
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.atu_move_port_mask = 0x1f,
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.pvt = true,
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.multi_chip = true,
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.ptp_support = true,
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.ops = &mv88e6393x_ops,
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},
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[MV88E6390] = {
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.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
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.family = MV88E6XXX_FAMILY_6390,
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@ -6389,7 +6423,8 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
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.name = "Marvell 88E6393X",
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.num_databases = 4096,
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.num_ports = 11, /* 10 + Z80 */
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.num_internal_phys = 9,
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.num_internal_phys = 8,
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.internal_phys_offset = 1,
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.max_vid = 8191,
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.max_sid = 63,
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.port_base_addr = 0x0,
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@ -82,6 +82,7 @@ enum mv88e6xxx_model {
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MV88E6350,
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MV88E6351,
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MV88E6352,
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MV88E6361,
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MV88E6390,
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MV88E6390X,
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MV88E6393X,
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@ -100,7 +101,7 @@ enum mv88e6xxx_family {
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MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
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MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
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MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
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MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6393X */
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MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
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};
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/**
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@ -167,6 +168,11 @@ struct mv88e6xxx_info {
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/* Supports PTP */
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bool ptp_support;
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/* Internal PHY start index. 0 means that internal PHYs range starts at
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* port 0, 1 means internal PHYs range starts at port 1, etc
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*/
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unsigned int internal_phys_offset;
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};
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struct mv88e6xxx_atu_entry {
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@ -513,7 +519,8 @@ struct mv88e6xxx_ops {
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int speed, int duplex);
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/* What interface mode should be used for maximum speed? */
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phy_interface_t (*port_max_speed_mode)(int port);
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phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip,
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int port);
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int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
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@ -1196,9 +1196,12 @@ out:
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int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus)
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{
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int phy_start = chip->info->internal_phys_offset;
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int phy_end = chip->info->internal_phys_offset +
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chip->info->num_internal_phys;
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int phy, irq;
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for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
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for (phy = phy_start; phy < phy_end; phy++) {
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irq = irq_find_mapping(chip->g2_irq.domain, phy);
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if (irq < 0)
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return irq;
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@ -342,7 +342,8 @@ int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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duplex);
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}
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phy_interface_t mv88e6341_port_max_speed_mode(int port)
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phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port)
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{
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if (port == 5)
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return PHY_INTERFACE_MODE_2500BASEX;
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@ -381,7 +382,8 @@ int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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duplex);
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}
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phy_interface_t mv88e6390_port_max_speed_mode(int port)
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phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port)
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{
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if (port == 9 || port == 10)
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return PHY_INTERFACE_MODE_2500BASEX;
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@ -403,7 +405,8 @@ int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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duplex);
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}
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phy_interface_t mv88e6390x_port_max_speed_mode(int port)
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phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port)
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{
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if (port == 9 || port == 10)
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return PHY_INTERFACE_MODE_XAUI;
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@ -421,6 +424,10 @@ int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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u16 reg, ctrl;
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int err;
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if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361 &&
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speed > 2500)
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return -EOPNOTSUPP;
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if (speed == 200 && port != 0)
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return -EOPNOTSUPP;
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@ -500,12 +507,17 @@ int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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return 0;
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}
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phy_interface_t mv88e6393x_port_max_speed_mode(int port)
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phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port)
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{
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if (port == 0 || port == 9 || port == 10)
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return PHY_INTERFACE_MODE_10GBASER;
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return PHY_INTERFACE_MODE_NA;
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if (port != 0 && port != 9 && port != 10)
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return PHY_INTERFACE_MODE_NA;
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if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361)
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return PHY_INTERFACE_MODE_2500BASEX;
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return PHY_INTERFACE_MODE_10GBASER;
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}
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static int mv88e6xxx_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
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@ -133,6 +133,7 @@
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
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#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400
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@ -359,10 +360,14 @@ int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
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int speed, int duplex);
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phy_interface_t mv88e6341_port_max_speed_mode(int port);
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phy_interface_t mv88e6390_port_max_speed_mode(int port);
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phy_interface_t mv88e6390x_port_max_speed_mode(int port);
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phy_interface_t mv88e6393x_port_max_speed_mode(int port);
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phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port);
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phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port);
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phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port);
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phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
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int port);
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int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
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