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drm/msm/a6xx: Add gmu_read64() register read op

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Add a simple function to read 64 registers in the GMU domain

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Sharat Masetty 2018-10-04 15:11:41 +05:30 committed by Rob Clark
parent d3fa91c909
commit c28aa2031f
1 changed files with 10 additions and 0 deletions
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10
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
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@ -98,6 +98,16 @@ static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
gmu_write(gmu, reg, val | or); gmu_write(gmu, reg, val | or);
} }
static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
{
u64 val;
val = (u64) msm_readl(gmu->mmio + (lo << 2));
val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
return val;
}
#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
interval, timeout) interval, timeout)