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pinctrl: ocelot: Fix interrupt controller

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When an external device generated a level based interrupt then the
interrupt controller could miss the interrupt. The reason is that the
interrupt controller can detect only link changes.

In the following example, if there is a PHY that generates an interrupt
then the following would happen. The GPIO detected that the interrupt
line changed, and then the 'ocelot_irq_handler' was called. Here it
detects which GPIO line saw the change and for that will call the
following:
1. irq_mask
2. phy interrupt routine
3. irq_eoi
4. irq_unmask

And this works fine for simple cases, but if the PHY generates many
interrupts, for example when doing PTP timestamping, then the following
could happen. Again the function 'ocelot_irq_handler' will be called
and then from here the following could happen:
1. irq_mask
2. phy interrupt routine
3. irq_eoi
4. irq_unmask

Right before step 3(irq_eoi), the PHY will generate another interrupt.
Now the interrupt controller will acknowledge the change in the
interrupt line. So we miss the interrupt.

A solution will be to use 'handle_level_irq' instead of
'handle_fasteoi_irq', because for this will change routine order of
handling the interrupt.
1. irq_mask
2. irq_ack
3. phy interrupt routine
4. irq_unmask

And now if the PHY will generate a new interrupt before irq_unmask, the
interrupt controller will detect this because it already acknowledge the
change in interrupt line at step 2(irq_ack).

But this is not the full solution because there is another issue. In
case there are 2 PHYs that share the interrupt line. For example phy1
generates an interrupt, then the following can happen:
1.irq_mask
2.irq_ack
3.phy0 interrupt routine
4.phy1 interrupt routine
5.irq_unmask

In case phy0 will generate an interrupt while clearing the interrupt
source in phy1, then the interrupt line will be kept down by phy0. So
the interrupt controller will not see any changes in the interrupt line.
The solution here is to update 'irq_unmask' such that it can detect if
the interrupt line is still active or not. And if it is active then call
again the procedure to clear the interrupts. But we don't want to do it
every time, only if we know that the interrupt controller has not seen
already that the interrupt line has changed.

While at this, add support also for IRQ_TYPE_LEVEL_LOW.

Fixes: be36abb71d ("pinctrl: ocelot: add support for interrupt controller")
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220909145942.844102-1-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Horatiu Vultur 2022-09-09 16:59:42 +02:00 committed by Linus Walleij
parent 76648c867c
commit c297561bc9
1 changed files with 97 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
drivers/pinctrl/pinctrl-ocelot.c
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@ -331,6 +331,7 @@ struct ocelot_pinctrl {
const struct ocelot_pincfg_data *pincfg_data;
struct ocelot_pmx_func func[FUNC_MAX];
u8 stride;
struct workqueue_struct *wq;
};
struct ocelot_match_data {
@ -338,6 +339,11 @@ struct ocelot_match_data {
struct ocelot_pincfg_data pincfg_data;
};
struct ocelot_irq_work {
struct work_struct irq_work;
struct irq_desc *irq_desc;
};
#define LUTON_P(p, f0, f1) \
static struct ocelot_pin_caps luton_pin_##p = { \
.pin = p, \
@ -1813,6 +1819,75 @@ static void ocelot_irq_mask(struct irq_data *data)
gpiochip_disable_irq(chip, gpio);
}
static void ocelot_irq_work(struct work_struct *work)
{
struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work);
struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc);
struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc);
struct irq_data *data = irq_desc_get_irq_data(w->irq_desc);
unsigned int gpio = irqd_to_hwirq(data);
local_irq_disable();
chained_irq_enter(parent_chip, w->irq_desc);
generic_handle_domain_irq(chip->irq.domain, gpio);
chained_irq_exit(parent_chip, w->irq_desc);
local_irq_enable();
kfree(w);
}
static void ocelot_irq_unmask_level(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
struct irq_desc *desc = irq_data_to_desc(data);
unsigned int gpio = irqd_to_hwirq(data);
unsigned int bit = BIT(gpio % 32);
bool ack = false, active = false;
u8 trigger_level;
int val;
trigger_level = irqd_get_trigger_type(data);
/* Check if the interrupt line is still active. */
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
(val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
active = true;
/*
* Check if the interrupt controller has seen any changes in the
* interrupt line.
*/
regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val);
if (val & bit)
ack = true;
/* Enable the interrupt now */
gpiochip_enable_irq(chip, gpio);
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
bit, bit);
/*
* In case the interrupt line is still active and the interrupt
* controller has not seen any changes in the interrupt line, then it
* means that there happen another interrupt while the line was active.
* So we missed that one, so we need to kick the interrupt again
* handler.
*/
if (active && !ack) {
struct ocelot_irq_work *work;
work = kmalloc(sizeof(*work), GFP_ATOMIC);
if (!work)
return;
work->irq_desc = desc;
INIT_WORK(&work->irq_work, ocelot_irq_work);
queue_work(info->wq, &work->irq_work);
}
}
static void ocelot_irq_unmask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
@ -1836,13 +1911,12 @@ static void ocelot_irq_ack(struct irq_data *data)
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
static struct irq_chip ocelot_eoi_irqchip = {
static struct irq_chip ocelot_level_irqchip = {
.name = "gpio",
.irq_mask = ocelot_irq_mask,
.irq_eoi = ocelot_irq_ack,
.irq_unmask = ocelot_irq_unmask,
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
IRQCHIP_IMMUTABLE,
.irq_ack = ocelot_irq_ack,
.irq_unmask = ocelot_irq_unmask_level,
.flags = IRQCHIP_IMMUTABLE,
.irq_set_type = ocelot_irq_set_type,
GPIOCHIP_IRQ_RESOURCE_HELPERS
};
@ -1859,14 +1933,9 @@ static struct irq_chip ocelot_irqchip = {
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
{
type &= IRQ_TYPE_SENSE_MASK;
if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
if (type & IRQ_TYPE_LEVEL_HIGH)
irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
handle_fasteoi_irq, NULL);
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip,
handle_level_irq, NULL);
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
handle_edge_irq, NULL);
@ -1996,6 +2065,10 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
if (!info->desc)
return -ENOMEM;
info->wq = alloc_ordered_workqueue("ocelot_ordered", 0);
if (!info->wq)
return -ENOMEM;
info->pincfg_data = &data->pincfg_data;
reset = devm_reset_control_get_optional_shared(dev, "switch");
@ -2018,7 +2091,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
dev_err(dev, "Failed to create regmap\n");
return PTR_ERR(info->map);
}
dev_set_drvdata(dev, info->map);
dev_set_drvdata(dev, info);
info->dev = dev;
/* Pinconf registers */
@ -2043,6 +2116,15 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
return 0;
}
static int ocelot_pinctrl_remove(struct platform_device *pdev)
{
struct ocelot_pinctrl *info = platform_get_drvdata(pdev);
destroy_workqueue(info->wq);
return 0;
}
static struct platform_driver ocelot_pinctrl_driver = {
.driver = {
.name = "pinctrl-ocelot",
@ -2050,6 +2132,7 @@ static struct platform_driver ocelot_pinctrl_driver = {
.suppress_bind_attrs = true,
},
.probe = ocelot_pinctrl_probe,
.remove = ocelot_pinctrl_remove,
};
module_platform_driver(ocelot_pinctrl_driver);
MODULE_LICENSE("Dual MIT/GPL");