From c2fa4f4ad8ddf4b9fac344f1da7a25d4868f08f5 Mon Sep 17 00:00:00 2001 From: Adam Kropelin Date: Fri, 16 Sep 2005 19:28:18 -0700 Subject: [PATCH] [PATCH] pciehp: Use dword accessors for PCI_ROM_ADDRESS PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using pci_bus_{read,write}_config_dword(). A recent audit of drivers/ turned up several cases of byte- and word-sized accesses. The harmful ones were fixed by Linus directly. This patches up one of the remaining harmless-but-still-wrong cases caught in the dragnet. Signed-off-by: Adam Kropelin Cc: Cc: Greg KH Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/pci/hotplug/pciehp_ctrl.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c index 0e0947601526..898f6da6f0de 100644 --- a/drivers/pci/hotplug/pciehp_ctrl.c +++ b/drivers/pci/hotplug/pciehp_ctrl.c @@ -2526,7 +2526,6 @@ configure_new_function(struct controller *ctrl, struct pci_func *func, int cloop; u8 temp_byte; u8 class_code; - u16 temp_word; u32 rc; u32 temp_register; u32 base; @@ -2682,8 +2681,7 @@ configure_new_function(struct controller *ctrl, struct pci_func *func, } /* End of base register loop */ /* disable ROM base Address */ - temp_word = 0x00L; - rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word); + rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00); /* Set HP parameters (Cache Line Size, Latency Timer) */ rc = pciehprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);