iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

Browse Source 
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
  powerpc/ps3: Fix build error on UP
  powerpc/cell: Select PCI for IBM_CELL_BLADE AND CELLEB
  powerpc: ppc32 needs elf_read_implies_exec()
  powerpc/86xx: Add device_type entry to soc for ppc9a
  powerpc/44x: Correct memory size calculation for denali-based boards
  maintainers: Fix PowerPC 4xx git tree
  powerpc: fix for long standing bug noticed by gcc 4.4.0
  Revert "powerpc: Add support for early tlbilx opcode"
This commit is contained in:
Linus Torvalds 2009-04-28 15:55:32 -07:00
commit c3310e7766
10 changed files with 54 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -3448,7 +3448,7 @@ P: Matt Porter
M: mporter@kernel.crashing.org
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
S: Maintained
LINUX FOR POWERPC EMBEDDED XILINX VIRTEX

56
arch/powerpc/boot/4xx.c
View File

@ -158,6 +158,46 @@ void ibm440spe_fixup_memsize(void)
#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
/*
* Some U-Boot versions set the number of chipselects to two
* for Sequoia/Rainier boards while they only have one chipselect
* hardwired. Hardcode the number of chipselects to one
* for sequioa/rainer board models or read the actual value
* from the memory controller register DDR0_10 otherwise.
*/
static inline u32 ibm4xx_denali_get_cs(void)
{
void *devp;
char model[64];
u32 val, cs;
devp = finddevice("/");
if (!devp)
goto read_cs;
if (getprop(devp, "model", model, sizeof(model)) <= 0)
goto read_cs;
model[sizeof(model)-1] = 0;
if (!strcmp(model, "amcc,sequoia") ||
!strcmp(model, "amcc,rainier"))
return 1;
read_cs:
/* get CS value */
val = SDRAM0_READ(DDR0_10);
val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
cs = 0;
while (val) {
if (val & 0x1)
cs++;
val = val >> 1;
}
return cs;
}
void ibm4xx_denali_fixup_memsize(void)
{
u32 val, max_cs, max_col, max_row;
@ -173,17 +213,7 @@ void ibm4xx_denali_fixup_memsize(void)
max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
/* get CS value */
val = SDRAM0_READ(DDR0_10);
val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
cs = 0;
while (val) {
if (val & 0x1)
cs++;
val = val >> 1;
}
cs = ibm4xx_denali_get_cs();
if (!cs)
fatal("No memory installed\n");
if (cs > max_cs)
@ -193,9 +223,9 @@ void ibm4xx_denali_fixup_memsize(void)
val = SDRAM0_READ(DDR0_14);
if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
dpath = 8; /* 64 bits */
else
dpath = 4; /* 32 bits */
else
dpath = 8; /* 64 bits */
/* get address pins (rows) */
val = SDRAM0_READ(DDR0_42);

1
arch/powerpc/boot/dts/gef_ppc9a.dts
View File

@ -161,6 +161,7 @@
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8641-soc", "simple-bus";
ranges = <0x0 0xfef00000 0x00100000>;
reg = <0xfef00000 0x100000>; // CCSRBAR 1M

1
arch/powerpc/include/asm/elf.h
View File

@ -260,6 +260,7 @@ do { \
#else
# define SET_PERSONALITY(ex) \
set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X)
#endif /* __powerpc64__ */
extern int dcache_bsize;

6
arch/powerpc/include/asm/mmu.h
View File

@ -52,12 +52,6 @@
*/
#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
/* This indicates that the processor uses the wrong opcode for tlbilx
* instructions. During the ISA 2.06 development the opcode for tlbilx
* changed and some early implementations used to old opcode
*/
#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000)
#ifndef __ASSEMBLY__
#include <asm/cputable.h>

11
arch/powerpc/include/asm/ppc-opcode.h
View File

@ -44,7 +44,6 @@
#define PPC_INST_STSWI 0x7c0005aa
#define PPC_INST_STSWX 0x7c00052a
#define PPC_INST_TLBILX 0x7c000024
#define PPC_INST_TLBILX_EARLY 0x7c000626
#define PPC_INST_WAIT 0x7c00007c
/* macros to insert fields into opcodes */
@ -64,18 +63,10 @@
#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
__PPC_T_TLB(t) | \
__PPC_RA(a) | __PPC_RB(b))
__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \
__PPC_T_TLB(t) | \
__PPC_RA(a) | __PPC_RB(b))
#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b)
#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b)
#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b)
#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
__PPC_WC(w))

2
arch/powerpc/kernel/cputable.c
View File

@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_E500MC,
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE,
MMU_FTR_USE_TLBILX,
.icache_bsize = 64,
.dcache_bsize = 64,
.num_pmcs = 4,

16
arch/powerpc/mm/tlb_nohash_low.S
View File

@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION
andi. r3,r3,MMUCSR0_TLBFI@l
bne 1b
MMU_FTR_SECTION_ELSE
BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_ALL(0,r3)
MMU_FTR_SECTION_ELSE_NESTED(96)
PPC_TLBILX_ALL_EARLY(0,r3)
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
PPC_TLBILX_ALL(0,0)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION
wrteei 0
mfspr r4,SPRN_MAS6 /* save MAS6 */
mtspr SPRN_MAS6,r3
BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_PID(0,0)
MMU_FTR_SECTION_ELSE_NESTED(96)
PPC_TLBILX_PID_EARLY(0,0)
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
mtspr SPRN_MAS6,r4 /* restore MAS6 */
wrtee r10
MMU_FTR_SECTION_ELSE
@ -193,16 +185,12 @@ BEGIN_MMU_FTR_SECTION
mtspr SPRN_MAS1,r4
tlbwe
MMU_FTR_SECTION_ELSE
BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_VA(0,r3)
MMU_FTR_SECTION_ELSE_NESTED(96)
PPC_TLBILX_VA_EARLY(0,r3)
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
1: wrtee r10
blr
#elif
#else
#error Unsupported processor type !
#endif

5
arch/powerpc/platforms/cell/Kconfig
View File

@ -13,7 +13,6 @@ config PPC_CELL_COMMON
config PPC_CELL_NATIVE
bool
select PPC_CELL_COMMON
select PPC_OF_PLATFORM_PCI
select MPIC
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
@ -25,6 +24,8 @@ config PPC_IBM_CELL_BLADE
bool "IBM Cell Blade"
depends on PPC64 && PPC_BOOK3S
select PPC_CELL_NATIVE
select PPC_OF_PLATFORM_PCI
select PCI
select MMIO_NVRAM
select PPC_UDBG_16550
select UDBG_RTAS_CONSOLE
@ -33,6 +34,8 @@ config PPC_CELLEB
bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
depends on PPC64 && PPC_BOOK3S
select PPC_CELL_NATIVE
select PPC_OF_PLATFORM_PCI
select PCI
select HAS_TXX9_SERIAL
select PPC_UDBG_BEAT
select USB_OHCI_BIG_ENDIAN_MMIO

4
arch/powerpc/platforms/ps3/setup.c
View File

@ -45,10 +45,6 @@
DEFINE_MUTEX(ps3_gpu_mutex);
EXPORT_SYMBOL_GPL(ps3_gpu_mutex);
#if !defined(CONFIG_SMP)
static void smp_send_stop(void) {}
#endif
static union ps3_firmware_version ps3_firmware_version;
void ps3_get_firmware_version(union ps3_firmware_version *v)